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  • DRV8316 三相集成式 FET 电机驱动器

    • ZHCSN76B January   2021  – April 2022 DRV8316

      PRODUCTION DATA  

  • CONTENTS
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  • DRV8316 三相集成式 FET 电机驱动器
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 SPI Timing Requirements
    7. 7.7 SPI Slave Mode Timings
    8. 7.8 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Output Stage
      2. 8.3.2  Control Modes
        1. 8.3.2.1 6x PWM Mode (MODE = 00b or MODE Pin Tied to AGND)
        2. 8.3.2.2 3x PWM Mode (MODE = 10b or MODE Pin is Connected to AGND with RMODE)
        3. 8.3.2.3 Current Limit Mode (MODE = 01b / 11b or MODE Pin is Hi-Z or Connected to AVDD)
      3. 8.3.3  Device Interface Modes
        1. 8.3.3.1 Serial Peripheral Interface (SPI)
        2. 8.3.3.2 Hardware Interface
      4. 8.3.4  Step-Down Mixed-Mode Buck Regulator
        1. 8.3.4.1 Buck in Inductor Mode
        2. 8.3.4.2 Buck in Resistor mode
        3. 8.3.4.3 Buck Regulator with External LDO
        4. 8.3.4.4 AVDD Power Sequencing on Buck Regulator
        5. 8.3.4.5 Mixed mode Buck Operation and Control
      5. 8.3.5  AVDD Linear Voltage Regulator
      6. 8.3.6  Charge Pump
      7. 8.3.7  Slew Rate Control
      8. 8.3.8  Cross Conduction (Dead Time)
      9. 8.3.9  Propagation Delay
        1. 8.3.9.1 Driver Delay Compensation
      10. 8.3.10 Pin Diagrams
        1. 8.3.10.1 Logic Level Input Pin (Internal Pulldown)
        2. 8.3.10.2 Logic Level Input Pin (Internal Pullup)
        3. 8.3.10.3 Open Drain Pin
        4. 8.3.10.4 Push Pull Pin
        5. 8.3.10.5 Four Level Input Pin
      11. 8.3.11 Current Sense Amplifiers
        1. 8.3.11.1 Current Sense Amplifier Operation
        2. 8.3.11.2 Current Sense Amplifier Offset Correction
      12. 8.3.12 Active Demagnetization
        1. 8.3.12.1 Automatic Synchronous Rectification Mode (ASR Mode)
          1. 8.3.12.1.1 Automatic Synchronous Rectification in Commutation
          2. 8.3.12.1.2 Automatic Synchronous Rectification in PWM Mode
        2. 8.3.12.2 Automatic Asynchronous Rectification Mode (AAR Mode)
      13. 8.3.13 Cycle-by-Cycle Current Limit
        1. 8.3.13.1 Cycle by Cycle Current Limit with 100% Duty Cycle Input
      14. 8.3.14 Protections
        1. 8.3.14.1 VM Supply Undervoltage Lockout (NPOR)
        2. 8.3.14.2 AVDD Undervoltage Lockout (AVDD_UV)
        3. 8.3.14.3 BUCK Undervoltage Lockout (BUCK_UV)
        4. 8.3.14.4 VCP Charge Pump Undervoltage Lockout (CPUV)
        5. 8.3.14.5 Overvoltage Protections (OV)
        6. 8.3.14.6 Overcurrent Protection (OCP)
          1. 8.3.14.6.1 OCP Latched Shutdown (OCP_MODE = 00b)
          2. 8.3.14.6.2 OCP Automatic Retry (OCP_MODE = 01b)
          3. 8.3.14.6.3 OCP Report Only (OCP_MODE = 10b)
          4. 8.3.14.6.4 OCP Disabled (OCP_MODE = 11b)
        7. 8.3.14.7 Buck Overcurrent Protection
        8. 8.3.14.8 Thermal Warning (OTW)
        9. 8.3.14.9 Thermal Shutdown (OTS)
          1. 8.3.14.9.1 OTS FET
          2. 8.3.14.9.2 OTS (Non FET)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Functional Modes
        1. 8.4.1.1 Sleep Mode
        2. 8.4.1.2 Operating Mode
        3. 8.4.1.3 Fault Reset (CLR_FLT or nSLEEP Reset Pulse)
      2. 8.4.2 DRVOFF functionality
    5. 8.5 SPI Communication
      1. 8.5.1 Programming
        1. 8.5.1.1 SPI Format
    6. 8.6 Register Map
      1. 8.6.1 STATUS Registers
      2. 8.6.2 CONTROL Registers
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Three-Phase Brushless-DC Motor Control
        1. 9.2.1.1 Detailed Design Procedure
          1. 9.2.1.1.1 Motor Voltage
          2. 9.2.1.1.2 Using Active Demagnetization
          3. 9.2.1.1.3 Driver Propagation Delay and Dead Time
          4. 9.2.1.1.4 Using Delay Compensation
          5. 9.2.1.1.5 Using the Buck Regulator
          6. 9.2.1.1.6 Current Sensing and Output Filtering
          7. 9.2.1.1.7 Power Dissipation and Junction Temperature Losses
        2. 9.2.1.2 Application Curves
      2. 9.2.2 Three-Phase Brushless-DC Motor Control With Current Limit
        1. 9.2.2.1 Block Diagram
        2. 9.2.2.2 Detailed Design Procedure
          1. 9.2.2.2.1 Motor Voltage
          2. 9.2.2.2.2 ILIM Implementation
        3. 9.2.2.3 Application Curves
      3. 9.2.3 Brushed-DC and Solenoid Load
        1. 9.2.3.1 Block Diagram
        2. 9.2.3.2 Design Requirements
          1. 9.2.3.2.1 Detailed Design Procedure
      4. 9.2.4 Three Solenoid Loads
        1. 9.2.4.1 Block Diagram
        2. 9.2.4.2 Design Requirements
          1. 9.2.4.2.1 Detailed Design Procedure
  10. 10Power Supply Recommendations
    1. 10.1 Bulk Capacitance
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
    3. 11.3 Thermal Considerations
      1. 11.3.1 Power Dissipation
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information
  14. 重要声明
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DATA SHEET

DRV8316 三相集成式 FET 电机驱动器

本资源的原文使用英文撰写。 为方便起见,TI 提供了译文;由于翻译过程中可能使用了自动化工具,TI 不保证译文的准确性。 为确认准确性,请务必访问 ti.com 参考最新的英文版本(控制文档)。

1 特性

  • 的三相 BLDC 电机驱动器
  • 4.5V 至 35V 工作电压(绝对最大值 40V)
  • 高输出电流能力:8A 峰值
  • 低 MOSFET 导通状态电阻
    • TA = 25°C 时,RDS(ON) (HS + LS) 为 95 mΩ
  • 低功耗睡眠模式
    • 1.5 µA(VVM = 24V,TA = 25°C)
  • 多种控制接口选项
    • 6x PWM 控制接口
    • 3x PWM 控制接口
    • 具有逐周期电流限制的 6x PWM 控制接口
    • 具有逐周期电流限制的 3x PWM 控制接口
  • 不需要外部电流感测电阻器,内置电流感测功能
  • 灵活的器件配置选项
    • DRV8316R:用于器件配置和故障状态的 5 MHz 16 位 SPI 接口
    • DRV8316T:基于硬件引脚的配置
  • 支持 1.8V、3.3V 和 5V 逻辑输入
  • 内置 3.3V (5%)、30 mA LDO 稳压器
  • 内置 3.3V/5V、200 mA 降压稳压器
  • 延迟补偿减少占空比失真
  • 整套集成保护特性
    • 电源欠压锁定 (UVLO)
    • 电荷泵欠压 (CPUV)
    • 过流保护 (OCP)
    • 热警告和热关断 (OTW/OTSD)
    • 故障条件指示引脚 (nFAULT)
    • 可选择通过 SPI 接口进行故障诊断

2 应用

  • CPAP 呼吸机
  • 无刷直流 (BLDC) 电机模块
  • 打印机
  • 云台相机
  • HVAC 电机
  • 小型家用电器
  • 办公自动化设备
  • 工厂自动化和机器人

3 说明

DRV8316 为要驱动 12V 至 24V 有刷直流电机的客户提供了一种单芯片功率级解决方案。DRV8316 集成了三个 1/2 H 桥,具有 40V 的绝对最大电压和 95 mΩ 的超低 RDS(ON)(高侧 + 低侧),可提供大功率驱动能力。使用集成电流感应功能感测电流,无需外部电流检测电阻器。可调降压稳压器和 LDO 的电源管理性能为器件生成必要的电压轨,可用于为外部电路供电。

DRV8316 实现了 6x 或 3x PWM 控制方案,可用于通过外部微控制器实现有传感器或无传感器磁场定向控制 (FOC)、正弦控制或梯形控制。DRV8316 能够驱动高达 200 kHz 的 PWM 频率。该控制方案具有高度可配置性,可通过硬件引脚或寄存器设置进行配置,涵盖范围从电机电流限制行为到故障响应。

每个输出驱动器通道包含采用半桥配置的 N 通道功率 MOSFET。该器件支持各种 PWM 控制模式,从而使用简单接口连接到可通过 30 mA、3.3V 内部稳压器 (AVDD) 供电的控制电路。DRV8316R/T 还支持降压稳压器,与可编程的稳压电源结合使用可以支持 200 mA 电流。该器件支持 200 kHz 的最大 PWM 频率。

DRV8316 集成多种保护特性,旨在出现故障事件时保护器件、电机和系统。

有关器件使用的设计考虑因素和建议,请参考Section 9.1。

器件信息(1)
器件型号 封装 封装尺寸(标称值)
DRV8316R VQFN (40) 7.00mm x 5.00mm
DRV8316T(2) VQFN (40) 7.00mm x 5.00mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附录。
(2) 器件仅为预发布版。
简化版原理图

4 Revision History

Changes from Revision A (May 2021) to Revision B (April 2022)

  • 将器件状态更新为“量产数据”。Go

Changes from Revision * (January 2021) to Revision A (May 2021)

  • Updated the charge pump fly cap value from 10 nF to 47 nFGo

5 Device Comparison Table

DEVICE PACKAGES INTERFACE BUCK REGULATOR
DRV8316R 40-pin VQFN (7x5 mm) SPI Yes
DRV8316T(2) Hardware
(2) Device available for preview only.

6 Pin Configuration and Functions

Figure 6-1 DRV8316R40-Pin VQFN With Exposed Thermal PadTop View
Figure 6-2 DRV8316T40-Pin VQFN With Exposed Thermal PadTop View
Table 6-1 Pin Functions
PIN 40-pin Package TYPE(1) DESCRIPTION
NAME DRV8316R DRV8316T
AGND 2, 26 2, 26 GND Device analog ground. Refer Section 11.1 for connections recommendation.
AVDD 25 25 PWR O 3.3-V internal regulator output. Connect an X5R or X7R, 1-µF, 6.3-V ceramic capacitor between the AVDD and AGND pins. This regulator can source up to 30 mA externally.
CP 8 8 PWR O Charge pump output. Connect a X5R or X7R, 1-µF, 16-V ceramic capacitor between the CP and VM pins.
CPH 7 7 PWR Charge pump switching node. Connect a X5R or X7R, 47-nF, ceramic capacitor between the CPH and CPL pins. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device.
CPL 6 6 PWR
DRVOFF 21 21 I When this pin is pulled high the six MOSFETs in the power stage are turned OFF making all outputs Hi-Z.
FB_BK 3 3 PWR I Feedback for buck regulator. Connect to buck regulator output after the inductor/resistor.
GAIN — 36 I Amplifier gain setting. The pin is a 4 level input pin set by an external resistor.
GND_BK 4 4 GND Buck regulator ground. Refer Section 11.1 for connections recommendation.
INHA 27 27 I High-side driver control input for OUTA. This pin controls the output of the high-side MOSFET.
INHB 29 29 I High-side driver control input for OUTB. This pin controls the output of the high-side MOSFET.
INHC 31 31 I High-side driver control input for OUTC. This pin controls the output of the high-side MOSFET.
INLA 28 28 I Low-side driver control input for OUTA. This pin controls the output of the low-side MOSFET.
INLB 30 30 I Low-side driver control input for OUTB. This pin controls the output of the low-side MOSFET.
INLC 32 32 I Low-side driver control input for OUTC. This pin controls the output of the low-side MOSFET.
MODE — 33 I PWM input mode setting. This pin is a 2-level input pin set by an external resistor.
NC 1, 24 1 — No connection, open
nFAULT 22 22 O Fault indicator. Pulled logic-low with fault condition; Open-drain output requires an external pull-up resistor to 1.8 V to 5.0 V. If external supply is used to pull up nFAULT, ensure that it is pulled to >2.2 V on power up or the device will enter test mode
nSCS 36 — I Serial chip select. A logic low on this pin enables serial interface communication.
nSLEEP 23 23 I Driver nSLEEP. When this pin is logic low, the device goes into a low-power sleep mode. An 20 to 40-µs low pulse can be used to reset fault conditions without entering sleep mode.
OCP — 35 I OCP level setting. This pin is a 2 level input pin set by an external resistor (Hardware devices).
OUTA 13, 14 13, 14 PWR O Half bridge output A
OUTB 16, 17 16, 17 PWR O Half bridge output B
OUTC 19, 20 19, 20 PWR O Half bridge output C
PGND 12, 15, 18 12, 15, 18 GND Device power ground. Refer Section 11.1 for connections recommendation.
SCLK 35 — I Serial clock input. Serial data is shifted out and captured on the corresponding rising and falling edge on this pin (SPI devices).
SDI 34 — I Serial data input. Data is captured on the falling edge of the SCLK pin (SPI devices).
SDO 33 — O Serial data output. Data is shifted out on the rising edge of the SCLK pin. This pin requires an external pullup resistor (SPI devices).
SLEW — 34 I Slew rate control setting. This pin is a 4-level input pin set by an external resistor.
SOA 40 40 O Current sense amplifier output. Supports capacitive load or low pass filter (resistor in series and capacitor to GND)
SOB 39 39 O Current sense amplifier output. Supports capacitive load or low pass filter (resistor in series and capacitor to GND)
SOC 38 38 O Current sense amplifier output. Supports capacitive load or low pass filter (resistor in series and capacitor to GND)
SW_BK 5 5 PWR O Buck switch node. Connect this pin to an inductor or resistor.
VM 9, 10, 11 9, 10, 11 PWR I Power supply. Connect to motor supply voltage; bypass to PGND with two 0.1-µF capacitors (for each pin) plus one bulk capacitor rated for VM. TI recommends a capacitor voltage rating at least twice the normal operating voltage of the device.
VSEL_BK — 24 I Buck output voltage setting. This pin is a 4-level input pin set by an external resistor.
VREF/ILIM 37 37 PWR/I VREF in PWM Mode 1 and Mode 3: Current sense amplifier power supply input and reference. Connect a X5R or X7R, 0.1-µF, 6.3-V ceramic capacitor between the VREF and AGND pins.
ILIM in PWM Mode 2 and Mode4: Sets the threshold for phase current used in cycle by cycle current limit.
Thermal pad GND Must be connected to analog ground.
(1) I = input, O = output, GND = ground pin, PWR = power, NC = no connect

7 Specifications

 

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