Data Sheet
TPS748 具有可编程软启动功能的 1.5A 低压降线性稳压器
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1 特性
- VOUT 范围：0.8V 至 3.6V
- 超低 VIN 范围：0.8V 至 5.5V
- VBIAS 范围：2.7V 至 5.5V
- 低压降：1.5A、VBIAS = 5V 下的典型值为 60mV
- 电源正常 (PG) 输出可实现电源监视或为其他电源提供时序信号
- 线路、负载和温度范围内的精度为 1%（新芯片）
- 线路、负载和温度范围内的精度为 2%（旧芯片）
- 可编程软启动可提供线性电压启动
- VBIAS 支持低 VIN 运行，具有良好的瞬态响应
- 任何输出电容器 ≥ 2.2μF 时保持稳定
- 采用小型 3mm × 3mm × 1mm VSON-10 封装和 5mm × 5mm VQFN-20 封装
3 说明
TPS748 低压降 (LDO) 线性稳压器可面向多种应用提供易于使用的稳健型电源管理解决方案。用户可编程软启动通过减少启动时的电容涌入电流，最大限度地减少了输入电源上的应力。软启动具有单调性，旨在为各类处理器和 ASIC 供电。借助使能输入和电源正常输出，可通过外部稳压器轻松实现上电排序。凭借全方位的灵活性，该器件可为 FPGA、DSP 等具有特殊启动要求的应用配置可满足其时序要求的解决方案。
具有精密基准的误差放大器可在整个负载、线路、温度和过程范围内提供 1% 精度（新芯片）。该器件在使用大于或等于 2.2μF 的任何类型的电容器时都能保持稳定运行，并具有 TJ = –40°C 至 +125°C 的额定结温范围。TPS748 采用小型 3mm × 3mm VSON-10 封装，可实现高度紧凑的解决方案总尺寸。该器件还可采用 5mm × 5mm VQFN-20 封装，从而与 TPS742 兼容。
(1) 如需更多信息，请参阅机械、封装和可订购信息。
(2) 封装尺寸（长 × 宽）为标称值，并包括引脚（如适用）。
典型应用电路（可调节）
导通响应4 Pin Configuration and Functions
Figure 4-1 DRC Package,10-Pin VSON With Thermal Pad(Top
View)
Figure 4-2 RGW Package,20-Pin VQFN(Top View)Table 4-1 Pin Functions
| PIN | I/O | DESCRIPTION | ||
|---|---|---|---|---|
| NAME | VSON | VQFN | ||
| BIAS | 4 | 10 | I | Bias input voltage for error amplifier, reference, and internal control circuits. A 1-µF or larger input capacitor is recommended for optimal performance. If IN is connected to BIAS, a 4.7-µF or larger capacitor must be used. |
| EN | 5 | 11 | I | Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode. This pin must not be left unconnected. |
| FB | 8 | 16 | I | Feedback pin. The feedback connection to the center tap of an external resistor divider network that sets the output voltage. This pin must not be left floating. |
| GND | 6 | 12 | — | Ground |
| IN | 1, 2 | 5-8 | I | Input to the device. A 1-µF or larger input capacitor is recommended for optimal performance. |
| NC | N/A | 2-4, 13, 14, 17 | — | No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane. |
| OUT | 9, 10 | 1, 18-20 | O | Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2 μF, ceramic) is needed from this pin to ground to assure stability. |
| PG | 3 | 9 | O | Power Good pin. An open-drain, active-high output that indicates the status of VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When VOUT is below this threshold the pin is driven to a low-impedance state. A pull-up resistor from 10 kΩ to 1 MΩ should be connected from this pin to a supply of up to 5.5 V. The supply can be higher than the input voltage. Alternatively, the PG pin can be left unconnected if output monitoring is not necessary. |
| SS | 7 | 15 | — | Soft-Start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left unconnected, the regulator output soft-start ramp time is typically 200 μs. |
| Thermal pad | — | Must be soldered to the ground plane for increased thermal performance. Internally connected to ground. | ||
5 Specifications
5.1 Absolute Maximum Ratings
over operating temperature range (unless otherwise noted)(1)
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| VIN, VBIAS | Input voltage | –0.3 | 6 | V |
| VEN | Enable voltage | –0.3 |
6 |
V |
| VPG | Power-good voltage | –0.3 | 6 | V |
| IPG | PG sink current | 0 | 1.5 | mA |
| VSS | Soft-start voltage | –0.3 |
6 |
V |
| VFB | Feedback voltage | –0.3 |
6 |
V |
| VOUT | Output voltage | –0.3 | VIN + 0.3 | V |
| IOUT | Maximum output current | Internally limited | ||
| Output short-circuit duration | Indefinite | |||
| PDISS | Continuous total power dissipation | See Thermal Information | ||
| TJ | Junction Temperature | –40 | 150 | °C |
| Tstg | Storage Temperature | –55 | 150 | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
5.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
| Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| VIN | Input supply voltage | VOUT + VDO (VIN) | VOUT + 0.3 | 5.5 | V |
| VEN | Enable supply voltage | VIN | 5.5 | V | |
| VBIAS(1) | BIAS supply voltage | VOUT + VDO (VBIAS)(2) | VOUT + 1.6(2) | 5.5 | V |
| VOUT | Output voltage | 0.8 | 3.3 | V | |
| IOUT | Output current | 0 | 1.5 | A | |
| COUT | Output capacitor | 2.2 | µF | ||
| CIN | Input capacitor(3) | 1 | µF | ||
| CBIAS | Bias capacitor | 0.1 | 1 | µF | |
| TJ | Operating junction temperature | –40 | 125 | ℃ | |
(1) BIAS supply is required when VIN is below VOUT + 1.62 V.
(2) VBIAS has a minimum voltage of 2.7 V or VOUT + VDO (VBIAS), whichever is higher.
(3) If VIN and VBIAS are connected to the same supply, the recommended minimum capacitor for the supply is 4.7 μF.
