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TPS748 低压降 (LDO) 线性稳压器可面向多种应用提供易于使用的稳健型电源管理解决方案。用户可编程软启动通过减少启动时的电容涌入电流,最大限度地减少了输入电源上的应力。软启动具有单调性,旨在为各类处理器和 ASIC 供电。借助使能输入和电源正常输出,可通过外部稳压器轻松实现上电排序。凭借全方位的灵活性,该器件可为 FPGA、DSP 等具有特殊启动要求的应用配置可满足其时序要求的解决方案。
具有精密基准的误差放大器可在整个负载、线路、温度和过程范围内提供 1% 精度(新芯片)。该器件在使用大于或等于 2.2μF 的任何类型的电容器时都能保持稳定运行,并具有 TJ = –40°C 至 +125°C 的额定结温范围。TPS748 采用小型 3mm × 3mm VSON-10 封装,可实现高度紧凑的解决方案总尺寸。该器件还可采用 5mm × 5mm VQFN-20 封装,从而与 TPS742 兼容。
PIN | I/O | DESCRIPTION | ||
---|---|---|---|---|
NAME | VSON | VQFN | ||
BIAS | 4 | 10 | I | Bias input voltage for error amplifier, reference, and internal control circuits. A 1-µF or larger input capacitor is recommended for optimal performance. If IN is connected to BIAS, a 4.7-µF or larger capacitor must be used. |
EN | 5 | 11 | I | Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode. This pin must not be left unconnected. |
FB | 8 | 16 | I | Feedback pin. The feedback connection to the center tap of an external resistor divider network that sets the output voltage. This pin must not be left floating. |
GND | 6 | 12 | — | Ground |
IN | 1, 2 | 5-8 | I | Input to the device. A 1-µF or larger input capacitor is recommended for optimal performance. |
NC | N/A | 2-4, 13, 14, 17 | — | No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane. |
OUT | 9, 10 | 1, 18-20 | O | Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2 μF, ceramic) is needed from this pin to ground to assure stability. |
PG | 3 | 9 | O | Power Good pin. An open-drain, active-high output that indicates the status of VOUT. When VOUT exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When VOUT is below this threshold the pin is driven to a low-impedance state. A pull-up resistor from 10 kΩ to 1 MΩ should be connected from this pin to a supply of up to 5.5 V. The supply can be higher than the input voltage. Alternatively, the PG pin can be left unconnected if output monitoring is not necessary. |
SS | 7 | 15 | — | Soft-Start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left unconnected, the regulator output soft-start ramp time is typically 200 μs. |
Thermal pad | — | Must be soldered to the ground plane for increased thermal performance. Internally connected to ground. |
MIN | MAX | UNIT | ||
---|---|---|---|---|
VIN, VBIAS | Input voltage | –0.3 | 6 | V |
VEN | Enable voltage | –0.3 |
6 |
V |
VPG | Power-good voltage | –0.3 | 6 | V |
IPG | PG sink current | 0 | 1.5 | mA |
VSS | Soft-start voltage | –0.3 |
6 |
V |
VFB | Feedback voltage | –0.3 |
6 |
V |
VOUT | Output voltage | –0.3 | VIN + 0.3 | V |
IOUT | Maximum output current | Internally limited | ||
Output short-circuit duration | Indefinite | |||
PDISS | Continuous total power dissipation | See Thermal Information | ||
TJ | Junction Temperature | –40 | 150 | °C |
Tstg | Storage Temperature | –55 | 150 |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 |
MIN | NOM | MAX | UNIT | ||
---|---|---|---|---|---|
VIN | Input supply voltage | VOUT + VDO (VIN) | VOUT + 0.3 | 5.5 | V |
VEN | Enable supply voltage | VIN | 5.5 | V | |
VBIAS(1) | BIAS supply voltage | VOUT + VDO (VBIAS)(2) | VOUT + 1.6(2) | 5.5 | V |
VOUT | Output voltage | 0.8 | 3.3 | V | |
IOUT | Output current | 0 | 1.5 | A | |
COUT | Output capacitor | 2.2 | µF | ||
CIN | Input capacitor(3) | 1 | µF | ||
CBIAS | Bias capacitor | 0.1 | 1 | µF | |
TJ | Operating junction temperature | –40 | 125 | ℃ |
THERMAL METRIC(1) | TPS748 | UNIT | ||||
---|---|---|---|---|---|---|
RGW (VQFN) | RGW (VQFN)(2) | DRC (VSON) | DRC (VSON) (2) | |||
20 PINS | 20 PINS | 10 PINS | 10 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 35.6 | 34.7 | 44.2 | 47.2 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 33.3 | 31.0 | 50.3 | 63.7 | °C/W |
RθJB | Junction-to-board thermal resistance | 15 | 13.5 | 19.6 | 19.5 | °C/W |
ψJT | Junction-to-top characterization parameter | 0.4 | 1.4 | 0.7 | 4.2 | °C/W |
ψJB | Junction-to-board characterization parameter | 15.2 | 13.5 | 17.8 | 19.4 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | 3.8 | 3.6 | 4.3 | 3.3 | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|---|---|
VREF | Internal reference (Adj.) | TA = 25°C | 0.796 | 0.8 | 0.804 | V | ||
VOUT | Output voltage range | VIN = 5 V, IOUT = 1.5 A | VREF | 3.6 | V | |||
Accuracy(1) | 2.97 V ≤ VBIAS ≤ 5.5 V, 50 mA ≤ IOUT ≤ 1.5 A (Legacy Chip) | –2 | ±0.5 | 2 | % | |||
2.97 V ≤ VBIAS ≤ 5.5 V, 50 mA ≤ IOUT ≤ 1.5 A (New Chip) | –1 | ±0.3 | 1 | |||||
ΔVOUT(ΔVIN) | Line regulation | VOUT(nom) + 0.3 ≤ VIN ≤ 5.5 V (Legacy Chip) | 0.03 | %/V | ||||
VOUT(nom) + 0.3 ≤ VIN ≤ 5.5 V (New Chip) | 0.001 | |||||||
ΔVOUT(ΔIOUT) | Load regulation | 50 mA ≤ IOUT ≤ 1.5 A | 0.09 | %/A | ||||
VDO | VIN dropout voltage(2) | IOUT = 1.5 A, VBIAS – VOUT(nom) ≥ 3.25 V (Legacy Chip) (3) | 60 | 165 | mV | |||
IOUT = 1.5 A, VBIAS – VOUT(nom) ≥ 3.25 V (New Chip) (3) | 50 | 100 | ||||||
VBIAS dropout voltage(2) | IOUT = 1.5 A, VIN = VBIAS (Legacy Cip) | 1.31 | 1.6 | V | ||||
IOUT = 1.5 A, VIN = VBIAS (New Chip) | 1.31 | 1.43 | ||||||
ICL | Output current limit | VOUT = 80% × VOUT(nom) | 2 | 5.5 | A | |||
IBIAS | BIAS pin current | (Legacy Chip) | 1 | 2 | mA | |||
(New Chip) | 1 | 1.2 | ||||||
ISHDN | Shutdown supply current (IGND) | VEN ≤ 0.4 V (Legacy Chip) | 1 | 50 | µA | |||
VEN ≤ 0.4 V (New Chip) | 0.85 | 2.75 | ||||||
IFB | Feedback pin current | (Legacy Chip) | –1 | 0.15 | 1 | µA | ||
(New Chip) | –30 | 0.15 | 30 | nA | ||||
PSRR | Power-supply rejection (VIN to VOUT) | 1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V | 60 | dB | ||||
300 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V | 30 | |||||||
Power-supply rejection (VBIAS to VOUT) | 1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V (Legacy Chip) | 50 | ||||||
1 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V (New Chip) | 59 | |||||||
300 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V (Legacy Chip) | 30 | |||||||
300 kHz, IOUT = 1.5 A, VIN = 1.8 V, VOUT = 1.5 V (New Chip) | 50 | |||||||
Vn | Output noise voltage | BW = 100 Hz to 100 kHz, IOUT = 1.5 A, CSS = 1 nF (Legacy Chip) | 25 × VOUT | μVrms | ||||
BW = 100 Hz to 100 kHz, IOUT = 1.5 A, CSS = 1 nF (New Chip) | 20 × VOUT | |||||||
tSTR | Minimum startup time | RLOAD for IOUT = 1.0 A, CSS = open (Legacy Chip) | 200 | µs | ||||
RLOAD for IOUT = 1.0 A, CSS = open (New Chip) | 250 | |||||||
ISS | Soft-start charging current | VSS = 0.4 V (Legacy Chip) | 440 | nA | ||||
VSS = 0.4 V (New Chip) | 530 | |||||||
VEN(hi) | Enable input high level | 1.1 | 5.5 | V | ||||
VEN(lo) | Enable input low level | 0 | 0.4 | V | ||||
VEN(hys) | Enable pin hysteresis | (Legacy Chip) | 50 | mV | ||||
(New Chip) | 55 | |||||||
VEN(dg) | Enable pin deglitch time | 20 | µs | |||||
IEN | Enable pin current | VEN = 5 V (Legacy Chip) | 0.1 | 1 | µA | |||
VEN = 5 V (New Chip) | 0.1 | 0.3 | ||||||
VIT | PG trip threshold | VOUT decreasing | 85 | 90 | 94 | %VOUT | ||
VHYS | PG trip hysteresis | 3 | %VOUT | |||||
VPG(lo) | PG output low voltage | IPG = 1 mA (sinking), VOUT < VIT (Legacy Chip) | 0.3 | V | ||||
IPG = 1 mA (sinking), VOUT < VIT (New Chip) | 0.125 | |||||||
IPG(lkg) | PG leakage current | VPG = 5.25 V, VOUT > VIT (Legacy Chip) | 0.1 | 1 | µA | |||
VPG = 5.25 V, VOUT > VIT (New Chip) | 0.001 | 0.05 | ||||||
TSD | Thermal shutdown temperature | Shutdown, temperature increasing | 165 | ℃ | ||||
Reset, temperature decreasing | 140 | |||||||
RPULLDOWN | Output pulldown resitance | VBIAS = 5V, VEN = 0V | 0.83 | 1 | kΩ |
at TJ = 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, IOUT = 50 mA, VEN = VIN, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF (unless otherwise noted)
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at TJ = 25°C, VIN = VOUT(nom) + 0.3 V, VBIAS = 5 V, IOUT = 1 A, VEN = VIN = 1.8 V, VOUT = 1.5 V, CIN = 1 μF, CBIAS = 4.7 μF, and COUT = 10 μF (unless otherwise noted)
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The TPS748 is a low-dropout regulator that features soft-start capability. This regulator uses a low current bias input to power all internal control circuitry, allowing the NMOS pass transistor to regulate very low input and output voltages.
The use of an NMOS-pass transistor offers several critical advantages for many applications. Unlike a PMOS topology device, the output capacitor has little effect on loop stability. This architecture allows the TPS748 to be stable with any capacitor type of value 2.2 μF or greater. Transient response is also superior to PMOS topologies, particularly for low VIN applications.
The TPS748 features a programmable voltage-controlled soft-start circuit that provides a smooth, monotonic start-up and limits start-up inrush currents that may be caused by large capacitive loads. A power-good (PG) output is available to allow supply monitoring and sequencing of other supplies. An enable (EN) pin with hysteresis and deglitch allows slow-ramping signals to be used for sequencing the device. The low VIN and VOUT capability allows for inexpensive, easy-to-design, and efficient linear regulation between the multiple supply voltages often required by processor-intensive systems.