TPS748 具有可编程软启动功能的 1.5A 低压降线性稳压器
- ZHCSN49N January 2007 – June 2024 TPS74801
  
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TPS748 具有可编程软启动功能的 1.5A 低压降线性稳压器

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1 特性

V_OUT 范围：0.8V 至 3.6V
超低 V_IN 范围：0.8V 至 5.5V
V_BIAS 范围：2.7V 至 5.5V
低压降：1.5A、V_BIAS = 5V 下的典型值为 60mV
电源正常 (PG) 输出可实现电源监视或为其他电源提供时序信号
线路、负载和温度范围内的精度为 1%（新芯片）
线路、负载和温度范围内的精度为 2%（旧芯片）
可编程软启动可提供线性电压启动
V_BIAS 支持低 V_IN 运行，具有良好的瞬态响应
任何输出电容器 ≥ 2.2μF 时保持稳定
采用小型 3mm × 3mm × 1mm VSON-10 封装和 5mm × 5mm VQFN-20 封装

2 应用

3 说明

TPS748 低压降 (LDO) 线性稳压器可面向多种应用提供易于使用的稳健型电源管理解决方案。用户可编程软启动通过减少启动时的电容涌入电流，最大限度地减少了输入电源上的应力。软启动具有单调性，旨在为各类处理器和 ASIC 供电。借助使能输入和电源正常输出，可通过外部稳压器轻松实现上电排序。凭借全方位的灵活性，该器件可为 FPGA、DSP 等具有特殊启动要求的应用配置可满足其时序要求的解决方案。

具有精密基准的误差放大器可在整个负载、线路、温度和过程范围内提供 1% 精度（新芯片）。该器件在使用大于或等于 2.2μF 的任何类型的电容器时都能保持稳定运行，并具有 T_J = –40°C 至 +125°C 的额定结温范围。TPS748 采用小型 3mm × 3mm VSON-10 封装，可实现高度紧凑的解决方案总尺寸。该器件还可采用 5mm × 5mm VQFN-20 封装，从而与 TPS742 兼容。

封装信息

器件型号	封装⁽¹⁾	封装尺寸⁽²⁾
TPS748	DRC（VSON，10）	3mm × 3mm
TPS748	RGW（VQFN，20）	5mm × 5mm

(1) 如需更多信息，请参阅机械、封装和可订购信息。

(2) 封装尺寸（长 × 宽）为标称值，并包括引脚（如适用）。

典型应用电路（可调节）

导通响应

4 Pin Configuration and Functions

TPS748 DRC Package,10-Pin VSON With Thermal Pad(Top
View)

Figure 4-1 DRC Package,10-Pin VSON With Thermal Pad(Top View)

TPS748 RGW Package,20-Pin VQFN(Top View)

Figure 4-2 RGW Package,20-Pin VQFN(Top View)

Table 4-1 Pin Functions

PIN			I/O	DESCRIPTION
NAME	VSON	VQFN	I/O	DESCRIPTION
BIAS	4	10	I	Bias input voltage for error amplifier, reference, and internal control circuits. A 1-µF or larger input capacitor is recommended for optimal performance. If IN is connected to BIAS, a 4.7-µF or larger capacitor must be used.
EN	5	11	I	Enable pin. Driving this pin high enables the regulator. Driving this pin low puts the regulator into shutdown mode. This pin must not be left unconnected.
FB	8	16	I	Feedback pin. The feedback connection to the center tap of an external resistor divider network that sets the output voltage. This pin must not be left floating.
GND	6	12	—	Ground
IN	1, 2	5-8	I	Input to the device. A 1-µF or larger input capacitor is recommended for optimal performance.
NC	N/A	2-4, 13, 14, 17	—	No connection. This pin can be left floating or connected to GND to allow better thermal contact to the top-side plane.
OUT	9, 10	1, 18-20	O	Regulated output voltage. A small capacitor (total typical capacitance ≥ 2.2 μF, ceramic) is needed from this pin to ground to assure stability.
PG	3	9	O	Power Good pin. An open-drain, active-high output that indicates the status of V_OUT. When V_OUT exceeds the PG trip threshold, the PG pin goes into a high-impedance state. When V_OUT is below this threshold the pin is driven to a low-impedance state. A pull-up resistor from 10 kΩ to 1 MΩ should be connected from this pin to a supply of up to 5.5 V. The supply can be higher than the input voltage. Alternatively, the PG pin can be left unconnected if output monitoring is not necessary.
SS	7	15	—	Soft-Start pin. A capacitor connected on this pin to ground sets the start-up time. If this pin is left unconnected, the regulator output soft-start ramp time is typically 200 μs.
Thermal pad			—	Must be soldered to the ground plane for increased thermal performance. Internally connected to ground.

5 Specifications

5.1 Absolute Maximum Ratings

over operating temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
V_IN, V_BIAS	Input voltage	–0.3	6	V
V_EN	Enable voltage	–0.3	6	V
V_PG	Power-good voltage	–0.3	6	V
I_PG	PG sink current	0	1.5	mA
V_SS	Soft-start voltage	–0.3	6	V
V_FB	Feedback voltage	–0.3	6	V
V_OUT	Output voltage	–0.3	V_IN + 0.3	V
I_OUT	Maximum output current	Internally limited
	Output short-circuit duration	Indefinite
P_DISS	Continuous total power dissipation	See Thermal Information
T_J	Junction Temperature	–40	150	°C
T_stg	Storage Temperature	–55	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

5.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_IN	Input supply voltage	V_OUT + V_DO (V_IN)	V_OUT + 0.3	5.5	V
V_EN	Enable supply voltage		V_IN	5.5	V
V_BIAS⁽¹⁾	BIAS supply voltage	V_OUT + V_DO (V_BIAS)⁽²⁾	V_OUT + 1.6⁽²⁾	5.5	V
V_OUT	Output voltage	0.8		3.3	V
I_OUT	Output current	0		1.5	A
C_OUT	Output capacitor	2.2			µF
C_IN	Input capacitor⁽³⁾	1			µF
C_BIAS	Bias capacitor	0.1	1		µF
T_J	Operating junction temperature	–40		125	℃

(1) BIAS supply is required when V_IN is below V_OUT + 1.62 V.

(2) V_BIAS has a minimum voltage of 2.7 V or V_OUT + V_DO (V_BIAS), whichever is higher.

(3) If V_IN and V_BIAS are connected to the same supply, the recommended minimum capacitor for the supply is 4.7 μF.

5.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS748				UNIT
		RGW (VQFN)	RGW (VQFN)⁽²⁾	DRC (VSON)	DRC (VSON) ⁽²⁾
		20 PINS	20 PINS	10 PINS	10 PINS
R_θJA	Junction-to-ambient thermal resistance	35.6	34.7	44.2	47.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	33.3	31.0	50.3	63.7	°C/W
R_θJB	Junction-to-board thermal resistance	15	13.5	19.6	19.5	°C/W
ψ_JT	Junction-to-top characterization parameter	0.4	1.4	0.7	4.2	°C/W
ψ_JB	Junction-to-board characterization parameter	15.2	13.5	17.8	19.4	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	3.8	3.6	4.3	3.3	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC package thermla metrics application note.

(2) New Chip.

5.5 Electrical Characteristics

at V_EN = 1.1 V, V_IN = V_OUT + 0.3 V, C_BIAS = 0.1 μF, C_IN = C_OUT = 10 μF, C_NR = 1 nF, I_OUT = 50 mA, V_BIAS = 5.0 V, and T_J = –40°C to 125°C (unless otherwise noted); typical values are at T_J = 25°C

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_REF	Internal reference (Adj.)	T_A = 25°C	0.796	0.8	0.804	V
V_OUT	Output voltage range	V_IN = 5 V, I_OUT = 1.5 A	V_REF		3.6	V
	Accuracy⁽¹⁾	2.97 V ≤ V_BIAS ≤ 5.5 V, 50 mA ≤ I_OUT ≤ 1.5 A (Legacy Chip)	–2	±0.5	2	%
	Accuracy⁽¹⁾	2.97 V ≤ V_BIAS ≤ 5.5 V, 50 mA ≤ I_OUT ≤ 1.5 A (New Chip)	–1	±0.3	1	%
ΔV_OUT_(ΔVIN)	Line regulation	V_OUT(nom) + 0.3 ≤ V_IN ≤ 5.5 V (Legacy Chip)		0.03		%/V
ΔV_OUT_(ΔVIN)	Line regulation	V_OUT(nom) + 0.3 ≤ V_IN ≤ 5.5 V (New Chip)		0.001		%/V
ΔV_OUT_(ΔIOUT)	Load regulation	50 mA ≤ I_OUT ≤ 1.5 A		0.09		%/A
V_DO	V_IN dropout voltage⁽²⁾	I_OUT = 1.5 A, V_BIAS – V_OUT(nom) ≥ 3.25 V (Legacy Chip) ⁽³⁾		60	165	mV
	V_IN dropout voltage⁽²⁾	I_OUT = 1.5 A, V_BIAS – V_OUT(nom) ≥ 3.25 V (New Chip) ⁽³⁾		50	100	mV
	V_BIAS dropout voltage⁽²⁾	I_OUT = 1.5 A, V_IN = V_BIAS(Legacy Cip)		1.31	1.6	V
	V_BIAS dropout voltage⁽²⁾	I_OUT = 1.5 A, V_IN = V_BIAS(New Chip)		1.31	1.43	V
I_CL	Output current limit	V_OUT = 80% × V_OUT(nom)	2		5.5	A
I_BIAS	BIAS pin current	(Legacy Chip)		1	2	mA
I_BIAS	BIAS pin current	(New Chip)		1	1.2	mA
I_SHDN	Shutdown supply current (I_GND)	V_EN ≤ 0.4 V (Legacy Chip)		1	50	µA
I_SHDN	Shutdown supply current (I_GND)	V_EN ≤ 0.4 V (New Chip)		0.85	2.75	µA
I_FB	Feedback pin current	(Legacy Chip)	–1	0.15	1	µA
I_FB	Feedback pin current	(New Chip)	–30	0.15	30	nA
PSRR	Power-supply rejection (V_IN to V_OUT)	1 kHz, I_OUT = 1.5 A, V_IN = 1.8 V, V_OUT = 1.5 V		60		dB
	Power-supply rejection (V_IN to V_OUT)	300 kHz, I_OUT = 1.5 A, V_IN = 1.8 V, V_OUT = 1.5 V		30
	Power-supply rejection (V_BIAS to V_OUT)	1 kHz, I_OUT = 1.5 A, V_IN = 1.8 V, V_OUT = 1.5 V (Legacy Chip)		50
		1 kHz, I_OUT = 1.5 A, V_IN = 1.8 V, V_OUT = 1.5 V (New Chip)		59
		300 kHz, I_OUT = 1.5 A, V_IN = 1.8 V, V_OUT = 1.5 V (Legacy Chip)		30
		300 kHz, I_OUT = 1.5 A, V_IN = 1.8 V, V_OUT = 1.5 V (New Chip)		50
V_n	Output noise voltage	BW = 100 Hz to 100 kHz, I_OUT = 1.5 A, C_SS = 1 nF (Legacy Chip)		25 × V_OUT		μVrms
V_n	Output noise voltage	BW = 100 Hz to 100 kHz, I_OUT = 1.5 A, C_SS = 1 nF (New Chip)		20 × V_OUT		μVrms
t_STR	Minimum startup time	R_LOAD for I_OUT = 1.0 A, C_SS = open (Legacy Chip)		200		µs
t_STR	Minimum startup time	R_LOAD for I_OUT = 1.0 A, C_SS = open (New Chip)		250		µs
I_SS	Soft-start charging current	V_SS = 0.4 V (Legacy Chip)		440		nA
I_SS	Soft-start charging current	V_SS = 0.4 V (New Chip)		530		nA
V_EN(hi)	Enable input high level		1.1		5.5	V
V_EN(lo)	Enable input low level		0		0.4	V
V_EN(hys)	Enable pin hysteresis	(Legacy Chip)		50		mV
V_EN(hys)	Enable pin hysteresis	(New Chip)		55		mV
V_EN(dg)	Enable pin deglitch time			20		µs
I_EN	Enable pin current	V_EN = 5 V (Legacy Chip)		0.1	1	µA
I_EN	Enable pin current	V_EN = 5 V (New Chip)		0.1	0.3	µA
V_IT	PG trip threshold	V_OUT decreasing	85	90	94	%V_OUT
V_HYS	PG trip hysteresis			3		%V_OUT
V_PG(lo)	PG output low voltage	I_PG = 1 mA (sinking), V_OUT < V_IT(Legacy Chip)			0.3	V
V_PG(lo)	PG output low voltage	I_PG = 1 mA (sinking), V_OUT < V_IT(New Chip)			0.125	V
I_PG(lkg)	PG leakage current	V_PG = 5.25 V, V_OUT > V_IT(Legacy Chip)		0.1	1	µA
I_PG(lkg)	PG leakage current	V_PG = 5.25 V, V_OUT > V_IT(New Chip)		0.001	0.05	µA
T_SD	Thermal shutdown temperature	Shutdown, temperature increasing		165		℃
T_SD	Thermal shutdown temperature	Reset, temperature decreasing		140		℃
R_PULLDOWN	Output pulldown resitance	V_BIAS = 5V, V_EN = 0V		0.83	1	kΩ

(1) Adjustable devices tested at 0.8 V; resistor tolerance is not taken into account.

(2) Dropout is defined as the voltage from V_IN to V_OUT when V_OUT is 3% below nominal.

(3) 3.25 V is a test condition of this device and can be adjusted by referring to Figure 5-11.

5.6 Typical Characteristics: I_OUT = 50 mA

at T_J = 25°C, V_IN = V_OUT(nom) + 0.3 V, V_BIAS = 5 V, I_OUT = 50 mA, V_EN = V_IN, C_IN = 1 μF, C_BIAS = 4.7 μF, and C_OUT = 10 μF (unless otherwise noted)

Legacy chip

Figure 5-1 V_IN Line Regulation

Legacy chip

Figure 5-3 V_BIAS Line Regulation

Figure 5-5 Load Regulation at Light Load

Legacy chip

Figure 5-7 Load Regulation

TPS748 VIN Dropout Voltage vs IOUT and Temperature
(TJ)

Legacy chip

Figure 5-9 V_IN Dropout Voltage vs I_OUT and Temperature (T_J)

TPS748 VIN Dropout Voltage vs (VBIAS – VOUT)
and Temperature (TJ)

Figure 5-11 V_IN Dropout Voltage vs (V_BIAS – V_OUT) and Temperature (T_J)

TPS748 VBIAS Dropout Voltage vs IOUT and Temperature
(TJ)

Legacy chip

Figure 5-13 V_BIAS Dropout Voltage vs I_OUT and Temperature (T_J)

Legacy chip

Figure 5-15 V_BIAS PSRR vs Frequency

Legacy chip

Figure 5-17 V_IN PSRR vs Frequency

Legacy chip

Figure 5-19 V_IN PSRR vs (V_IN – V_OUT)

Legacy chip

Figure 5-21 Noise Spectral Density

TPS748 BIAS
Pin Current vs Output Current and Temperature (TJ)

Legacy chip

Figure 5-23 BIAS Pin Current vs Output Current and Temperature (T_J)

TPS748 BIAS
Pin Current vs VBIAS and Temperature (TJ)

Legacy chip

Figure 5-25 BIAS Pin Current vs V_BIAS and Temperature (T_J)

TPS748 Soft-Start Charging Current (ISS) vs Temperature
(TJ)

Legacy chip

Figure 5-27 Soft-Start Charging Current (I_SS) vs Temperature (T_J)

Legacy chip

Figure 5-29 Low-Level PG Voltage vs Current

Legacy chip

Figure 5-31 Current Limit vs (V_BIAS – V_OUT)

New chip

Figure 5-2 V_IN Line Regulation

New chip

Figure 5-4 V_BIAS Line Regulation

New chip

Figure 5-6 Load Regulation at Light Load

New chip

Figure 5-8 Load Regulation

New chip

Figure 5-10 V_IN Dropout Voltage vs I_OUT and Temperature (T_J)

Figure 5-12 V_IN Dropout Voltage vs (V_BIAS – V_OUT) and Temperature (T_J)

New chip

Figure 5-14 V_BIAS Dropout Voltage vs I_OUT and Temperature (T_J)

New chip

Figure 5-16 V_BIAS PSRR vs Frequency

Figure 5-18 V_IN PSRR vs Frequency

New chip

Figure 5-20 V_IN PSRR vs (V_IN – V_OUT)

New chip

Figure 5-22 Noise Spectral Density

New chip

Figure 5-24 BIAS Pin Current vs Output Current and Temperature (T_J)

New chip

Figure 5-26 BIAS Pin Current vs V_BIAS and Temperature (T_J)

New chip

Figure 5-28 Soft-Start Charging Current (I_SS) vs Temperature (T_J)

New chip

Figure 5-30 Low-Level PG Voltage vs Current

New chip

Figure 5-32 Current Limit vs (V_BIAS – V_OUT)

5.7 Typical Characteristics: I_OUT = 1 A

at T_J = 25°C, V_IN = V_OUT(nom) + 0.3 V, V_BIAS = 5 V, I_OUT = 1 A, V_EN = V_IN = 1.8 V, V_OUT = 1.5 V, C_IN = 1 μF, C_BIAS = 4.7 μF, and C_OUT = 10 μF (unless otherwise noted)

Legacy chip

Figure 5-33 V_BIAS Line Transient

Legacy chip

Figure 5-35 V_IN Line Transient

Legacy chip

Figure 5-37 Output Load Transient Response

Legacy chip

Figure 5-39 Turn-On Response

Legacy chip

Figure 5-41 Power-Up, Power-Down

New chip

Figure 5-34 V_BIAS Line Transient

New chip

Figure 5-36 V_IN Line Transient

New chip

Figure 5-38 Output Load Transient Response

New chip

Figure 5-40 Turn-On Response

New chip

Figure 5-42 Power-Up, Power-Down

6 Detailed Description

6.1 Overview

The TPS748 is a low-dropout regulator that features soft-start capability. This regulator uses a low current bias input to power all internal control circuitry, allowing the NMOS pass transistor to regulate very low input and output voltages.

The use of an NMOS-pass transistor offers several critical advantages for many applications. Unlike a PMOS topology device, the output capacitor has little effect on loop stability. This architecture allows the TPS748 to be stable with any capacitor type of value 2.2 μF or greater. Transient response is also superior to PMOS topologies, particularly for low V_IN applications.

The TPS748 features a programmable voltage-controlled soft-start circuit that provides a smooth, monotonic start-up and limits start-up inrush currents that may be caused by large capacitive loads. A power-good (PG) output is available to allow supply monitoring and sequencing of other supplies. An enable (EN) pin with hysteresis and deglitch allows slow-ramping signals to be used for sequencing the device. The low V_IN and V_OUT capability allows for inexpensive, easy-to-design, and efficient linear regulation between the multiple supply voltages often required by processor-intensive systems.