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  • ADC368x 18 位、0.5 至 65MSPS、低噪声、极低功率双通道 ADC

    • ZHCSN12B December   2020  – October 2022 ADC3681 , ADC3682 , ADC3683

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  • ADC368x 18 位、0.5 至 65MSPS、低噪声、极低功率双通道 ADC
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics - Power Consumption
    6. 6.6  Electrical Characteristics - DC Specifications
    7. 6.7  Electrical Characteristics - AC Specifications
    8. 6.8  Timing Requirements
    9. 6.9  Typical Characteristics - ADC3681
    10. 6.10 Typical Characteristics - ADC3682
    11. 6.11 Typical Characteristics - ADC3683
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Analog Input
        1. 8.3.1.1 Analog Input Bandwidth
        2. 8.3.1.2 Analog Front End Design
          1. 8.3.1.2.1 Sampling Glitch Filter Design
          2. 8.3.1.2.2 Analog Input Termination and DC Bias
            1. 8.3.1.2.2.1 AC-Coupling
            2. 8.3.1.2.2.2 DC-Coupling
        3. 8.3.1.3 Auto-Zero Feature
      2. 8.3.2 Clock Input
        1. 8.3.2.1 Single Ended vs Differential Clock Input
        2. 8.3.2.2 Signal Acquisition Time Adjust
      3. 8.3.3 Voltage Reference
        1. 8.3.3.1 Internal voltage reference
        2. 8.3.3.2 External voltage reference (VREF)
        3. 8.3.3.3 External voltage reference with internal buffer (REFBUF)
      4. 8.3.4 Digital Down Converter
        1. 8.3.4.1 DDC MUX
        2. 8.3.4.2 Digital Filter Operation
        3. 8.3.4.3 FS/4 Mixing with Real Output
        4. 8.3.4.4 Numerically Controlled Oscillator (NCO) and Digital Mixer
        5. 8.3.4.5 Decimation Filter
        6. 8.3.4.6 SYNC
        7. 8.3.4.7 Output Formatting with Decimation
      5. 8.3.5 Digital Interface
        1. 8.3.5.1 Output Formatter
        2. 8.3.5.2 Output Scrambler
        3. 8.3.5.3 Output Bit Mapper
        4. 8.3.5.4 Output Interface/Mode Configuration
          1. 8.3.5.4.1 Configuration Example
        5. 8.3.5.5 Output Data Format
      6. 8.3.6 Test Pattern
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Operation
      2. 8.4.2 Power Down Options
      3. 8.4.3 Digital Channel Averaging
    5. 8.5 Programming
      1. 8.5.1 Configuration using PINs only
      2. 8.5.2 Configuration using the SPI interface
        1. 8.5.2.1 Register Write
        2. 8.5.2.2 Register Read
    6. 8.6 Register Map
      1. 8.6.1 Detailed Register Description
  9. 9 Application Information Disclaimer
    1. 9.1 Typical Application
      1. 9.1.1 Design Requirements
      2. 9.1.2 Detailed Design Procedure
        1. 9.1.2.1 Input Signal Path
        2. 9.1.2.2 Sampling Clock
        3. 9.1.2.3 Voltage Reference
      3. 9.1.3 Application Curves
    2. 9.2 Initialization Set Up
      1. 9.2.1 Register Initialization During Operation
    3. 9.3 Power Supply Recommendations
    4. 9.4 Layout
      1. 9.4.1 Layout Guidelines
      2. 9.4.2 Layout Example
  10. 10Device and Documentation Support
    1. 10.1 接收文档更新通知
    2. 10.2 支持资源
    3. 10.3 Trademarks
    4. 10.4 Electrostatic Discharge Caution
    5. 10.5 术语表
  11. 11Mechanical, Packaging, and Orderable Information
  12. 重要声明
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DATA SHEET

ADC368x 18 位、0.5 至 65MSPS、低噪声、极低功率双通道 ADC

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 双通道 ADC
  • 18 位 10、25、65MSPS ADC
  • 本底噪声：-160dBFS/Hz
  • 低功耗和优化的功率调节：
    每通道 53mW (10MSPS) 至每通道 94mW (65MSPS)
  • 延迟：1-2 个时钟周期
  • 18 位，无丢码
  • INL/DNL：±7/±0.7LSB（典型值）
  • 基准：外部或内部
  • 输入带宽：900 MHz (3dB)
  • 工业温度范围：-40°C 至 +105°C
  • 片上数字滤波器（可选）
    • 2 倍、4 倍、8 倍、16 倍、32 倍抽取率
    • 32 位 NCO
  • 串行 LVDS 数字接口（2 线、1 线和 1/2 线）
  • 小尺寸：40-QFN (5x5mm) 封装
  • 频谱性能 (fIN = 5MHz)：
    • SNR：83.8dBFS
    • SFDR：89dBc HD2、HD3
    • SFDR：101dBFS 最严重毛刺
  • 频谱性能 (fIN = 20 MHz)：
    • SNR：82.6dBFS
    • SFDR：85dBc HD2、HD3
    • SFDR：97dBFS 最严重毛刺

2 应用

  • 高速数据采集
  • 工业监控
  • 软件定义无线电
  • 电能质量分析仪
  • 源测量单元 (SMU)
  • 通信基础设施
  • 频谱分析仪
  • 控制环路
  • 仪表
  • 成像
  • 光谱分析
  • 雷达

3 说明

ADC3681、ADC3682、ADC3683 (ADC368x) 属于低噪声、超低功耗、18 位、65MSPS 高速双通道 ADC 系列器件。该器件可实现超低噪声性能和 -160dBFS/Hz 的噪声频谱密度，还具有出色的线性度和动态范围。ADC368x 可提供出色的直流精度以及中频采样支持，因此适合各种应用。高速控制环路受益于低至仅一个时钟周期的低延迟。该 ADC 在 65Msps 下的功耗仅为每通道 94mW，且其功耗随采样率减小而降低。

ADC368x 使用串行 LVDS (SLVDS) 接口输出数据，可更大限度减少数字互连的次数。该器件提供双通道、单通道和半通道选项。ADC36xx 属于引脚对引脚兼容 ADC 系列，具有 16 位和 18 位分辨率和不同的速度等级。它采用 40 引脚 QFN 封装 (5mm x 5mm)，支持 -40⁰C 至 +105⁰C 的工业级工作温度范围。

封装信息
器件型号封装(1)封装尺寸（标称值）
ADC368xVQFN (40)5.00mm x 5.00mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
器件比较
器件型号 分辨率 采样率
ADC3683 18 位 65MSPS
ADC3682 18 位 25MSPS
ADC3681 18 位 10MSPS
FFT：Fs = 65MSPS，Fin = 5MHz

4 Revision History

Changes from Revision A (December 2021) to Revision B (October 2022)

  • 删除了器件比较 表中器件型号 ADC3681 的“产品预发布”说明Go
  • Added the Typical Characteristics - ADC3681 graphsGo
  • Added the Typical Characteristics - ADC3682 graphsGo
  • Added GND symbol to REFGND pin for all voltage reference option diagramsGo
  • Added the Output Bit Mapper sectionGo
  • Added Table 8-11 Go
  • Changed Figure 9-6 diagram with correct indexing Go

Changes from Revision * (December 2020) to Revision A (December 2021)

  • 删除了器件比较 表中器件型号 ADC3682 的“产品预发布”说明Go
  • Changed Sample N+1 position in Figure 7-2 and Figure 7-3 Go
  • Added condition to resynch during operation to the SYNC sectionGo

5 Pin Configuration and Functions

GUID-7A67AD96-BEF3-468C-8977-F6B5502F1165-low.gifFigure 5-1 RSB (WQQFN) Package, 40-Pin
(Top View)
Table 5-1 Pin Descriptions
PINI/ODescription
NameNo.
INPUT/REFERENCE
AINP12IPositive analog input, channel A
AINM13INegative analog input, channel A
BINP39IPositive analog input, channel B
BINM38INegative analog input, channel B
VCM8OCommon-mode voltage output for the analog inputs, 0.95V
VREF2IExternal voltage reference input, 1.6V
REFBUF4I1.2V external voltage reference input for use with internal reference buffer. Internal 100 kΩ pull-up resistor to AVDD. This pin is also used to configure default operating conditions.
REFGND3IReference ground input, 0V
CLOCK
CLKP6IPositive differential sampling clock input for the ADC
CLKM7INegative differential sampling clock input for the ADC
CONFIGURATION
PDN/SYNC1IPower down/Synchronization input. This pin can be configured via the SPI interface. Active high. This pin has an internal 21 kΩ pull-down resistor.
RESET9IHardware reset. Active high. This pin has an internal 21 kΩ pull-down resistor.
SEN16ISerial interface enable. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD.
SCLK35ISerial interface clock input. This pin has an internal 21 kΩ pull-down resistor.
SDIO10I/OSerial interface data input and output. This pin has an internal 21 kΩ pull-down resistor.
NC27-Do not connect
DIGITAL INTERFACE
DA0P20OPositive differential serial LVDS output for lane 0, channel A
DA0M19ONegative differential serial LVDS output for lane 0, channel A
DA1P18OPositive differential serial LVDS output for lane 1, channel A
DA1M17ONegative differential serial LVDS output for lane 1, channel A
DB0P31OPositive differential serial LVDS output for lane 0, channel B
DB0M32ONegative differential serial LVDS output for lane 0, channel B
DB1P33OPositive differential serial LVDS output for lane 1, channel B
DB1M34ONegative differential serial LVDS output for lane 1, channel B
DCLKP23OPositive differential serial LVDS bit clock output.
DCLKM22ONegative differential serial LVDS bit clock output.
FCLKP28OPositive differential serial LVDS frame clock output.
FCLKM29ONegative differential serial LVDS frame clock output.
DCLKINP25IPositive differential serial LVDS bit clock input. Internal 100 Ω differential termination.
DCLKINM24INegative differential serial LVDS bit clock input. Internal 100 Ω differential termination.
POWER SUPPLY
AVDD5,15,36IAnalog 1.8V power supply
GND11,14,37,40, PowerPadIGround, 0V
IOVDD21,30I1.8V power supply for digital interface
IOGND26IGround, 0V for digital interface

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Supply voltage range, AVDD, IOVDD –0.3 2.1 V
Supply voltage range, GND, IOGND, REFGND –0.3 0.3 V
Voltage applied to input pins AINP/M, BINP/M, CLKP/M, VREF, REFBUF –0.3 MIN(2.1, AVDD+0.3) V
PDN/SYNC, RESET, SCLK, SEN, SDIO –0.3 MIN(2.1, AVDD+0.3)
DCLKINP/M –0.3 MIN(2.1, IOVDD+0.3)
Junction temperature, TJ 105 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) 2500 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) 1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Supply voltage range AVDD(1) 1.75 1.8 1.85 V
IOVDD(1) 1.75 1.8 1.85 V
TA Operating free-air temperature –40 105 °C
TJ Operating junction temperature 105(2) °C
(1) Measured to GND.
(2) Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.

 
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