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  • AWR6843AOP 单芯片 60GHz 至 64GHz 毫米波传感器封装天线 (AOP)

    • ZHCSMR7C November   2020  – July 2022 AWR6843AOP

      PRODUCTION DATA  

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  • AWR6843AOP 单芯片 60GHz 至 64GHz 毫米波传感器封装天线 (AOP)
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 功能方框图
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagram
    2. 7.2 Signal Descriptions
      1. 7.2.1 Pin Functions - Digital and Analog [ALP Package]
    3. 7.3 Pin Attributes
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Power-On Hours (POH)
    4. 8.4  Recommended Operating Conditions
    5. 8.5  Power Supply Specifications
    6. 8.6  Power Consumption Summary
    7. 8.7  RF Specification
    8. 8.8  CPU Specifications
    9. 8.9  Thermal Resistance Characteristics for FCBGA Package [ALP0180A]
    10. 8.10 Timing and Switching Characteristics
      1. 8.10.1  Antenna Radiation Patterns
        1. 8.10.1.1 Antenna Radiation Patterns for Receiver
        2. 8.10.1.2 Antenna Radiation Patterns for Transmitter
      2. 8.10.2  Antenna Positions
      3. 8.10.3  Power Supply Sequencing and Reset Timing
      4. 8.10.4  Input Clocks and Oscillators
        1. 8.10.4.1 Clock Specifications
      5. 8.10.5  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 8.10.5.1 Peripheral Description
        2. 8.10.5.2 MibSPI Transmit and Receive RAM Organization
          1. 8.10.5.2.1 SPI Timing Conditions
          2. 8.10.5.2.2 SPI Controller Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. 8.10.5.2.3 SPI Controller Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 8.10.5.3 SPI Peripheral Mode I/O Timings
          1. 8.10.5.3.1 SPI Peripheral Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output) (1) (1) (1)
        4. 8.10.5.4 Typical Interface Protocol Diagram (Peripheral Mode)
      6. 8.10.6  LVDS Interface Configuration
        1. 8.10.6.1 LVDS Interface Timings
      7. 8.10.7  General-Purpose Input/Output
        1. 8.10.7.1 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      8. 8.10.8  Controller Area Network - Flexible Data-rate (CAN-FD)
        1. 8.10.8.1 Dynamic Characteristics for the CANx TX and RX Pins
      9. 8.10.9  Serial Communication Interface (SCI)
        1. 8.10.9.1 SCI Timing Requirements
      10. 8.10.10 Inter-Integrated Circuit Interface (I2C)
        1. 8.10.10.1 I2C Timing Requirements
      11. 8.10.11 Quad Serial Peripheral Interface (QSPI)
        1. 8.10.11.1 QSPI Timing Conditions
        2. 8.10.11.2 Timing Requirements for QSPI Input (Read) Timings
        3. 8.10.11.3 QSPI Switching Characteristics
      12. 8.10.12 ETM Trace Interface
        1. 8.10.12.1 ETMTRACE Timing Conditions
        2. 8.10.12.2 ETM TRACE Switching Characteristics
      13. 8.10.13 Data Modification Module (DMM)
        1. 8.10.13.1 DMM Timing Requirements
      14. 8.10.14 JTAG Interface
        1. 8.10.14.1 JTAG Timing Conditions
        2. 8.10.14.2 Timing Requirements for IEEE 1149.1 JTAG
        3. 8.10.14.3 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Subsystems
      1. 9.3.1 RF and Analog Subsystem
        1. 9.3.1.1 Clock Subsystem
        2. 9.3.1.2 Transmit Subsystem
        3. 9.3.1.3 Receive Subsystem
      2. 9.3.2 Processor Subsystem
      3. 9.3.3 Automotive Interface
      4. 9.3.4 Host Interface
      5. 9.3.5 Main Subsystem Cortex-R4F
      6. 9.3.6 DSP Subsystem
      7. 9.3.7 Hardware Accelerator
    4. 9.4 Other Subsystems
      1. 9.4.1 ADC Channels (Service) for User Application
        1. 9.4.1.1 GP-ADC Parameter
  10. 10Monitoring and Diagnostics
    1. 10.1 Monitoring and Diagnostic Mechanisms
      1. 10.1.1 Error Signaling Module
  11. 11Applications, Implementation, and Layout
    1. 11.1 Application Information
    2. 11.2 Reference Schematic
  12. 12Device and Documentation Support
    1. 12.1 Device Nomenclature
    2. 12.2 Tools and Software
    3. 12.3 Documentation Support
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 Electrostatic Discharge Caution
    7. 12.7 术语表
  13. 13Mechanical, Packaging, and Orderable Information
    1. 13.1 Packaging Information
    2. 13.2 Tray Information for ALP, 15 × 15 mm
  14. 重要声明
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DATA SHEET

AWR6843AOP 单芯片 60GHz 至 64GHz 毫米波传感器封装天线 (AOP)

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • FMCW 收发器
    • 集成 4 个接收器和 3 个发送器的封装天线 (AOP)
    • 集成 PLL、发送器、接收器、基带和 ADC
    • 60GHz 至 64GHz 的覆盖范围，具有 4GHz 的连续带宽
    • 支持 6 位移相器
    • 基于分数 N PLL 的超精确线性调频脉冲引擎
  • 内置校准和自检
    • 基于 Arm®Cortex®-R4F 的无线电控制系统
    • 内置固件 (ROM)
    • 针对工艺和温度进行自校准的系统
    • 在符合功能安全标准的器件上提供嵌入式自监控，无需主机处理器参与
  • 用于高级信号处理的 C674x DSP（仅限 AWR6843）
  • 用于 FFT、滤波和 CFAR 处理的硬件加速器
  • 存储器压缩
  • 用于物体检测和接口控制的 Arm® Cortex®-R4F 微控制器
    • 支持自主模式（从 QSPI 闪存加载用户应用）
  • 具有 ECC 的内部存储器
    • AWR6843：1.75MB，分为 MSS 程序 RAM (512KB)、MSS 数据 RAM (192KB)、DSP L1RAM (64KB) 和 L2 RAM (256KB) 以及 L3 雷达数据立方体 RAM (768KB)
    • AWR6443：1.4MB，分为 MSS 程序 RAM (512KB)、MSS 数据 RAM (192KB) 和 L3 雷达数据立方体 RAM (768KB)
    • 技术参考手册包括允许的大小修改
  • 为用户应用提供的其他接口
    • 多达 6 个 ADC 通道（低采样率监控）
    • 多达 2 个 SPI 端口
    • 多达 2 个 UART
    • 2 个 CAN-FD 接口
    • I2C
    • GPIO
    • 用于原始 ADC 数据和调试仪表的双通道 LVDS 接口
  • 器件安全（在部分器件型号上）
    • 支持经过身份验证和加密的安全引导
    • 具有密钥撤销功能的客户可编程根密钥、对称密钥（256 位）、非对称密钥（最高 RSA-2K）
    • 加密软件加速器 – PKA、AES（最高 256 位）、SHA（最高 256 位）、TRNG/DRGB
  • 符合功能安全标准
    • 专为功能安全应用开发
    • 文档有助于使 ISO 26262 功能安全系统设计满足 ASIL-D 级要求
    • 硬件完整性高达 ASIL-B 级
    • 安全相关认证
      • 经 TUV SUD 进行 ISO 26262 认证达到 ASIL B 级
  • 符合 AEC-Q100 标准
  • 电源管理
    • 内置 LDO 网络，可增强 PSRR
    • I/O 支持双电压 3.3V/1.8V
  • 时钟源
    • 具有内部振荡器的 40.0MHz 晶体
    • 支持频率为 40MHz 的外部振荡器
    • 支持外部驱动、频率为 40MHz 的时钟（方波/正弦波）
  • 轻松的硬件设计
    • 0.8mm 间距、180 引脚 15mm × 15mm 覆晶 BGA 封装 (ALP)，可实现轻松组装和低成本 PCB 设计
    • 小解决方案尺寸
  • 运行条件：
    • 结温范围为 –40°C 至 125°C

2 应用

  • 车内感应
  • 车内儿童检测
  • 占位检测
  • 安全带提醒装置
  • 驾驶员生命体征监测
  • 脚踢传感器/接入传感器
  • 手势识别

3 说明

AWR6843AOP 是一款封装天线 (AOP) 器件，是德州仪器 (TI) 的单芯片雷达器件系列的升级版。该器件在极小的封装中实现了出色的集成度，是适用于汽车领域中低功耗、自监控、超精确雷达系统的理想解决方案。当前提供多种符合汽车标准的型号，包括功能安全合规型器件 (ASIL-B) 和非功能安全器件。

它集成了一个 DSP 子系统，该子系统包含 TI 用于雷达信号处理的高性能 C674x DSP。该器件包含一个 BIST 处理器子系统，该子系统负责无线电配置、控制和校准。此外，该器件还包含用于汽车连接的用户可编程 Arm Cortex-R4F。硬件加速器区块 (HWA) 可执行雷达处理，并减轻 DSP 上的负载，从而执行更高级的算法。简单编程模型更改可支持各种传感器应用，并且能够进行动态重新配置，从而实现多模式传感器。此外，该器件作为完整的平台解决方案进行提供，该解决方案包括硬件参考设计、软件驱动程序、样例配置、API 指南以及用户文档。

器件信息
器件型号 封装(1) 封装尺寸 托盘/卷带包装
AWR6843ARBGALPQ1 FCBGA (180) 15mm × 15mm 托盘
AWR6843ARBGALPRQ1 FCBGA (180) 15mm × 15mm 卷带包装
AWR6843ARBSALPQ1 FCBGA (180) 15mm × 15mm 托盘
AWR6843ARBSALPRQ1 FCBGA (180) 15mm × 15mm 卷带包装
(1) 如需更多信息，请参阅Section 13机械、封装和可订购信息。

4 功能方框图

图 4-1 展示了器件的功能方框图

GUID-20201029-CA0I-72QD-ZFJ3-2WHTZ9R3B1CM-low.gif图 4-1 功能方框图

5 Revision History

Changes from November 13, 2020 to May 27, 2021 (from Revision * (November 2020) to Revision A (May 2021))

  • 通篇：将 AWR6843AOP 器件信息和文档产品状态从“预告信息”更新/更改为“量产数据 (PD)”Go
  • 通篇：将 A2D 更新/更改为 ADC；将“主子系统”更新/更改为“主要子系统”并将“主要 R4F”更改为“MSS R4F”Go
  • 器件信息：更新/添加了器件型号以及托盘/卷带封装信息。更新/更改了“说明”段落Go
  • Device Features Comparison: Changed/Updated to include AWR6843AOP product status to PD and included note about LVDS debugGo
  • (Pin Attributes): Updated/Changed table to remove unsupported mux modes Go
  • Power Consumption Summary: Updated/Modified VIOIN current consumption value (changing from a TYP to a MAX value of 50 mA)Go
  • RF Specification: Updated/Changed Reciever Effective isotropic noise figure (EINF) TYP value from 14 to 9 dB and added Transmitter Power backoff range row Go
  • Antenna radiation patterns: Updated/Changed RX and TX radiation pattern figures Go
  • Transmit Subsystem: Updated/Changed figure.Go
  • Receive Subsystem: Updated/Changed figure.Go
  • Packaging Information: Updated/Added note on the expected variability in the color of the AOP productGo
  • Tray Information for ALP, 15 × 15 mm: Added tray information.Go

Changes from May 28, 2021 to June 1, 2021 (from Revision A (May 2021) to Revision B (June 2021))

  • 通篇：将 CAN 更新/更改为 CAN-FDGo
  • (Pin Functions): Updated "CAN_FD_RX" to "CAN1_FD_RX" and added a row for signal name "CAN2_FD_RX" to the list and reassociated ball no. D2Go
  • (Pin Functions): Updated "CAN_FD_TX" to "CAN1_FD_TX" and added a row for signal name "CAN2_FD_TX" to the list and reassociated ball no. B4Go
  • (Pin Attributes): Updated/Changed ball number B4 to show correct signal name as "CAN2_FD_TX"Go
  • (Pin Attributes): Updated/Changed ball number D2 to show correct signal name as "CAN2_FD_RX"Go
  • (Pin Attributes): Updated/Changed signal name from "CAN_FD_RX" to "CAN1_FD_RX'Go
  • (Pin Attributes): Updated/Changed signal name from "CAN_FD_TX" to "CAN1_FD_TX'Go
  • Removed External Clock Electrical Characteristics tableGo
  • Updated/Changed External Clock Mode Specifications table to match AWR16Go
  • Updated/changed the CAN-FD descriptionGo
  • Updated/changed "CAN_FD_rx" to "CANx_FD_RX" and "CAN_FD_tx" to "CANx_FD_TX" in the table to include both instancesGo
  • Updated/Changed Host Interrupt bullet in Host InterfaceGo
  • Updated/Changed text from "ADC channel mapped to B12" to "GPADC channel 6"Go
  • (GP-ADC Parameter): Updated/Changed GP-ADC Parameter table to match AWR16Go
  • Updated/changed "CAN" to "CAN-FD"Go
  • (Monitoring and Diagnostic Mechanisms): Updated/Changed table header and description to reflect Functional Safety-Compliance; added a note for reference to safety related collateral Go
  • Section 13.2 (Tray Information for ABL, 10.4 × 10.4 mm): Added new section with tray information.Go

Changes from June 2, 2021 to July 31, 2022 (from Revision B (June 2021) to Revision C (July 2022))

  • （特性）：更新了功能安全合规性认证资料；添加了关于器件安全的详细信息；提及了毫米波传感器的额定工作温度范围Go
  • （说明）：更新/更改了“说明”以添加有关器件子系统的更多详细信息。Go
  • (Device Comparison) Removed information on Functional-Safety compliance from the table and instead added a table-note for this and LVDS Interface; Additional information on Device security updated.Go
  • (QSPI Timings):Updated/Changed Setup Time from 7.3us to 5us and Hold Time from 1.5us to 1us for QSPI TimingsGo
  • (QSPI Timings): Updated/Changed Delay time, sclk falling edge to d[1] transition i.e. [Q6, Q9] from -3.5us to -2.5us (Min) and 7us to 4us (Max) in QSPI Switching CharacteristicsGo
  • (Monitoring and Diagnostic Mechanisms): Updated/Changed table header and description to reflect Functional Safety-Compliance; added a note for reference to safety related collateral Go
  • (Monitoring and Diagnostic Mechanisms): Updated/Changed table header and description to reflect Functional Safety-Compliance; added a note for reference to safety related collateral Go

6 Device Comparison

Table 6-1 Device Features Comparison
FUNCTION AWR6843AOP(1) AWR1843AOP AWR6843 AWR6443 AWR1843 AWR1642 AWR1443
Antenna on Package (AOP) Yes Yes — — — — —
Number of receivers 4 4 4 4 4 4 4
Number of transmitters 3(2) 3(2) 3(2) 3(2) 3(2) 2 3
RF frequency range 60 to 64 GHz 76 to 81 GHz 60 to 64 GHz 60 to 64 GHz 76 to 81 GHz 76 to 81 GHz 76 to 81 GHz
On-chip memory 1.75MB 2MB 1.75MB 1.4MB 2MB 1.5MB 576KB
Max I/F (Intermediate Frequency) (MHz) 10 10 10 10 10 5 5
Max real sampling rate (Msps) 25 25 25 25 25 12.5 12.5
Max complex sampling rate (Msps) 12.5 12.5 12.5 12.5 12.5 6.25 6.25
Device Security(3) Yes Yes Yes — Yes Yes —
Processors
MCU (R4F) Yes Yes Yes Yes Yes Yes Yes
DSP (C674x) Yes Yes Yes — Yes Yes —
Peripherals
Serial Peripheral Interface (SPI) ports 2 2 2 2 2 2 1
Quad Serial Peripheral Interface (QSPI) Yes Yes Yes Yes Yes Yes Yes
Inter-Integrated Circuit (I2C) interface 1 1 1 1 1 1 1
Controller Area Network (DCAN) interface — 1 — — 1 1 1
Controller Area Network (CAN-FD) interface 2 1 2 2 1 — —
Trace Yes Yes Yes Yes Yes Yes —
PWM Yes Yes Yes Yes Yes Yes —
Hardware In Loop (HIL/DMM) Yes Yes Yes Yes Yes Yes —
GPADC Yes Yes Yes Yes Yes Yes Yes
LVDS/Debug(4) Yes Yes Yes Yes Yes Yes Yes
CSI2 — — — — — — —
Hardware accelerator Yes Yes Yes Yes Yes — Yes
1-V bypass mode Yes Yes Yes Yes Yes Yes Yes
JTAG Yes Yes Yes Yes Yes Yes Yes
Product status Product Preview (PP),
Advance Information (AI),
or Production Data (PD)		 PD(5) PD(5) PD(5) PD(5) PD(5) PD(5) PD(5)
(1) Developed for Functional Safety applications, the device supports hardware integrity upto ASIL-B. Refer to the related documentation for more details.
(2) 3 Tx Simultaneous operation is supported only with 1-V LDO bypass and PA LDO disable mode. In this mode, the 1-V supply needs to be fed on the VOUT PA pin.
(3) Device security features including Secure Boot and Customer Programmable Keys are available in select devices for only select part variants as indicated by the Device Type identifier in Section 3, Device Information table.
(4) The LVDS interface is not a production interface and is only used for debug.
(5) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. ADVANCE INFORMATION for pre-production products; subject to change without notice.

6.1 Related Products

For information about other devices in this family of products or related products see the links that follow.

    mmWave sensorsTI’s mmWave sensors rapidly and accurately sense range, angle and velocity with less power using the smallest footprint mmWave sensor portfolio for industrial applications.
    Automotive mmWave sensors TI’s automotive mmWave sensor portfolio offers high-performance radar front end to ultra-high resolution, small and low-power single-chip radar solutions. TI’s scalable sensor portfolio enables design and development of ADAS system solution for every performance, application and sensor configuration ranging from comfort functions to safety functions in all vehicles.
    Companion products for AWR6843AOP Review products that are frequently purchased or used in conjunction with this product.
    Reference designs for AWR6843AOP TI Designs Reference Design Library is a robust reference design library spanning analog, embedded processor and connectivity. Created by TI experts to help you jump-start your system design, all TI Designs include schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download designs at ti.com/tidesigns.
    Vehicle occupant detection reference design This reference design demonstrates the use of the AWR6843 60GHz single-chip mmWave sensor with integrated DSP, as a Vehicle Occupant Detection (VOD) and Child Presence Detection (CPD) Sensor enabling the detection of life forms in a vehicle. This design provides a reference software processing chain which runs on the C674x DSP, enabling the generation of a heat map to detect occupants in a Field of View (FOV) of ±60 degrees.

7 Terminal Configuration and Functions

7.1 Pin Diagram

Figure 7-1 shows the pin locations for the 180-pin 15 × 15 mm FCBGA package

GUID-7EB1ED49-4E53-4036-BA12-548134BE6482-low.png Figure 7-1 Pin Diagram (Top View)

7.2 Signal Descriptions

Note:

All IO pins of the device (except NERROR IN, NERROR_OUT, and WARM_RESET) are non-failsafe; hence, care needs to be taken that they are not driven externally without the VIO supply being present to the device.

Note:

The GPIO state during the power supply ramp is not ensured. In case the GPIO is used in the application where the state of the GPIO is critical, even when NRESET is low , a tri-state buffer should be used to isolate the GPIO output from the radar device and a pull resister used to define the required state in the application. The NRESET signal to the radar device could be used to control the output enable (OE) of the tri-state buffer.

7.2.1 Pin Functions - Digital and Analog [ALP Package]

NAMEI/ODESCRIPTIONNO.
DIGITAL
BSS_UART_TXODebug UART Transmit [Radar Block]D3, E2, K3, L2, U8, U10, U16, V16
CAN1_FD_RXICAN1 FD (MCAN) Receive SignalA4, B3, E2, F2, K2, U8, V16
CAN1_FD_TX O CAN1 FD (MCAN) Transmit Signal C2, C3, D1, D3, J3, T3, U16
CAN2_FD_RX I CAN2 FD (MCAN) Receive Signal D2
CAN2_FD_TX O CAN2 FD (MCAN) Transmit Signal B4
DMM0IDebug Interface (Hardware In Loop) - Data LineU7
DMM1IDebug Interface (Hardware In Loop) - Data LineU6
DMM2IDebug Interface (Hardware In Loop) - Data LineV5
DMM3IDebug Interface (Hardware In Loop) - Data LineU5
DMM4IDebug Interface (Hardware In Loop) - Data LineV3
DMM5IDebug Interface (Hardware In Loop) - Data LineM1
DMM6IDebug Interface (Hardware In Loop) - Data LineL2
DMM7IDebug Interface (Hardware In Loop) - Data LineL1
DMM8IDebug Interface (Hardware In Loop) - Data LineC3
DMM9IDebug Interface (Hardware In Loop) - Data LineB3
DMM10IDebug Interface (Hardware In Loop) - Data LineC4
DMM11IDebug Interface (Hardware In Loop) - Data LineA3
DMM12IDebug Interface (Hardware In Loop) - Data LineB4
DMM13IDebug Interface (Hardware In Loop) - Data LineA4
DMM14IDebug Interface (Hardware In Loop) - Data LineC5
DMM15IDebug Interface (Hardware In Loop) - Data LineB5
DMM_CLKIDebug Interface (Hardware In Loop) - ClockU3
DMM_MUX_INIDebug Interface (Hardware In Loop) Mux Select between DMM1 and DMM2 (Two Instances)L3, M3, U12
DMM_SYNCIDebug Interface (Hardware In Loop) - SyncU4
DSS_UART_TXODebug UART Transmit [DSP]D2, F2, G3, H2, L1
EPWM1AOPWM Module 1 - Output AB4, U16, V13
EPWM1BOPWM Module 1 - Output BA4, M2, U16, V10
EPWM1SYNCIIPWM Module 1 - Sync InputC3, L3
EPWM1SYNCOIPWM Module 1 - Sync OutputB3
EPWM2AOPWM Module 2- Output AC5, M2, U16, V10, V16
EPWM2BOPWM Module 2 - Output BB5, V16
EPWM2SYNCOOPWM Module 2 - Sync OutputV3
EPWM3AOPWM Module 3 - Output AC4, V16
EPWM3BOPWM Module 3 - Output AA3
EPWM3SYNCOOPWM Module 3 - Sync OutputU5
GPIO_0IOGeneral-purpose I/OM2
GPIO_1IOGeneral-purpose I/OL3
GPIO_2IOGeneral-purpose I/OK3
GPIO_3IOGeneral-purpose I/OD2
GPIO_4IOGeneral-purpose I/OD3
GPIO_5IOGeneral-purpose I/OE2
GPIO_6IOGeneral-purpose I/OJ2
GPIO_7IOGeneral-purpose I/OH2
GPIO_8IOGeneral-purpose I/OH3
GPIO_9IOGeneral-purpose I/OG2
GPIO_10IOGeneral-purpose I/OJ3
GPIO_11IOGeneral-purpose I/OK2
GPIO_12IOGeneral-purpose I/OB2
GPIO_13IOGeneral-purpose I/OM2
GPIO_14IOGeneral-purpose I/OU16
GPIO_15IOGeneral-purpose I/OV16
GPIO_16IOGeneral-purpose I/OL3
GPIO_17IOGeneral-purpose I/OT3
GPIO_18IOGeneral-purpose I/OU8
GPIO_19IOGeneral-purpose I/OF2
GPIO_20IOGeneral-purpose I/OD1
GPIO_21IOGeneral-purpose I/OG1
GPIO_22IOGeneral-purpose I/OG3
GPIO_23IOGeneral-purpose I/OU9
GPIO_24IOGeneral-purpose I/OU10
GPIO_25IOGeneral-purpose I/OV13
GPIO_26IOGeneral-purpose I/OK3
GPIO_27IOGeneral-purpose I/OV10
GPIO_28IOGeneral-purpose I/OU12
GPIO_29IOGeneral-purpose I/OM3
GPIO_30IOGeneral-purpose I/OC2, D2
GPIO_31IOGeneral-purpose I/OU7
GPIO_32IOGeneral-purpose I/OU6
GPIO_33IOGeneral-purpose I/OV5
GPIO_34IOGeneral-purpose I/OU5
GPIO_35IOGeneral-purpose I/OV3
GPIO_36IOGeneral-purpose I/OM1
GPIO_37IOGeneral-purpose I/OL2
GPIO_38IOGeneral-purpose I/OL1
GPIO_39IOGeneral-purpose I/OC3
GPIO_40IOGeneral-purpose I/OB3
GPIO_41IOGeneral-purpose I/OC4
GPIO_42IOGeneral-purpose I/OA3
GPIO_43IOGeneral-purpose I/OB4
GPIO_44IOGeneral-purpose I/OA4
GPIO_45IOGeneral-purpose I/OC5
GPIO_46IOGeneral-purpose I/OB5
GPIO_47IOGeneral-purpose I/OU3
I2C_SCLIOI2C ClockG3, V16
I2C_SDAIOI2C DataG1, U16
LVDS_TXP[0]ODifferential data Out – Lane 0N2
LVDS_TXM[0]ODifferential data Out – Lane 0N1
LVDS_TXP[1]ODifferential data Out – Lane 1P2
LVDS_TXM[1]ODifferential data Out – Lane 1P1
LVDS_CLKPODifferential clock OutR1
LVDS_CLKMODifferential clock OutR2
LVDS_FRCLKPODifferential Frame ClockT1
LVDS_FRCLKMODifferential Frame ClockT2
MCU_CLKOUTOProgrammable clock given out to external MCU or the processorV13
MSS_UARTA_RXIMain Subsystem - UART A ReceiveE2, U9, V16
MSS_UARTA_TXOMain Subsystem - UART A TransmitD3, U7, U10, U16
MSS_UARTB_RXIOMain Subsystem - UART B ReceiveU12, V16
MSS_UARTB_TXOMain Subsystem - UART B TransmitD3, E2, K3, M1, T3, U10, U16
NDMM_ENIDebug Interface (Hardware In Loop) Enable - Active Low SignalU10, U16
NERROR_INIFailsafe input to the device. Nerror output from any other device can be concentrated in the error signaling monitor module inside the device and appropriate action can be taken by FirmwareU14
NERROR_OUTOOpen drain fail safe output signal. Connected to PMIC/Processor/MCU to indicate that some severe criticality fault has happened. Recovery would be through reset.U15
PMIC_CLKOUTOOutput Clock from AWR6843AOP device for PMICK3, M2, V10
QSPI[0]IOQSPI Data Line #0 (Used with Serial Data Flash)H3
QSPI[1]IQSPI Data Line #1 (Used with Serial Data Flash)G2
QSPI[2]IQSPI Data Line #2 (Used with Serial Data Flash)J3
QSPI[3]IQSPI Data Line #3 (Used with Serial Data Flash)K2
QSPI_CLKOQSPI Clock (Used with Serial Data Flash)H2
QSPI_CLK_EXTIQSPI Clock (Used with Serial Data Flash)D3
QSPI_CS_NOQSPI Chip Select (Used with Serial Data Flash)J2
RS232_RXIDebug UART (Operates as Bus Master) - Receive SignalV16
RS232_TXODebug UART (Operates as Bus Master) - Transmit SignalU16
SOP[0]ISense On Power - Line#0U10
SOP[1]ISense On Power - Line#1M3
SOP[2]ISense On Power - Line#2V10
SPIA_CLKIOSPI Channel A - ClockD2
SPIA_CS_NIOSPI Channel A - Chip SelectC2
SPIA_MISOIOSPI Channel A - Master In Slave OutD1
SPIA_MOSIIOSPI Channel A - Master Out Slave InF2
SPIB_CLKIOSPI Channel B - ClockE2, H2
SPIB_CS_NIOSPI Channel B Chip Select (Instance ID 0)D3, J2
SPIB_CS_N_1IOSPI Channel B Chip Select (Instance ID 1)B2, L3, M3
SPIB_CS_N_2IOSPI Channel B Chip Select (Instance ID 2)G2, L3, M3
SPIB_MISOIOSPI Channel B - Master In Slave OutG3, H3
SPIB_MOSIIOSPI Channel B - Master Out Slave InG1, G2
SPI_HOST_INTROOut of Band Interrupt to an external host communicating over SPIB2
SYNC_INILow frequency Synchronization signal inputU12
SYNC_OUTOLow Frequency Synchronization Signal outputK3, L3, M3, U12
TCKIJTAG Test ClockT3
TDIIJTAG Test Data InputU9
TDOOJTAG Test Data OutputU10
TMSIJTAG Test Mode SignalU8
TRACE_CLKODebug Trace Output - ClockU3
TRACE_CTLODebug Trace Output - ControlU4
TRACE_DATA_0ODebug Trace Output - Data LineU7
TRACE_DATA_1ODebug Trace Output - Data LineU6
TRACE_DATA_2ODebug Trace Output - Data LineV5
TRACE_DATA_3ODebug Trace Output - Data LineU5
TRACE_DATA_4ODebug Trace Output - Data LineV3
TRACE_DATA_5ODebug Trace Output - Data LineM1
TRACE_DATA_6ODebug Trace Output - Data LineL2
TRACE_DATA_7ODebug Trace Output - Data LineL1
TRACE_DATA_8ODebug Trace Output - Data LineC3
TRACE_DATA_9ODebug Trace Output - Data LineB3
TRACE_DATA_10ODebug Trace Output - Data LineC4
TRACE_DATA_11ODebug Trace Output - Data LineA3
TRACE_DATA_12ODebug Trace Output - Data LineB4
TRACE_DATA_13ODebug Trace Output - Data LineA4
TRACE_DATA_14ODebug Trace Output - Data LineC5
TRACE_DATA_15ODebug Trace Output - Data LineB5
FRAME_STARTOPulse signal indicating the start of each frameK3, V10, V13
CHIRP_STARTOPulse signal indicating the start of each chirpK3, V10, V13
CHIRP_ENDOPulse signal indicating the end of each chirpK3, V10, V13
ADC_VALIDOWhen high, indicating valid ADC samplesB2, L3, M2
WARM_RESETIOOpen drain fail safe warm reset signal. Can be driven from PMIC for diagnostic or can be used as status signal that the device is going through reset.U13
ANALOG
NRESETIPower on reset for chip. Active lowU11
CLKPIIn XTAL mode: Differential port for reference crystal In External clock mode: Single ended input reference clock portA7
CLKMIIn XTAL mode: Differential port for reference crystal In External clock mode: Connect this port to groundB7
OSC_CLKOUTOReference clock output from clocking sub system after cleanup PLL (1.4-V output voltage swing).A14, K3
VBGAPODevice's Band Gap Reference OutputA16
VDDINPower1.2V digital power supplyE1, J1, V4, V8, V15
VIN_SRAMPower1.2V power rail for internal SRAMA5, V6, V12
VNWAPower1.2V power rail for SRAM array back biasC1, V7, V14
VIOINPowerI/O Supply (3.3V or 1.8V): All CMOS I/Os would operate on this supplyH1, V9
VIOIN_18Power1.8V supply for CMOS IOB1, F1, K1, V11
VIN_18CLKPower1.8V supply for clock moduleC15, C18
VIOIN_18DIFFPower1.8V supply for LVDS portU2
VPPPowerVoltage supply for fuse chainV2
VIN_13RF1Power1.3V Analog and RF supply,VIN_13RF1 and VIN_13RF2 could be shorted on the boardJ16, J17, J18
VIN_13RF2Power1.3V Analog and RF supplyH16, H17, H18
VIN_18BBPower1.8V Analog base band power supplyM16, M17, M18
VIN_18VCOPower1.8V RF VCO supplyA12, C11
VSSGroundDigital groundA1, A2, E3, F3, N3, P3, R3, T4, T5, T6, T7, T8, T9, T10, T11, T12, T13, T14, T15, T16, U1, V1
VSSAGroundAnalog groundA6, A8, A11, A13, A15, A17, A18, B6, B8, B9, B10, B11, B12, B13, B14, B15, B16, B17, B18, C6, C7, C8, C12, C13, C14, C16, C17, D16, D17, D18, E16, E17, E18, F16, F17, F18, K16, K17, K18, L16, L17, L18, N16, N17, N18, P16, R16, R17, T17, U17, U18, V17, V18
VOUT_14APLLOInternal LDO outputA10
VOUT_14SYNTHOInternal LDO outputA9
VOUT_PAIOInternal LDO outputG16, G17, G18
Analog Test1 / GPADC1IOAnalog IO dedicated for ADC serviceP18
Analog Test2 / GPADC2IOAnalog IO dedicated for ADC serviceP17
Analog Test3 / GPADC3IOAnalog IO dedicated for ADC serviceR18
Analog Test4 / GPADC4IOAnalog IO dedicated for ADC serviceT18
ANAMUX / GPADC5IOAnalog IO dedicated for ADC serviceC9
VSENSE / GPADC6IOAnalog IO dedicated for ADC serviceC10

7.3 Pin Attributes

Table 7-1 Pin Attributes (ALP180A Package)
BALL NUMBER [1] BALL NAME [2] SIGNAL NAME [3] PINCNTL ADDRESS [4] MODE [5][9] TYPE [6] BALL RESET STATE [7] PULL UP/DOWN TYPE [8]
M2 GPIO_0 GPIO_13 0xFFFFEA04 0 IO Output Disabled Pull Down
GPIO_0 1 IO
PMIC_CLKOUT 2 O
EPWM1B 10 O
ePWM2A 11 O
L3 GPIO_1 GPIO_16 0xFFFFEA08 0 IO Output Disabled Pull Down
GPIO_1 1 IO
SYNC_OUT 2 O
DMM_MUX_IN 12 I
SPIB_CS_N_1 13 IO
SPIB_CS_N_2 14 IO
EPWM1SYNCI 15 I
K3 GPIO_2 GPIO_26 0xFFFFEA64 0 IO Output Disabled Pull Down
GPIO_2 1 IO
OSC_CLKOUT 2 O
MSS_UARTB_TX 7 O
BSS_UART_TX 8 O
SYNC_OUT 9 O
PMIC_CLKOUT 10 O
CHIRP_START 11 O
CHIRP_END 12 O
FRAME_START 13 O
U7 GPIO_31 (DP0) TRACE_DATA_0 0xFFFFEA7C 0 O Output Disabled Pull Down
GPIO_31 1 IO
DMM0 2 I
MSS_UARTA_TX 4 IO
U6 GPIO_32 (DP1) TRACE_DATA_1 0xFFFFEA80 0 O Output Disabled Pull Down
GPIO_32 1 IO
DMM1 2 I
V5 GPIO_33 (DP2) TRACE_DATA_2 0xFFFFEA84 0 O Output Disabled Pull Down
GPIO_33 1 IO
DMM2 2 I
U5 GPIO_34 (DP3) TRACE_DATA_3 0xFFFFEA88 0 O Output Disabled Pull Down
GPIO_34 1 IO
DMM3 2 I
EPWM3SYNCO 4 O
V3 GPIO_35 (DP4) TRACE_DATA_4 0xFFFFEA8C 0 O Output Disabled Pull Down
GPIO_35 1 IO
DMM4 2 I
EPWM2SYNCO 4 O
M1 GPIO_36 (DP5) TRACE_DATA_5 0xFFFFEA90 0 O Output Disabled Pull Down
GPIO_36 1 IO
DMM5 2 I
MSS_UARTB_TX 5 O
L2 GPIO_37 (DP6) TRACE_DATA_6 0xFFFFEA94 0 O Output Disabled Pull Down
GPIO_37 1 IO
DMM6 2 I
BSS_UART_TX 5 O
L1 GPIO_38 (DP7) TRACE_DATA_7 0xFFFFEA98 0 O Output Disabled Pull Down
GPIO_38 1 IO
DMM7 2 I
DSS_UART_TX 5 O
C3 GPIO_39 (DP8) TRACE_DATA_8 0xFFFFEA9C 0 O Output Disabled Pull Down
GPIO_39 1 IO
DMM8 2 I
CAN1_FD_TX 4 O
EPWM1SYNCI 5 I
B3 GPIO_40 (DP9) TRACE_DATA_9 0xFFFFEAA0 0 O Output Disabled Pull Down
GPIO_40 1 IO
DMM9 2 I
CAN1_FD_RX 4 I
EPWM1SYNCO 5 O
C4 GPIO_41 (DP10) TRACE_DATA_10 0xFFFFEAA4 0 O Output Disabled Pull Down
GPIO_41 1 IO
DMM10 2 I
EPWM3A 4 O
A3 GPIO_42 (DP11) TRACE_DATA_11 0xFFFFEAA8 0 O Output Disabled Pull Down
GPIO_42 1 IO
DMM11 2 I
EPWM3B 4 O
B4 GPIO_43 (DP12) TRACE_DATA_12 0xFFFFEAAC 0 O Output Disabled Pull Down
GPIO_43 1 IO
DMM12 2 I
EPWM1A 4 O
CAN2_FD_TX 5 O
A4 GPIO_44 (DP13) TRACE_DATA_13 0xFFFFEAB0 0 O Output Disabled Pull Down
GPIO_44 1 IO
DMM13 2 I
EPWM1B 4 O
CAN1_FD_RX 5 I
C5 GPIO_45 (DP14) TRACE_DATA_14 0xFFFFEAB4 0 O Output Disabled Pull Down
GPIO_45 1 IO
DMM14 2 I
EPWM2A 4 O
B5 GPIO_46 (DP15) TRACE_DATA_15 0xFFFFEAB8 0 O Output Disabled Pull Down
GPIO_46 1 IO
DMM15 2 I
EPWM2B 4 O
U3 GPIO_47 (DMM_CLK) TRACE_CLK 0xFFFFEABC 0 O Output Disabled Pull Down
GPIO_47 1 IO
DMM_CLK 2 I
U4 DMM_SYNC TRACE_CTL 0xFFFFEAC0 0 O Output Disabled Pull Down
DMM_SYNC 2 I
V13 MCU_CLKOUT GPIO_25 0xFFFFEA60 0 IO Output Disabled Pull Down
MCU_CLKOUT 1 O
CHIRP_START 2 O
CHIRP_END 6 O
FRAME_START 7 O
EPWM1A 12 O
U14 NERROR_IN NERROR_IN 0xFFFFEA44 0 I Input
U15 NERROR_OUT NERROR_OUT 0xFFFFEA4C 0 O Hi-Z (Open Drain)
V10 PMIC_CLKOUT SOP[2] 0xFFFFEA68 During Power Up I Output Disabled Pull Down
GPIO_27 0 IO
PMIC_CLKOUT 1 O
CHIRP_START 6 O
CHIRP_END 7 O
FRAME_START 8 O
EPWM1B 11 O
EPWM2A 12 O
H3 QSPI[0] GPIO_8 0xFFFFEA2C 0 IO Output Disabled Pull Down
QSPI[0] 1 IO
SPIB_MISO 2 IO
G2 QSPI[1] GPIO_9 0xFFFFEA30 0 IO Output Disabled Pull Down
QSPI[1] 1 I
SPIB_MOSI 2 IO
SPIB_CS_N_2 8 IO
J3 QSPI[2] GPIO_10 0xFFFFEA34 0 IO Output Disabled Pull Down
QSPI[2] 1 I
CAN1_FD_TX 8 O
K2 QSPI[3] GPIO_11 0xFFFFEA38 0 IO Output Disabled Pull Down
QSPI[3] 1 I
CAN1_FD_RX 8 I
H2 QSPI_CLK GPIO_7 0xFFFFEA3C 0 IO Output Disabled Pull Down
QSPI_CLK 1 O
SPIB_CLK 2 IO
DSS_UART_TX 6 O
J2 QSPI_CS_N GPIO_6 0xFFFFEA40 0 IO Output Disabled Pull Up
QSPI_CS_N 1 O
SPIB_CS_N 2 IO
V16 RS232_RX GPIO_15 0xFFFFEA74 0 IO Input Enabled Pull Up
RS232_RX 1 I
MSS_UARTA_RX 2 I
BSS_UART_TX 6 IO
MSS_UARTB_RX 7 IO
CAN1_FD_RX 8 I
I2C_SCL 9 IO
EPWM2A 10 O
EPWM2B 11 O
EPWM3A 12 O
U16 RS232_TX GPIO_14 0xFFFFEA78 0 IO Output Enabled
RS232_TX 1 O
MSS_UARTA_TX 5 IO
MSS_UARTB_TX 6 IO
BSS_UART_TX 7 IO
CAN1_FD_TX 10 O
I2C_SDA 11 IO
EPWM1A 12 O
EPWM1B 13 O
NDMM_EN 14 I
EPWM2A 15 O
D2 SPIA_CLK GPIO_3 0xFFFFEA14 0 IO Output Disabled Pull Up
SPIA_CLK 1 IO
CAN2_FD_RX 6 I
DSS_UART_TX 7 O
C2 SPIA_CS_N GPIO_30 0xFFFFEA18 0 IO Output Disabled Pull Up
SPIA_CS_N 1 IO
CAN1_FD_TX 6 O
D1 SPIA_MISO GPIO_20 0xFFFFEA10 0 IO Output Disabled Pull Up
SPIA_MISO 1 IO
CAN1_FD_TX 2 O
F2 SPIA_MOSI GPIO_19 0xFFFFEA0C 0 IO Output Disabled Pull Up
SPIA_MOSI 1 IO
CAN1_FD_RX 2 I
DSS_UART_TX 8 O
E2 SPIB_CLK GPIO_5 0xFFFFEA24 0 IO Output Disabled Pull Up
SPIB_CLK 1 IO
MSS_UARTA_RX 2 I
MSS_UARTB_TX 6 O
BSS_UART_TX 7 O
CAN1_FD_RX 8 I
D3 SPIB_CS_N GPIO_4 0xFFFFEA28 0 IO Output Disabled Pull Up
SPIB_CS_N 1 IO
MSS_UARTA_TX 2 O
MSS_UARTB_TX 6 O
BSS_UART_TX 7 IO
QSPI_CLK_EXT 8 I
CAN1_FD_TX 9 O
G3 SPIB_MISO GPIO_22 0xFFFFEA20 0 IO Output Disabled Pull Up
SPIB_MISO 1 IO
I2C_SCL 2 IO
DSS_UART_TX 6 O
G1 SPIB_MOSI GPIO_21 0xFFFFEA1C 0 IO Output Disabled Pull Up
SPIB_MOSI 1 IO
I2C_SDA 2 IO
B2 SPI_HOST_INTR GPIO_12 0xFFFFEA00 0 IO Output Disabled Pull Down
SPI_HOST_INTR 1 O
SPIB_CS_N_1 6 IO
U12 SYNC_IN GPIO_28 0xFFFFEA6C 0 IO Output Disabled Pull Down
SYNC_IN 1 I
MSS_UARTB_RX 6 IO
DMM_MUX_IN 7 I
SYNC_OUT 9 O
M3 SYNC_OUT SOP[1] 0xFFFFEA70 During Power Up I Output Disabled Pull Down
GPIO_29 0 IO
SYNC_OUT 1 O
DMM_MUX_IN 9 I
SPIB_CS_N_1 10 IO
SPIB_CS_N_2 11 IO
T3 TCK GPIO_17 0xFFFFEA50 0 IO Input Enabled Pull Down
TCK 1 I
MSS_UARTB_TX 2 O
CAN1_FD_TX 8 O
U9 TDI GPIO_23 0xFFFFEA58 0 IO Input Enabled Pull Up
TDI 1 I
MSS_UARTA_RX 2 I
U10 TDO SOP[0] 0xFFFFEA5C During Power Up I Output Enabled
GPIO_24 0 IO
TDO 1 O
MSS_UARTA_TX 2 O
MSS_UARTB_TX 6 O
BSS_UART_TX 7 O
NDMM_EN 9 I
U8 TMS GPIO_18 0xFFFFEA54 0 IO Input Enabled Pull Down
TMS 1 I
BSS_UART_TX 2 O
CAN1_FD_RX 6 I
U13 WARM_RESET WARM_RESET 0xFFFFEA48 0 IO Hi-Z Input (Open Drain)
R2 LVDS_CLKM LVDS_CLKM O
R1 LVDS_CLKP LVDS_CLKP O
N2 LVDS_TXP[0] LVDS_TXP[0] O
N1 LVDS_TXM[0] LVDS_TXM[0] O
P2 LVDS_TXP[1] LVDS_TXP[1] O
P1 LVDS_TXM[1] LVDS_TXM[1] O
T1 LVDS_FRCLKP LVDS_FRCLKP O
T2 LVDS_FRCLKM LVDS_FRCLKM O
U11 NRESET NRESET I
A7 CLKP CLKP I
B7 CLKM CLKM I
A14 OSC_CLKOUT OSC_CLKOUT O
A16 VBGAP VBGAP O
E1 VDDIN VDDIN PWR
J1 VDDIN VDDIN PWR
V4 VDDIN VDDIN PWR
V8 VDDIN VDDIN PWR
V15 VDDIN VDDIN PWR
A5 VIN_SRAM VIN_SRAM PWR
V6 VIN_SRAM VIN_SRAM PWR
V12 VIN_SRAM VIN_SRAM PWR
C1 VNWA VNWA PWR
V7 VNWA VNWA PWR
V14 VNWA VNWA PWR
H1 VIOIN VIOIN PWR
V9 VIOIN VIOIN PWR
B1 VIOIN_18 VIOIN_18 PWR
F1 VIOIN_18 VIOIN_18 PWR
K1 VIOIN_18 VIOIN_18 PWR
V11 VIOIN_18 VIOIN_18 PWR
C15 VIN_18CLK VIN_18CLK PWR
C18 VIN_18CLK VIN_18CLK PWR
U2 VIOIN_18DIFF VIOIN_18DIFF PWR
V2 VPP VPP PWR
J16 VIN_13RF1 VIN_13RF1 PWR
J17 VIN_13RF1 VIN_13RF1 PWR
J18 VIN_13RF1 VIN_13RF1 PWR
H16 VIN_13RF2 VIN_13RF2 PWR
H17 VIN_13RF2 VIN_13RF2 PWR
H18 VIN_13RF2 VIN_13RF2 PWR
M16 VIN_18BB VIN_18BB PWR
M17 VIN_18BB VIN_18BB PWR
M18 VIN_18BB VIN_18BB PWR
A12 VIN_18VCO VIN_18VCO PWR
C11 VIN_18VCO VIN_18VCO PWR
A1 VSS VSS GND
A2 VSS VSS GND
E3 VSS VSS GND
F3 VSS VSS GND
N3 VSS VSS GND
P3 VSS VSS GND
R3 VSS VSS GND
T4 VSS VSS GND
T5 VSS VSS GND
T6 VSS VSS GND
T7 VSS VSS GND
T8 VSS VSS GND
T9 VSS VSS GND
T10 VSS VSS GND
T11 VSS VSS GND
T12 VSS VSS GND
T13 VSS VSS GND
T14 VSS VSS GND
T15 VSS VSS GND
T16 VSS VSS GND
U1 VSS VSS GND
V1 VSS VSS GND
A6 VSSA VSSA GND
A8 VSSA VSSA GND
A11 VSSA VSSA GND
A13 VSSA VSSA GND
A15 VSSA VSSA GND
A17 VSSA VSSA GND
A18 VSSA VSSA GND
B6 VSSA VSSA GND
B8 VSSA VSSA GND
B9 VSSA VSSA GND
B10 VSSA VSSA GND
B11 VSSA VSSA GND
B12 VSSA VSSA GND
B13 VSSA VSSA GND
B14 VSSA VSSA GND
B15 VSSA VSSA GND
B16 VSSA VSSA GND
B17 VSSA VSSA GND
B18 VSSA VSSA GND
C6 VSSA VSSA GND
C7 VSSA VSSA GND
C8 VSSA VSSA GND
C12 VSSA VSSA GND
C13 VSSA VSSA GND
C14 VSSA VSSA GND
C16 VSSA VSSA GND
C17 VSSA VSSA GND
D16 VSSA VSSA GND
D17 VSSA VSSA GND
D18 VSSA VSSA GND
E16 VSSA VSSA GND
E17 VSSA VSSA GND
E18 VSSA VSSA GND
F16 VSSA VSSA GND
F17 VSSA VSSA GND
F18 VSSA VSSA GND
K16 VSSA VSSA GND
K17 VSSA VSSA GND
K18 VSSA VSSA GND
L16 VSSA VSSA GND
L17 VSSA VSSA GND
L18 VSSA VSSA GND
N16 VSSA VSSA GND
N17 VSSA VSSA GND
N18 VSSA VSSA GND
P16 VSSA VSSA GND
R16 VSSA VSSA GND
R17 VSSA VSSA GND
T17 VSSA VSSA GND
U17 VSSA VSSA GND
U18 VSSA VSSA GND
V17 VSSA VSSA GND
V18 VSSA VSSA GND
A10 VOUT_14APLL VOUT_14APLL O
A9 VOUT_14SYNTH VOUT_14SYNTH O
G16 VOUT_PA VOUT_PA IO
G17 VOUT_PA VOUT_PA IO
G18 VOUT_PA VOUT_PA IO
P18 Analog Test1 / GPADC1 Analog Test1 / GPADC1 IO
P17 Analog Test2 / GPADC2 Analog Test2 / GPADC2 IO
R18 Analog Test3 / GPADC3 Analog Test3 / GPADC3 IO
T18 Analog Test4 / GPADC4 Analog Test4 / GPADC4 IO
C9 ANAMUX / GPADC5 ANAMUX / GPADC5 IO
C10 VSENSE / GPADC6 VSENSE / GPADC6 IO

The following list describes the table column headers:

  1. BALL NUMBER: Ball numbers on the bottom side associated with each signal on the bottom.
  2. BALL NAME: Mechanical name from package device (name is taken from muxmode 1).
  3. SIGNAL NAME: Names of signals multiplexed on each ball (also notice that the name of the ball is the signal name in muxmode 1).
  4. PINCNTL ADDRESS: MSS Address for PinMux Control
  5. MODE: Multiplexing mode number: value written to PinMux Cntl register to select specific Signal name for this Ball number. Mode column has bit range value.
  6. TYPE: Signal type and direction:
    • I = Input
    • O = Output
    • IO = Input or Output
  7. BALL RESET STATE: The state of the terminal after supplies are stable after power-on-reset (NRESET) is asserted
  8. PULL UP/DOWN TYPE: indicates the presence of an internal pullup or pulldown resistor. Pullup and pulldown resistors can be enabled or disabled via software.
    • Pull Up: Internal pullup
    • Pull Down: Internal pulldown
    • An empty box means No pull.
  9. Pin Mux Control Value maps to lower 4 bits of register.

IO MUX registers are available in the MSS memory map and the respective mapping to device pins is as follows:

Table 7-2 PAD IO Control Registers
Default Pin/Ball Name Package Ball /Pin (Address) Pin Mux Config Register
SPI_HOST_INTR B2 0xFFFFEA00
GPIO_0 M2 0xFFFFEA04
GPIO_1 L3 0xFFFFEA08
SPIA_MOSI F2 0xFFFFEA0C
SPIA_MISO D1 0xFFFFEA10
SPIA_CLK D2 0xFFFFEA14
SPIA_CS_N C2 0xFFFFEA18
SPIB_MOSI G1 0xFFFFEA1C
SPIB_MISO G3 0xFFFFEA20
SPIB_CLK E2 0xFFFFEA24
SPIB_CS_N D3 0xFFFFEA28
QSPI[0] H3 0xFFFFEA2C
QSPI[1] G2 0xFFFFEA30
QSPI[2] J3 0xFFFFEA34
QSPI[3] K2 0xFFFFEA38
QSPI_CLK H2 0xFFFFEA3C
QSPI_CS_N J2 0xFFFFEA40
NERROR_IN U14 0xFFFFEA44
WARM_RESET U13 0xFFFFEA48
NERROR_OUT U15 0xFFFFEA4C
TCK T3 0xFFFFEA50
TMS U8 0xFFFFEA54
TDI U9 0xFFFFEA58
TDO U10 0xFFFFEA5C
MCU_CLKOUT V13 0xFFFFEA60
GPIO_2 K3 0xFFFFEA64
PMIC_CLKOUT V10 0xFFFFEA68
SYNC_IN U12 0xFFFFEA6C
SYNC_OUT M3 0xFFFFEA70
RS232_RX V16 0xFFFFEA74
RS232_TX U16 0xFFFFEA78
GPIO_31 U7 0xFFFFEA7C
GPIO_32 U6 0xFFFFEA80
GPIO_33 V5 0xFFFFEA84
GPIO_34 U5 0xFFFFEA88
GPIO_35 V3 0xFFFFEA8C
GPIO_36 M1 0xFFFFEA90
GPIO_37 L2 0xFFFFEA94
GPIO_38 L1 0xFFFFEA98
GPIO_39 C3 0xFFFFEA9C
GPIO_40 B3 0xFFFFEAA0
GPIO_41 C4 0xFFFFEAA4
GPIO_42 A3 0xFFFFEAA8
GPIO_43 B4 0xFFFFEAAC
GPIO_44 A4 0xFFFFEAB0
GPIO_45 C5 0xFFFFEAB4
GPIO_46 B5 0xFFFFEAB8
GPIO_47 U3 0xFFFFEABC
DMM_SYNC U4 0xFFFFEAC0

The register layout is as follows:

Table 7-3 PAD IO Register Bit Descriptions
BIT FIELD TYPE RESET (POWER ON DEFAULT) DESCRIPTION
31-11 NU RW 0 Reserved
10 SC RW 0 IO slew rate control:
0 = Higher slew rate
1 = Lower slew rate
9 PUPDSEL RW 0 Pullup/PullDown Selection
0 = Pull Down
1 = Pull Up (This field is valid only if Pull Inhibit is set as '0')
8 PI RW 0 Pull Inhibit/Pull Disable
0 = Enable
1 = Disable
7 OE_OVERRIDE RW 1 Output Override
6 OE_OVERRIDE_CTRL RW 1 Output Override Control:
(A '1' here overrides any o/p manipulation of this IO by any of the peripheral block hardware it is associated with for example a SPI Chip select)
5 IE_OVERRIDE RW 0 Input Override
4 IE_OVERRIDE_CTRL RW 0 Input Override Control:
(A '1' here overrides any i/p value on this IO with a desired value)
3-0 FUNC_SEL RW 1 Function select for Pin Multiplexing (Refer to the Pin Mux Sheet)

8 Specifications

8.1 Absolute Maximum Ratings

PARAMETERS(1)(2)MINMAXUNIT
VDDIN1.2 V digital power supply–0.51.4V
VIN_SRAM1.2 V power rail for internal SRAM–0.51.4V
VNWA1.2 V power rail for SRAM array back bias–0.51.4V
VIOINI/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this supply.–0.53.8V
VIOIN_181.8 V supply for CMOS IO–0.52V
VIN_18CLK1.8 V supply for clock module–0.52V
VIOIN_18DIFF 1.8 V supply for LVDS port –0.5 2 V
VIN_13RF11.3 V Analog and RF supply, VIN_13RF1 and VIN_13RF2 could be shorted on the board.–0.51.45V
VIN_13RF2
VIN_13RF1
(1-V Internal LDO bypass mode)		 Device supports mode where external Power Management block can supply 1 V on VIN_13RF1 and VIN_13RF2 rails. In this configuration, the internal LDO of the device would be kept bypassed. –0.5 1.4 V
VIN_13RF2
(1-V Internal LDO bypass mode)
VIN_18BB1.8-V Analog baseband power supply–0.52V
VIN_18VCO supply1.8-V RF VCO supply–0.52V
Input and output voltage rangeDual-voltage LVCMOS inputs, 3.3 V or 1.8 V (Steady State)–0.3VVIOIN + 0.3V
Dual-voltage LVCMOS inputs, operated at 3.3 V/1.8 V
(Transient Overshoot/Undershoot) or external oscillator input		VIOIN + 20% up to
20% of signal period
CLKP, CLKMInput ports for reference crystal –0.52V
Clamp currentInput or Output Voltages 0.3 V above or below their respective power rails. Limit clamp current that flows through the internal diode protection cells of the I/O.–2020mA
TJ Operating junction temperature range –40 125 °C
TSTGStorage temperature range after soldered onto PC board–55150°C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.

8.2 ESD Ratings

VALUEUNIT
V(ESD)Electrostatic dischargeHuman-body model (HBM), per AEC Q100-002(1)±2000V
Charged-device model (CDM), per AEC Q100-011(2)±500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) Corner pins are rated as ±750 V

8.3 Power-On Hours (POH)

JUNCTION TEMPERATURE (TJ)(1)(2) OPERATING CONDITION NOMINAL CVDD VOLTAGE (V) POWER-ON HOURS [POH] (HOURS)
–40°C 100% duty cycle 1.2 600 (6%)
75°C 2000 (20%)
95°C 6500 (65%)
125°C 900 (9%)
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms and conditions for TI semiconductor products.
(2) The specified POH are applicable with max Tx output power settings using the default firmware gain tables. The specified POH would not be applicable, if the Tx gain table is overwritten using an API.

8.4 Recommended Operating Conditions

MINNOMMAXUNIT
VDDIN1.2 V digital power supply1.141.21.32V
VIN_SRAM1.2 V power rail for internal SRAM1.141.21.32V
VNWA1.2 V power rail for SRAM array back bias1.141.21.32V
VIOINI/O supply (3.3 V or 1.8 V):
All CMOS I/Os would operate on this supply.		3.133.33.45V
1.711.81.89
VIOIN_181.8 V supply for CMOS IO1.711.81.9V
VIN_18CLK1.8 V supply for clock module1.711.81.9V
VIOIN_18DIFF1.8 V supply for LVDS port1.711.81.9V
VIN_13RF11.3 V Analog and RF supply. VIN_13RF1 and VIN_13RF2 could be shorted on the board1.231.31.36V
VIN_13RF2
VIN_13RF1
(1-V Internal LDO bypass mode)		0.9511.05V
VIN_13RF2
(1-V Internal LDO bypass mode)
VIN18BB1.8-V Analog baseband power supply1.711.81.9V
VIN_18VCO1.8V RF VCO supply1.711.81.9V
VIHVoltage Input High (1.8 V mode)1.17V
Voltage Input High (3.3 V mode)2.25
VILVoltage Input Low (1.8 V mode)0.3*VIOINV
Voltage Input Low (3.3 V mode)0.62
VOHHigh-level output threshold (IOH = 6 mA)VIOIN – 450mV
VOLLow-level output threshold (IOL = 6 mA)450mV
NRESET SOP[2:0]VIL (1.8V Mode)0.45V
VIH (1.8V Mode)0.96
VIL (3.3V Mode)0.65
VIH (3.3V Mode)1.57

 
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