TPS736 具有反向电流保护功能的无电容 NMOS、400mA 低压降稳压器
- ZHCSMC2V September 2003 – September 2024 TPS736
  
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TPS736 具有反向电流保护功能的无电容 NMOS、400mA 低压降稳压器

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1 特性

不借助输出电容器或者任何电容值或类型的电容器即可实现稳定
输入电压范围为 1.7V 至 5.5V
超低压降电压：75mV（典型值）
无论是否使用可选输出电容器，均可实现出色的负载瞬态响应
NMOS 拓扑可提供低反向漏电流
低噪声：30μV_RMS 典型值（10Hz 至 100kHz）
初始精度为 0.5%
整个线路、负载和温度范围内的精度达 1%
关断模式下 I_Q 最大值小于 1μA
热关断和指定最小/最大电流限制保护
提供了多个输出电压版本：
- 1.20V 至 5.0V 固定输出
- 1.20V 至 5.5V 的可调输出
- 可提供定制输出

2 应用

便携式、电池供电类设备
适用于开关电源的后置稳压
噪声敏感电路（如 VCO）
适用于 DSP、FPGA、ASIC 和微处理器的负载点调节

3 说明

TPS736 低压降 (LDO) 线性稳压器采用全新的拓扑结构：在电压跟随器配置中使用 NMOS 导通晶体管。这个拓扑结构在使用具有低等效串联电阻 (ESR) 的输出电容器时保持稳定，甚至可实现无电容器运行。该器件还提供高反向阻断（低反向电流）和接地引脚电流（在所有输出电流值范围内几乎保持恒定）。

TPS736 利用先进的 BiCMOS 工艺实现高精度，同时提供超低压降电压和低接地引脚电流。未启用时，电流消耗低于 1μA，非常适合于便携式应用。极低的输出噪声（0.1μF C_NR 时为 30μV_RMS）使得此器件非常适合为 VCO 供电。该器件受到热关断和折返电流限制的保护。

封装信息

器件型号	封装⁽¹⁾	封装尺寸⁽²⁾
TPS736	DBV（SOT-23，5）	2.9mm × 2.8mm
	DCQ（SOT-223，6）	6.5mm × 7.06mm
	DRB（VSON，8）	3mm × 3mm

(1) 如需更多信息，请参阅机械、封装和可订购信息。

(2) 封装尺寸（长 × 宽）为标称值，并包括引脚（如适用）。

针对固定电压版本的典型应用电路

4 Pin Configuration and Functions

TPS736 DBV Package,5-Pin SOT-23(Top View)

Figure 4-1 DBV Package,5-Pin SOT-23(Top View)

TPS736 DCQ Package,6-Pin SOT-223(Top View)

Figure 4-3 DCQ Package,6-Pin SOT-223(Top View)

Figure 4-2 DRB Package,8-Pin VSON(Top View)

Table 4-1 Pin Functions

PIN				TYPE	DESCRIPTION
NAME	NO.
NAME	SOT-23	SOT-223	VSON
EN	3	5	5	I	Driving the enable pin (EN) high turns on the regulator. Driving this pin low puts the regulator into shutdown mode. See the Enable Pin and Shutdown section for more details. EN can be connected to IN if not used.
FB	4	4	3	I	Adjustable-voltage version only. This pin is the input to the control loop error amplifier, and sets the output voltage of the device.
GND	2	3, 6	4, Pad	—	Ground.
IN	1	1	8	I	Input supply.
NR	4	4	3	—	Fixed-voltage versions only. Connecting an external capacitor to this noise reduction pin bypasses noise generated by the internal band gap, reducing output noise to very low levels.
OUT	5	2	1	O	Output of the regulator. There are no output capacitor requirements for stability.

5 Specifications

5.1 Absolute Maximum Ratings

over operating junction temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Voltage	Input, V_IN	–0.3	6	V
	Enable, V_EN	–0.3	6
	Output, V_OUT	–0.3	5.5
	V_NR, V_FB	–0.3	6
Current	Maximum output, I_OUT	Internally limited
Output short-circuit duration		Indefinite
Continuous total power dissipation	P_DISS	See Thermal Information
Temperature	Operating junction, T_J	–55	150	°C
Temperature	Storage, T_stg	–65	150	°C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

5.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

5.3 Recommended Operating Conditions

over operating junction temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_IN	Input supply voltage	1.7	5.5	V
I_OUT	Output current	0	400	mA
T_J	Operating junction temperature	–40	125	°C

5.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS736 M3 new silicon		UNIT
		DRB (VSON)	DCQ (SOT-223)
		8 PINS	6 PINS
R_θJA	Junction-to-ambient thermal resistance	47.7	76	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	68.9	46.6	°C/W
R_θJB	Junction-to-board thermal resistance	20.6	18.1	°C/W
ψ_JT	Junction-to-top characterization parameter	3.4	8.6	°C/W
ψ_JB	Junction-to-board characterization parameter	20.6	17.6	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	3.5	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.

5.5 Thermal Information

THERMAL METRIC⁽¹⁾⁽²⁾		TPS736 Legacy silicon⁽³⁾			UNIT
		DRB (VSON)	DCQ (SOT-223)	DBV (SOT-23)
		8 PINS	6 PINS	5 PINS
R_θJA	Junction-to-ambient thermal resistance⁽⁴⁾	52.8	118.7	221.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance⁽⁵⁾	60.4	64.9	74.9	°C/W
R_θJB	Junction-to-board thermal resistance⁽⁶⁾	28.4	65.0	51.9	°C/W
ψ_JT	Junction-to-top characterization parameter⁽⁷⁾	2.1	14.0	2.8	°C/W
ψ_JB	Junction-to-board characterization parameter⁽⁸⁾	28.6	63.8	51.1	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance⁽⁹⁾	12.0	N/A	N/A	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application note.

(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.

(3) Thermal data for the DRB, DCQ, and DRV packages are derived by thermal simulations based on JEDEC-standard methodology as specified in the JESD51 series. The following assumptions are used in the simulations:
(a) i. DRB: The exposed pad is connected to the PCB ground layer through a 2x2 thermal via array.
ii. DCQ: The exposed pad is connected to the PCB ground layer through a 3x2 thermal via array.
iii. DBV: There is no exposed pad with the DBV package.
(b) i. DRB: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.
ii. DCQ: Each of top and bottom copper layers has a dedicated pattern for 20% copper coverage.
iii. DBV: The top and bottom copper layers are assumed to have a 20% thermal conductivity of copper representing a 20% copper coverage.
(c) These data were generated with only a single device at the center of a JEDEC high-K (2s2p) board with 3in × 3in copper area. To understand the effects of the copper area on thermal performance, see the Power Dissipation section of this data sheet.

(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(5) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the top of the package. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(6) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

(7) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).

(8) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted from the simulation data to obtain θJA using a procedure described in JESD51-2a (sections 6 and 7).

(9) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

5.6 Electrical Characteristics

Over operating temperature range (T_J = –40°C to 125°C), V_IN = V_OUT(nom) + 0.5V⁽¹⁾, I_OUT = 10mA, V_EN = 1.7V , and C_OUT = 0.1μF , unless otherwise noted. Typical values are at T_J = 25°C

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_IN	Input voltage range⁽¹⁾⁽²⁾			1.7		5.5	V
V_FB	Internal reference (TPS73601)	T_J = 25°C		1.198	1.204	1.210	V
V_OUT	Output voltage range (TPS73601)⁽³⁾			V_FB		5.5 - V_DO	V
	Accuracy⁽¹⁾⁽⁴⁾	Nominal	T_J = 25°C	–0.5		0.5	%
	Accuracy⁽¹⁾⁽⁴⁾	over V_IN, I_OUT, and T	V_OUT + 0.5V ≤ V_IN ≤ 5.5V; 10mA ≤ I_OUT ≤ 400mA	–1	±0.5	1	%
ΔV_OUT(ΔVIN)	Line regulation ⁽¹⁾	V_OUT(NOM) + 0.5V ≤ V_IN ≤ 5.5V			0.01		%/V
ΔV_OUT(ΔIOUT)	Load regulation	1mA ≤ I_OUT ≤ 400mA			0.002		%/mA
ΔV_OUT(ΔIOUT)	Load regulation	10mA ≤ I_OUT ≤ 400mA			0.0005		%/mA
V_DO	Dropout voltage⁽⁵⁾ (V_IN = V_OUT(NOM) - 0.1V)	I_OUT = 400mA			75	200	mV
Z_O(do)	Output impedance in dropout	1.7V ≤ V_IN ≤ V_OUT + V_DO			0.25		Ω
I_CL	Output current limit	V_OUT = 0.9 × V_OUT(nom)	legacy silicon	400	650	800	mA
		3.6V ≤ V_IN ≤ 4.2V, 0℃ ≤ T_J ≤ 70℃	legacy silicon	500		800
		V_OUT = 0.9 × V_OUT(nom)	new silicon, M3 suffix	500		800
I_SC	Short-circuit current	V_OUT = 0V			450		mA
I_REV	Reverse leakage current⁽⁶⁾ (-I_IN)	V_EN ≤ 0.5V, 0V ≤ V_IN ≤ V_OUT			0.1	10	µA
I_GND	Ground pin current	I_OUT = 10mA (I_Q)			400	550	µA
I_GND	Ground pin current	I_OUT = 400mA			800	1000	µA
I_SHDN	Shutdown current (I_GND)	V_EN ≤ 0.5V, V_OUT ≤ V_IN ≤ 5.5V, –40°C ≤ T_J ≤ 100℃, legacy silicon			0.02	1	µA
I_SHDN	Shutdown current (I_GND)	V_EN ≤ 0.5V, V_OUT ≤ V_IN ≤ 5.5V, new silicon, M3 suffix			0.02	1	µA
I_FB	Feedback pin current (TPS73601)				0.1	0.3	µA
PSRR	Power-supply rejection ratio (ripple rejection)	f = 100Hz, I_OUT = 400mA			58		dB
PSRR	Power-supply rejection ratio (ripple rejection)	f = 10kHz, I_OUT = 400mA			37		dB
V_N	Output noise voltage, BW = 10Hz to 100kHz	C_OUT = 10µF, no C_NR			27 x V_OUT		µV_RMS
V_N	Output noise voltage, BW = 10Hz to 100kHz	C_OUT = 10µF, C_NR =0.01µF			8.5 x V_OUT		µV_RMS
t_STR	Startup time	V_OUT = 3V, R_L = 30Ω, C_OUT = 1μF, C_NR = 0.01μF			600		µs
V_EN(high)	EN pin high (enabled)			1.7		V_IN	V
V_EN(low)	EN pin low (shutdown)			0		0.5	V
I_EN(high)	Enable pin current (enabled)	V_EN = 5.5V			0.02	0.1	µA
T_SD	Thermal shutdown temperature	Shutdown, temperature increasing			160		°C
T_SD	Thermal shutdown temperature	Reset, temperature decreasing			140		°C
T_J	Operating junction temperature			–40		125	℃

(1) Minimum V_IN = V_OUT + V_DO or 1.7V, whichever is greater.

(2) For V_OUT(nom) < 1.6V, when V_IN ≤ 1.6V, the output locks to V_IN and may result in a damaging over-voltage condition on the output. To avoid this situation, disable the device before powering down V_IN. (Legacy silicon only)

(3) TPS73601 is tested at V_OUT = 2.5V.

(4) Tolerance of external resistors not included in this specification.

(5) V_DO is not measured for output versions with V_OUT(nom) < 1.8V, because minimum V_IN = 1.7V.

(6) Fixed-voltage versions only; refer to Application Information section for more information.

5.7 Typical Characteristics

For all voltage versions, at T_J = 25°C, V_IN = V_OUT(nom) + 0.5 V, I_OUT = 10 mA, V_EN = 1.7 V, and C_OUT = 0.1 μF, unless otherwise noted.

Legacy silicon

Figure 5-1 Load Regulation

Legacy silicon

Figure 5-3 Line Regulation

TPS736 Dropout Voltage vs Output Current

Legacy silicon

Figure 5-5 Dropout Voltage vs Output Current

Legacy silicon

Figure 5-7 Dropout Voltage vs Temperature

TPS736 Output Voltage Accuracy Histogram

Legacy silicon

Figure 5-9 Output Voltage Accuracy Histogram

TPS736 Ground Pin Current vs Output Current

Legacy silicon

Figure 5-11 Ground Pin Current vs Output Current

TPS736 Ground Pin Current vs Temperature

Legacy silicon

Figure 5-13 Ground Pin Current vs Temperature

TPS736 Ground Pin Current In Shutdown vs Temperature

Legacy silicon

Figure 5-15 Ground Pin Current In Shutdown vs Temperature

Legacy silicon

Figure 5-17 Current Limit vs V_OUT (Foldback)

Legacy silicon

Figure 5-19 Current Limit vs V_IN

Legacy silicon

Figure 5-21 Current Limit vs Temperature

TPS736 PSRR
(Ripple Rejection) vs Frequency

Legacy silicon

Figure 5-23 PSRR (Ripple Rejection) vs Frequency

TPS736 PSRR
(Ripple Rejection) vs VIN – VOUT

Legacy silicon

Figure 5-25 PSRR (Ripple Rejection) vs V_IN – V_OUT

TPS736 Noise
Spectral Density CNR = 0 μF

Legacy silicon

Figure 5-27 Noise Spectral Density C_NR = 0 μF

TPS736 Noise
Spectral Density CNR = 0.01 μF

Legacy silicon

Figure 5-29 Noise Spectral Density C_NR = 0.01 μF

Legacy silicon

Figure 5-31 RMS Noise Voltage vs C_OUT

Legacy silicon

Figure 5-33 RMS Noise Voltage vs C_NR

Legacy silicon

Figure 5-35 TPS73633 Load Transient Response

Legacy silicon

Figure 5-37 TPS73633 Line Transient Response

Legacy silicon

Figure 5-39 TPS73633 Turn-On Response

Legacy silicon

Figure 5-41 TPS73633 Turn-Off Response

Legacy silicon

Figure 5-43 TPS73633 Power-Up, Power-Down

Legacy silicon

Figure 5-45 I_ENABLE vs Temperature

TPS736 TPS73601 RMS Noise Voltage vs CFB

Legacy silicon

Figure 5-47 TPS73601 RMS Noise Voltage vs C_FB

Legacy silicon

Figure 5-49 TPS73601 I_FB vs Temperature

TPS736 TPS73601 Load Transient, Adjustable Version

Legacy silicon

Figure 5-51 TPS73601 Load Transient, Adjustable Version

TPS736 TPS73601 Line Transient, Adjustable Version

Legacy silicon

Figure 5-53 TPS73601 Line Transient, Adjustable Version

New silicon, M3 suffix

Figure 5-2 Load Regulation

New silicon, M3 suffix

Figure 5-4 Line Regulation

New silicon, M3 suffix

Figure 5-6 Dropout Voltage vs Output Current

New silicon, M3 suffix

Figure 5-8 Dropout Voltage vs Temperature

Legacy silicon

Figure 5-10 Output Voltage Drift Histogram

New silicon, M3 suffix

Figure 5-12 Ground Pin Current vs Output Current

New silicon, M3 suffix

Figure 5-14 Ground Pin Current vs Temperature

New silicon, M3 suffix

Figure 5-16 Ground Pin Current in Shutdown vs Temperature

New silicon, M3 suffix

Figure 5-18 Current Limit vs V_OUT (Foldback)

New silicon, M3 suffix

Figure 5-20 Current Limit vs V_IN

New silicon, M3 suffix

Figure 5-22 Current Limit vs Temperature

New silicon, M3 suffix

Figure 5-24 PSRR (Ripple Rejection) vs Frequency

New silicon, M3 suffix

Figure 5-26 PSRR (Ripple Rejection) vs V_IN – V_OUT

New silicon, M3 suffix

Figure 5-28 Noise Spectral Density C_NR = 0 μF

New silicon, M3 suffix

Figure 5-30 Noise Spectral Density C_NR = 0.01 μF

New silicon, M3 suffix

Figure 5-32 RMS Noise Voltage vs C_OUT

New silicon, M3 suffix

Figure 5-34 RMS Noise Voltage vs C_NR

New silicon, M3 suffix

Figure 5-36 TPS73633 Load Transient Response

New silicon, M3 suffix

Figure 5-38 TPS73633 Line Transient Response

New silicon, M3 suffix

Figure 5-40 TPS73633 Turn-On Response

New silicon, M3 suffix

Figure 5-42 TPS73633 Turn-Off Response

New silicon, M3 suffix

Figure 5-44 TPS73633 Power-Up, Power-Down

New silicon, M3 suffix

Figure 5-46 I_ENABLE vs Temperature

New silicon, M3 suffix

Figure 5-48 TPS73601 RMS Noise Voltage vs C_FB

New silicon, M3 suffix

Figure 5-50 TPS73601 I_FB vs Temperature

New silicon, M3 suffix

Figure 5-52 TPS73601 Load Transient, Adjustable Version

New silicon, M3 suffix

Figure 5-54 TPS73601 Line Transient, Adjustable Version

6 Detailed Description

6.1 Overview

The TPS736 low-dropout linear regulator operates down to an input voltage of 1.7 V and supports output voltages down to 1.2 V while sourcing up to 400 mA of load current. This linear regulator uses an NMOS pass transistor with an integrated 4-MHz charge pump to provide a dropout voltage of less than 200 mV at full load current. This unique architecture also permits stable regulation over a wide range of output capacitors. In fact, the TPS736 device does not require any output capacitor for stability. The increased insensitivity to the output capacitor value and type makes this linear regulator an ideal choice when powering a load where the effective capacitance is unknown.

The TPS736 also features a noise reduction (NR) pin that allows for additional reduction of the output noise. With a noise reduction capacitor of 0.01 µF connected from the NR pin to GND, the TPS73615 output noise can be as low as 12.75 µV_RMS. The low noise output featured by the TPS736 makes the device well-suited for powering VCOs or any other noise sensitive load.

6.2 Functional Block Diagrams

Figure 6-1 Fixed-Voltage Version

Figure 6-2 Adjustable-Voltage Version