ADC3660 16 位、0.5 至 65 MSPS、低噪声、低功率双通道 ADC
- ZHCSM31B September 2020 – March 2022 ADC3660
  
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DATA SHEET

ADC3660 16 位、0.5 至 65 MSPS、低噪声、低功率双通道 ADC

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

双通道
16 位 65MSPS ADC（最大输出速率 = 31Msps）
本底噪声：-159dBFS/Hz
超低功耗：65MSPS 时为每通道 71mW
16 位，无丢码
INL：±2LSB；DNL：±0.2LSB
基准：外部或内部
输入带宽：900MHz (3dB)
工业温度范围：-40°C 至 +105°C
片上数字下变频器
- 2 倍、4 倍、8 倍、16 倍、32 倍抽取率
- 32 位 NCO
串行 CMOS 接口
1.8V 单电源
小尺寸: 40 引脚 WQFN (5mm × 5mm) 封装
频谱性能 (f_IN = 5MHz)：
- SNR：81.9dBFS
- SFDR：88dBc HD2、HD3
- SFDR：102dBFS 最严重毛刺

2 应用

3 说明

ADC3660 器件是一款低噪声、超低功耗、16 位、65MSPS 双通道高速模数转换器 (ADC)。该器件可实现低功耗，噪声频谱密度为 –159dBFS/Hz，还具有出色的线性度和动态范围。ADC3660 可实现出色的直流精度以及中频采样支持，因此是各种应用的出色选择。该 ADC 在 65MSPS 下的功耗仅为每通道 71mW，功耗随采样率减小而迅速降低。在旁路模式（最高 31MSPS）下，您可以在 1 或 2 个时钟周期后获取输出数据。

ADC3660 使用串行 CMOS (SCMOS) 接口输出数据，可更大限度减少数字互连的次数。该器件提供双通道、单通道和半通道选项。串行 CMOS 接口支持高达 250Mbps 的输出速率，相当于在复杂抽取后大约 15MSPS（双线）到大约 3.75MSPS（0.5 线）的输出速率。因此，ADC3660 可以使用内部抽取滤波器在“过采样和抽取”模式下运行，从而改进动态范围并省去外部抗混叠滤波器。

该器件采用 40 引脚 WQFN 封装（5mm × 5mm），支持 –40 至 +105⁰C 的工业级工作温度范围。

器件信息

器件型号 ⁽¹⁾	封装	封装尺寸（标称值）
ADC3660	WQFN (40)	5.00 × 5.00mm

(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。

FS = 65MSPS，F_in = 1MHz，16 倍抽取，实时

4 Revision History

Changes from Revision A (October 2020) to Revision B (March 2022)

Changed the output clock jitter unit from ps to ps pk-pk in the Timing RequirementsGo
Changed the ADC latency CMOS 2-wire NOM value from 1 to 2 and 1/2-wire NOM value from 2 to 1Go
Changed Figure 8-3 Go
Added GND symbol to REFGND pin for all voltage reference option diagramsGo
Added the Output Bit Mapper sectionGo
Added default power up configuration summary Table 8-11 Go
Updated power-up initialization diagram Figure 9-4 with the correct indexing Go

Changes from Revision * (September 2020) to Revision A (October 2020)

Added Updated characterization data for t_CD and t_DV Go
Added condition to resynch during operation to the SYNC sectionGo
added wait condition of 200000 clock cyclesGo

5 Pin Configuration and Functions

Figure 5-1 RSB Package, 40-Pin WQFN
(Top View)

Table 5-1 Pin Descriptions

PIN		I/O	Description
Name	No.	I/O	Description
INPUT/REFERENCE
AINP	12	I	Positive analog input, channel A
AINM	13	I	Negative analog input, channel A
BINP	39	I	Positive analog input, channel B
BINM	38	I	Negative analog input, channel B
VCM	8	O	Common-mode voltage output for the analog inputs, 0.95 V
VREF	2	I	External voltage reference input, 1.6 V
REFBUF	4	I	1.2V external voltage reference input for use with internal reference buffer. Internal 100 kΩ pull-up resistor to AVDD. This pin is also used to configure default operating conditions.
REFGND	3	I	Reference ground input, 0 V
CLOCK
CLKP	6	I	Positive differential sampling clock input for the ADC
CLKM	7	I	Negative differential sampling clock input for the ADC
CONFIGURATION
PDN/SYNC	1	I	Power down/Synchronization input. This pin can be configured via the SPI interface. Active high. This pin has an internal 21 kΩ pull-down resistor.
RESET	9	I	Hardware reset. Active high. This pin has an internal 21 kΩ pull-down resistor.
SEN	16	I	Serial interface enable. Active low. This pin has an internal 21 kΩ pull-up resistor to AVDD.
SCLK	35	I	Serial interface clock input. This pin has an internal 21 kΩ pull-down resistor.
SDIO	10	I/O	Serial interface data input and output. This pin has an internal 21 kΩ pull-down resistor.
NC	17,19,20,22, 29,31,32,34	-	Do not connect
DIGITAL INTERFACE
DA6	24	O	CMOS data output.
DA5	23	O	CMOS data output
FCLK	18	O	CMOS frame clock output
DB6	27	O	CMOS data output.
DB5	28	O	CMOS data output
DCLKIN	33	I	CMOS bit clock input
DCLK	25	O	CMOS bit clock output
POWER SUPPLY
AVDD	5,15,36	I	Analog 1.8V power supply
GND	11,14,37,40, PowerPad	I	Ground, 0V
IOVDD	21,30	I	1.8V power supply for digital interface
IOGND	26	I	Ground, 0V for digital interface

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER	TEST CONDITIONS	MIN	MAX	UNIT
Supply voltage range, AVDD, IOVDD		–0.3	2.1	V
Supply voltage range, GND, IOGND, REFGND		–0.3	0.3	V
Voltage applied to input pins	AINP/M, BINP/M, CLKP/M	–0.3	2.1	V
	VREF, REFBUF	–0.3	2.1
	PDN/SYNC, RESET, SCLK, SEN, SDIO, DCLKIN	–0.3	2.1
Junction temperature, T_J			105	°C
Storage temperature, T_stg		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	2500	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

			MIN	NOM	MAX	UNIT
Supply voltage range		AVDD⁽¹⁾	1.75	1.8	1.85	V
Supply voltage range		IOVDD⁽¹⁾	1.75	1.8	1.85	V
T_A	Operating free-air temperature		–40		105	°C
T_J	Operating junction temperature				105⁽²⁾	°C

(1) Measured to GND.

(2) Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		ADC3660	UNIT
		RSB (QFN)
		40 Pins
R_ΘJA	Junction-to-ambient thermal resistance	30.7	°C/W
R_ΘJC(top)	Junction-to-case (top) thermal resistance	16.4	°C/W
R_ΘJB	Junction-to-board thermal resistance	10.5	°C/W
Ψ_JT	Junction-to-top characterization parameter	0.2	°C/W
Ψ_JB	Junction-to-board characterization parameter	10.5	°C/W
R_ΘJC(bot)	Junction-to-case (bottom) thermal resistance	2.0	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics - Power Consumption

Typical values are over the operating free-air temperature range, at T_A = 25°C, full temperature range is T_MIN = –40°C to T_MAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6 V reference, 5 pF output load, and –1-dBFS differential input, unless otherwise noted

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
FS = 65 MSPS
I_AVDD	Analog supply current	FS = 65 MSPS, External reference	64	78	mA
I_IOVDD	I/O supply current⁽¹⁾	8x real decimation, 2-wire CMOS	15	20	mA
P_DIS	Power dissipation⁽¹⁾	External reference	142	178	mW
I_IOVDD	I/O supply current⁽¹⁾	16x real decimation, 1-wire CMOS	14		mA
		32x real decimation, 1-wire CMOS	12		mA
		32x real decimation, 1/2-wire CMOS	13		mA
		8x complex decimation, 2-wire CMOS	19		mA
		16x complex decimation, 1-wire CMOS	17		mA
		32x complex decimation, 1-wire CMOS	15
		32x complex decimation, 1/2-wire CMOS	16
MISCELLANEOUS
I_AVDD	Internal reference, additional analog supply current	Enabled via SPI	3		mA
	Internal reference buffer, additional analog supply current		0.3
	Single ended clock input, reduces analog supply current by		0.7
P_DIS	Power consumption in global power down mode	Default mask settings, internal reference	5		mW
P_DIS	Power consumption in global power down mode	Default mask settings, external reference	9		mW

(1) Measured with a 1 MHz input frequency full-scale sine wave at specified sample rate, with ~ 5 pF loading on each CMOS output pin.

6.6 Electrical Characteristics - DC Specifications

Typical values are over the operating free-air temperature range, at T_A = 25°C, full temperature range is T_MIN = –40°C to T_MAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6 V reference, and –1-dBFS differential input, unless otherwise noted

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
DC ACCURACY
No missing codes			16			bits
PSRR		F_IN = 1 MHz		50		dB
DNL	Differential nonlinearity	F_IN = 5 MHz	-0.5	± 0.2	+1	LSB
INL⁽¹⁾	Integral nonlinearity	F_IN = 5 MHz	-4.5	± 2	+4.5	LSB
V_{OS_ERR}	Offset error		-130	2	130	LSB
V_{OS_DRIFT}	Offset drift over temperature			-3.5		LSB/ºC
GAIN_ERR	Gain error	External 1.6V Reference		0		%FSR
GAIN_DRIFT	Gain drift over temperature	External 1.6V Reference		10.3		ppm/ºC
GAIN_ERR	Gain error	Internal Reference		2.4		%FSR
GAIN_DRIFT	Gain drift over temperature	Internal Reference		108.8		ppm/ºC
Transition Noise				1.5		LSB
ADC ANALOG INPUT (AINP/M, BINP/M)
FS	Input full scale	Differential		3.2		Vpp
V_CM	Input common model voltage		0.9	0.95	1.0	V
R_IN	Differential input resistance	F_IN = 100 kHz		8		kΩ
C_IN	Differential input Capacitance	F_IN = 100 kHz		7		pF
V_OCM	Output common mode voltage			0.95		V
BW	Analog Input Bandwidth (-3dB)			900		MHz
INTERNAL VOLTAGE REFERENCE
V_REF	Internal reference voltage			1.6		V
V_REFOutput Impedance				8		Ω
REFERENCE INPUT BUFFER (REFBUF)
External reference voltage				1.2		V
EXTERNAL VOLTAGE REFERENCE (VREF)
V_REF	External voltage reference			1.6		V
Input Current				0.3		mA
Input impedance				5.3		kΩ
CLOCK INPUT (CLKP/M)
Input clock frequency			0.5		65	MHz
V_ID	Differential input voltage			1	3.6	Vpp
V_CM	Input common mode voltage			0.9		V
R_IN	Single ended input resistance to common mode.			5		kΩ
C_IN	Single ended input capacitance			1.5		pF
Clock duty cycle			40	50	60	%
DIGITAL INPUTS (RESET, PDN, SCLK, SEN, SDIO)
V_IH	High level input voltage		1.4			V
V_IL	Low level input voltage				0.4	V
I_IH	High level input current			90	150	uA
I_IL	Low level input current		-150	-90		uA
C_I	Input capacitance			1.5		pF
DIGITAL OUTPUT (SDOUT)
V_OH	High level output voltage	I_LOAD = -400 uA	IOVDD – 0.1	IOVDD		V
V_OL	Low level output voltage	I_LOAD = 400 uA			0.1	V
DIGITAL SCMOS OUTPUTS (DA5/6, DB5/6)
Output data rate		per CMOS output pin			250	MHz
V_OH	High level output voltage	per CMOS output pin	IOVDD – 0.1	IOVDD		V
V_OL	Low level output voltage	I_LOAD = 400 uA			0.1	V
V_IH	High level input voltage	DCLKIN	IOVDD – 0.1	IOVDD		V
V_IL	Low level input voltage	DCLKIN			0.1	V

(1) Performance data shown is prior to decimation filtering. With DDC enabled, performance improves by the decimation filtering process.

6.7 Electrical Characteristics - AC Specifications

Typical values are over the operating free-air temperature range, at T_A = 25°C, full temperature range is T_MIN = –40°C to T_MAX = 105°C, ADC sampling rate = 65 MSPS, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6 V reference, and –1-dBFS differential input, unless otherwise noted

PARAMETER		TEST CONDITIONS	MIN	TYP	UNIT
NSD	Noise Spectral Density	f_IN = 1.1 MHz, A_IN = -20 dBFS		-159	dBFS/Hz
SNR⁽¹⁾	Signal to noise ratio	f_IN = 1.1 MHz		82.0	dBFS
		f_IN = 5 MHz	77.5	81.9
		f_IN = 10 MHz		81.2
		f_IN = 20 MHz		79.9
		f_IN = 40 MHz		77.6
		f_IN = 64 MHz		74.6
SNR	Signal to noise ratio, complex decimation by 16	f_IN = 1.1 MHz, f_NCO = 2.5 MHz		88.3	dBFS
		f_IN = 5 MHz, f_NCO = 5 MHz		89.2
		f_IN = 10 MHz, f_NCO = 10 MHz		89.3
		f_IN = 20 MHz, f_NCO = 20 MHz		88.7
		f_IN = 40 MHz, f_NCO = 40 MHz		86.5
		f_IN = 64 MHz, f_NCO = 62.6 MHz		84.3
SINAD⁽¹⁾	Signal to noise and distortion ratio	f_IN = 1.1 MHz		80.0	dBFS
		f_IN = 5 MHz	76.2	80.9
		f_IN = 10 MHz		80.8
		f_IN = 20 MHz		78.1
		f_IN = 40 MHz		76.2
		f_IN = 64 MHz		73.6
ENOB⁽¹⁾	Effective number of bits	f_IN = 1.1 MHz		13.3	bit
		f_IN = 5 MHz	12.6	13.3
		f_IN = 10 MHz		13.2
		f_IN = 20 MHz		13.0
		f_IN = 40 MHz		12.6
		f_IN = 64 MHz		12.1
THD⁽¹⁾	Total Harmonic Distortion (First five harmonics)	f_IN = 1.1 MHz		83	dBc
		f_IN = 5 MHz	81	87
		f_IN = 10 MHz		90
		f_IN = 20 MHz		82
		f_IN = 40 MHz		81
		f_IN = 64 MHz		80
SFDR⁽¹⁾	Spur free dynamic range including second and third harmonic	f_IN = 1.1 MHz		84	dBc
		f_IN = 5 MHz	83	88
		f_IN = 10 MHz		94
		f_IN = 20 MHz		85
		f_IN = 40 MHz		83
		f_IN = 64 MHz		84	dBc
Non HD2,3⁽¹⁾	Spur free dynamic range (excluding HD2 and HD3)	f_IN = 1.1 MHz		101	dBFS
		f_IN = 5 MHz	91	102
		f_IN = 10 MHz		99
		f_IN = 20 MHz		95
		f_IN = 40 MHz		93
		f_IN = 64 MHz		87
IMD3	Two tone inter-modulation distortion	f₁ = 3 MHz, f₂ = 4 MHz, A_IN = -7 dBFS/tone		88	dBc
IMD3	Two tone inter-modulation distortion	f₁ = 10 MHz, f₂ = 12 MHz, A_IN = -7 dBFS/tone		90	dBc

(1) Performance data shown is prior to decimation filtering. With DDC enabled, performance improves by the decimation filtering process.

6.8 Timing Requirements

PARAMETER		TEST CONDITIONS	MIN	NOM	MAX	UNIT
ADC TIMING SPECIFICATIONS
t_AD	Aperture Delay			0.85		ns
t_A	Aperture Jitter	square wave clock with fast edges		180		fs
t_J	Jitter on DCLKIN				± 50	ps pk-pk
t_ACQ	Signal acquisition period, Default	referenced to sampling clock falling edge		-T_S/4		Sampling Clock Period
t_CONV	Signal conversion period	referenced to sampling clock falling edge		10		ns
Wake up time	Time to valid data after coming out of power down. Internal reference.	Bandgap reference enabled, single ended clock		14.6		us
		Bandgap reference enabled, differential clock		14.0		us
		Bandgap reference disabled, single ended clock		1.7		ms
		Bandgap reference disabled, differential clock		2.1		ms
	Time to valid data after coming out of power down. External 1.6V reference.	Bandgap reference enabled, single ended clock		14.6		us
		Bandgap reference enabled, differential clock		14.0		us
		Bandgap reference disabled, single ended clock		1.8		ms
		Bandgap reference disabled, differential clock		1.7		ms
t_S,SYNC	Setup time for SYNC input signal	Referenced to sampling clock rising edge	500			ps
t_H,SYNC	Hold time for SYNC input signal	Referenced to sampling clock rising edge	600			ps
ADC Latency	Signal input to data output	Serialized CMOS: 2-wire		2		ADC clock cycles
		Serialized CMOS: 1-wire		1
		Serialized CMOS: 1/2-wire		1
Add. Latency	Real decimation by 2			21		Output clock cycles
	Complex decimation by 2			22
	Real or complex decimation by 4, 8, 16, 32			23
INTERFACE TIMING
t_PD	Propagation delay: sampling clock falling edge to DCLK rising edge	Delay between sampling clock falling edge to DCLKIN falling edge < 2.5ns. T_DCLK = DCLK period t_CDCLK = Sampling clock falling edge to DCLKIN falling edge	2 + T_DCLK + t_CDCLK	3 + T_DCLK + t_CDCLK	4 + T_DCLK + t_CDCLK	ns
t_PD		Delay between sampling clock falling edge to DCLKIN falling edge >= 2.5ns. T_DCLK = DCLK period t_CDCLK = Sampling clock falling edge to DCLKIN falling edge	2 + t_CDCLK	3 + t_CDCLK	4 + t_CDCLK	ns
t_CD	DCLK rising edge to output data delay 2-wire serial CMOS	Fout = 10 MSPS, DA/B5,6 = 80 MBPS	-0.24	0.10		ns
		Fout = 20 MSPS, DA/B5,6 = 160 MBPS	-0.29	0.10
		Fout = 30 MSPS, DA/B5,6 = 240 MBPS	-0.28	0.09
	DCLK rising edge to output data delay 1-wire serial CMOS	Fout = 5 MSPS, DA/B6 = 80 MBPS	-0.22	0.11
		Fout = 10 MSPS, DA/B6 = 160 MBPS	-0.27	0.11
		Fout = 15 MSPS, DA/B6 = 240 MBPS	-0.52	0.08
	DCLK rising edge to output data delay 1/2-wire serial CMOS	Fout = 5 MSPS, DA6 = 160 MBPS	-0.24	0.1
t_DV	Data valid, 2-wire serial CMOS	Fout = 10 MSPS, DA/B5,6 = 80 MBPS	12.19	12.36		ns
		Fout = 20 MSPS, DA/B5,6 = 160 MBPS	5.93	6.1
		Fout = 30 MSPS, DA/B5,6 = 240 MBPS	3.91	4.07
	Data valid, 1-wire serial CMOS	Fout = 5 MSPS, DA/B6 = 80 MBPS	12.21	12.39
		Fout = 10 MSPS, DA/B6 = 160 MBPS	5.95	6.10
		Fout = 15 MSPS, DA/B6 = 240 MBPS	3.83	4.08
	Data valid, 1/2-wire serial CMOS	Fout = 5 MSPS, DA6 = 160 MBPS	5.36	6.13
SERIAL PROGRAMMING INTERFACE (SCLK, SEN, SDIO) - Input
f_CLK,SCLK	Serial clock frequency				20	MHz
t_S,SEN	SEN falling edge to SCLK rising edge		10			ns
t_H,SEN	SCLK rising edge to SEN rising edge		9
t_S,SDIO	SDIO setup time from rising edge of SCLK		17
t_H,SDIO	SDIO hold time from rising edge of SCLK		9
SERIAL PROGRAMMING INTERFACE (SDIO) - Output
t_OZD	Delay from falling edge of 16th SCLK cycle during read operation for SDIO transition from tri-state to valid data		3.9		10.8	ns
t_ODZ	Delay from SEN rising edge for SDIO transition from valid data to tri-state		3.4		14
t_OD	Delay from falling edge of 16th SCLK cycle during read operation to SDIO valid		3.9		10.8

6.9 Typical Characteristics

Typical values at T_A = 25 °C, ADC sampling rate = 65 MSPS, A_IN = –1 dBFS differential input, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6 V reference, 5 pF output load, unless otherwise noted.

DECIMATION BYPASS⁽¹⁾

Figure 6-1 Single Tone FFT at F_IN = 1.1 MHz

DECIMATION BYPASS^¹

Figure 6-3 Single Tone FFT at F_IN = 10 MHz

A_IN = -7 dBFS/tone, DECIMATION BYPASS^¹

Figure 6-5 Two Tone FFT at F_IN = 3,4 MHz

A_IN = -7 dBFS/tone, DECIMATION BYPASS^¹

Figure 6-7 Two Tone FFT at F_IN = 10,12 MHz

Decimation by 32, complex. NCO = 10.1 MHz

Figure 6-9 Single Tone FFT at F_IN = 10 MHz

DECIMATION BYPASS^¹

Figure 6-11 ENOB vs Input Frequency

F_IN = 5 MHz, DECIMATION BYPASS^¹

Figure 6-13 AC Performance vs Sampling Rate

F_IN = 5 MHz, DECIMATION BYPASS^¹

Figure 6-15 AC Performance vs Clock Duty cycle

F_IN = 5 MHz, DECIMATION BYPASS^¹

Figure 6-17 ENOB vs AVDD

DECIMATION BYPASS^¹

Figure 6-19 DC Offset Histogramm

F_IN = 5 MHz, DECIMATION BYPASS^¹

Figure 6-21 DNL vs Code

F_S = 25 MSPS, A_IN = –20 dBFS, DECIMATION BYPASS^¹

Figure 6-23 Single Tone FFT at F_IN = 1.1 MHz

F_S = 25 MSPS, Decimation by 8, real

Figure 6-25 Single Tone FFT at F_IN = 1 MHz

F_S = 25 MSPS, DECIMATION BYPASS^¹

Figure 6-27 ENOB vs Input Frequency

F_S = 25 MSPS, F_IN = 5 MHz, DECIMATION BYPASS^¹

Figure 6-29 AC Performance vs Clock Amplitude

F_S = 25 MSPS, F_IN = 5 MHz, DECIMATION BYPASS^¹

Figure 6-31 AC Performance vs V_CM vs Temperature

F_S = 25 MSPS, F_IN = 5 MHz, DECIMATION BYPASS^¹

Figure 6-33 DNL vs Code

F_IN = 5 MHz, 50 mVpp signal on AVDD

Figure 6-35 PSRR vs Frequency

F_IN = 1 MHz, 16-bit resolution, 2-w

Figure 6-37 I_IOVDD Current vs Decimation

A_IN = –20 dBFS, DECIMATION BYPASS^¹

Figure 6-2 Single Tone FFT at F_IN = 1.1 MHz

DECIMATION BYPASS^¹

Figure 6-4 Single Tone FFT at F_IN = 40 MHz

A_IN = -20 dBFS/tone, DECIMATION BYPASS^¹

Figure 6-6 Two Tone FFT at F_IN = 3,4 MHz

Decimation by 16, real

Figure 6-8 Single Tone FFT at F_IN = 1 MHz

DECIMATION BYPASS^¹

Figure 6-10 AC Performance vs Input Frequency

F_IN = 5 MHz, DECIMATION BYPASS^¹

Figure 6-12 AC Performance vs Input Amplitude

DECIMATION BYPASS^¹

Figure 6-14 AC Performance vs Clock Amplitude

F_IN = 5 MHz, DECIMATION BYPASS^¹

Figure 6-16 AC Performance vs AVDD

F_IN = 5 MHz, DECIMATION BYPASS^¹

Figure 6-18 AC Performance vs VCM vs Temperature

F_IN = 5 MHz, DECIMATION BYPASS^¹

Figure 6-20 INL vs Code

F_S = 25 MSPS, DECIMATION BYPASS^¹

Figure 6-22 Single Tone FFT at F_IN = 1.1 MHz

F_S = 25 MSPS, DECIMATION BYPASS^¹

Figure 6-24 Single Tone FFT at F_IN = 10 MHz

F_S = 25 MSPS, DECIMATION BYPASS^¹

Figure 6-26 AC Performance vs Input Frequency

F_S = 25 MSPS, F_IN = 5 MHz, DECIMATION BYPASS^¹

Figure 6-28 AC Performance vs Input Amplitude

F_S = 25 MSPS, F_IN = 5 MHz, DECIMATION BYPASS^¹

Figure 6-30 AC Performance vs AVDD

F_S = 25 MSPS, F_IN = 5 MHz, DECIMATION BYPASS^¹

Figure 6-32 INL vs Code

Aggressor at -1 dBFS

Figure 6-34 Isolation vs Input Frequency

F_IN = 1 MHz, 32x complex decimation, 16-bit resolution

Figure 6-36 Current vs Sampling Rate

F_IN = 1 MHz, 32x complex decimation, 16-bit resolution, 2-w

Figure 6-38 I_IOVDD Current vs Load Capacitance

Decimation bypass mode is for full Nyquist zone illustration only.

7 Parameter Measurement Information

Figure 7-1 Timing diagram: 2-wire SCMOS (changed from 18-bit to 16-bit output after power up)

Figure 7-2 Timing diagram: 1-wire SCMOS (changed from 18-bit to 16-bit output after power up)

Figure 7-3 Timing diagram: 1/2-wire SCMOS (changed from 18-bit to 16-bit output after power up)

8 Detailed Description

8.1 Overview

The ADC3660 is a low noise, ultra-low power 16-bit high-speed dual channel ADC family supporting sampling rates up to 65Msps. It offers excellent DC precision together with IF sampling support which makes it ideally suited for a wide range of applications. The ADC3660 is equipped with an internal reference option but it also supports the use of an external, high precision 1.6V voltage reference or an external 1.2V reference which is buffered and gained up internally.

An optional programmable digital down converter enables external anti-alias filter relaxation as well as output data rate reduction. The digital filter provides a 32-bit programmable NCO and supports both real or complex decimation.

Note: The ADC3660 uses a serial CMOS (SCMOS) interface to output the data which minimizes the number of digital interconnects. The device supports a two-lane (2-wire), a one-lane (1-wire) and a half lane (1/2-wire) interface option. The serialized CMOS interface supports output rates up to 250Mbps which translates to the following maximum output rates:

Decimation Bypass Mode: ~ 31 Msps (2-wire) to ~ 8 Msps (0.5-wire)
Complex Decimation: ~ 15 Msps (2-wire) to ~4 Msps (0.5-wire)
Real Decimation: ~ 30 Msps (2-wire) to ~ 8 Msps (0.5-wire)

Hence the ADC3660 can be operated in 'oversampling and decimating' mode using the internal decimation filter in order to improve the dynamic range and relax external anti-aliasing filter.

The ADC3660 includes a digital output formatter which supports output resolutions from 14 to 20-bit.

The device features and control options can be set up either through pin configurations or via SPI register writes.

8.2 Functional Block Diagram

8.3 Feature Description

8.3.1 Analog Input

The analog inputs of ADC3660 are intended to be driven differentially. Both AC coupling and DC coupling of the analog inputs is supported. The analog inputs are designed for an input common mode voltage of 0.95 V which must be provided externally on each input pin. DC-coupled input signals must have a common mode voltage that meets the device input common mode voltage range.

The equivalent input network diagram is shown in Figure 8-1. All four sampling switches, on-resistance shown in red, are in same position (open or closed) simultaneously.

Figure 8-1 Equivalent Input Network

8.3.1.1 Analog Input Bandwidth

Figure 8-2 shows the analog full power input bandwidth of the ADC3660 with a 50 Ω differential termination. The -3 dB bandwidth is approximately 900 MHz and the useful input bandwidth with good AC performance is approximately 120 MHz.

The equivalent differential input resistance R_IN and input capacitance C_IN vs frequency are shown in Figure 8-3.

Figure 8-2 ADC Analog Input Bandwidth Response

Figure 8-3 Equivant R_IN, C_IN vs Input Frequency

8.3.1.2 Analog Front End Design

The ADC3660 is an unbuffered ADC and thus a passive kick-back filter is recommended to absorb the glitch from the sampling operation. Depending on if the input is driven by a balun or a differential amplifier with low output impedance, a termination network may be needed. Additionally a passive DC bias circuit is needed in AC-coupled applications which can be combined with the termination network.

8.3.1.2.1 Sampling Glitch Filter Design

The front end sampling glitch filter is designed to optimize the SNR and HD3 performance of the ADC. The filter performance is dependent on input frequency and therefore the following filter designs are recommended for different input frequency ranges as shown in Figure 8-4 and Figure 8-5 (assuming 50 Ω source impedance).

Figure 8-4 Sampling glitch filter for input frequencies from DC to 30 MHz

Figure 8-5 Sampling glitch filter for input frequencies from 30 to 70 MHz

8.3.1.2.2 Analog Input Termination and DC Bias

Depending on the input drive circuitry, a termination network and/or DC biasing needs to be provided.

8.3.1.2.2.1 AC-Coupling

The ADC3660 requires external DC bias using the common mode output voltage (VCM) of the ADC together with the termination network as shown in Figure 8-6. The termination is located within the glitch filter network. When using a balun on the input, the termination impedance has to be adjusted to account for the turns ratio of the transformer. When using an amplifier, the termination impedance can be adjusted to optimize the amplifier performance.

Figure 8-6 AC-Coupling: termination network provides DC bias (glitch filter example for DC - 30 MHz)