• 双通道
• 16 位 65MSPS ADC（最大输出速率 = 31Msps）
• 本底噪声：-159dBFS/Hz
• 超低功耗：65MSPS 时为每通道 71mW
• 16 位，无丢码
• INL：±2LSB；DNL：±0.2LSB
• 基准：外部或内部
• 输入带宽：900MHz (3dB)
• 工业温度范围：-40°C 至 +105°C
• 片上数字下变频器
  • 2 倍、4 倍、8 倍、16 倍、32 倍抽取率
  • 32 位 NCO
• 串行 CMOS 接口
• 1.8V 单电源
• 小尺寸: 40 引脚 WQFN (5mm × 5mm) 封装
• 频谱性能 (f_IN = 5MHz)：
  • SNR：81.9dBFS
  • SFDR：88dBc HD2、HD3
  • SFDR：102dBFS 最严重毛刺

• 数据采集 (DAQ)
• 电机诊断和监控
• 电能质量分析仪
• 电源品质测定器
• 声纳
• 雷达
• 国防无线电
• 无线通信
• 实验室和现场仪表
• 光谱仪

ADC3660 器件是一款低噪声、超低功耗、16 位、65MSPS 双通道高速模数转换器 (ADC)。该器件可实现低功耗，噪声频谱密度为 –159dBFS/Hz，还具有出色的线性度和动态范围。ADC3660 可实现出色的直流精度以及中频采样支持，因此是各种应用的出色选择。该 ADC 在 65MSPS 下的功耗仅为每通道 71mW，功耗随采样率减小而迅速降低。在旁路模式（最高 31MSPS）下，您可以在 1 或 2 个时钟周期后获取输出数据。

ADC3660 使用串行 CMOS (SCMOS) 接口输出数据，可更大限度减少数字互连的次数。该器件提供双通道、单通道和半通道选项。串行 CMOS 接口支持高达 250Mbps 的输出速率，相当于在复杂抽取后大约 15MSPS（双线）到大约 3.75MSPS（0.5 线）的输出速率。因此，ADC3660 可以使用内部抽取滤波器在“过采样和抽取”模式下运行，从而改进动态范围并省去外部抗混叠滤波器。

该器件采用 40 引脚 WQFN 封装（5mm × 5mm），支持 –40 至 +105⁰C 的工业级工作温度范围。

FS = 65MSPS，F_in = 1MHz，16 倍抽取，实时

Typical values at T_A = 25 °C, ADC sampling rate = 65 MSPS, A_IN = –1 dBFS differential input, 50% clock duty cycle, AVDD = IOVDD = 1.8 V, external 1.6 V reference, 5 pF output load, unless otherwise noted.

DECIMATION BYPASS(1)

Figure 6-1 Single Tone FFT at F_IN = 1.1 MHz

DECIMATION BYPASS1

Figure 6-3 Single Tone FFT at F_IN = 10 MHz

AIN = -7 dBFS/tone, DECIMATION BYPASS1

Figure 6-5 Two Tone FFT at F_IN = 3,4 MHz

AIN = -7 dBFS/tone, DECIMATION BYPASS1

Figure 6-7 Two Tone FFT at F_IN = 10,12 MHz

Decimation by 32, complex. NCO = 10.1 MHz

Figure 6-9 Single Tone FFT at F_IN = 10 MHz

DECIMATION BYPASS1

Figure 6-11 ENOB vs Input Frequency

FIN = 5 MHz, DECIMATION BYPASS1

Figure 6-13 AC Performance vs Sampling Rate

FIN = 5 MHz, DECIMATION BYPASS1

Figure 6-15 AC Performance vs Clock Duty cycle

FIN = 5 MHz, DECIMATION BYPASS1

Figure 6-17 ENOB vs AVDD

DECIMATION BYPASS1

Figure 6-19 DC Offset Histogramm

FIN = 5 MHz, DECIMATION BYPASS1

Figure 6-21 DNL vs Code

FS = 25 MSPS, AIN = –20 dBFS, DECIMATION BYPASS1

Figure 6-23 Single Tone FFT at F_IN = 1.1 MHz

FS = 25 MSPS, Decimation by 8, real

Figure 6-25 Single Tone FFT at F_IN = 1 MHz

FS = 25 MSPS, DECIMATION BYPASS1

Figure 6-27 ENOB vs Input Frequency

FS = 25 MSPS, FIN = 5 MHz, DECIMATION BYPASS1

Figure 6-29 AC Performance vs Clock Amplitude

FS = 25 MSPS, FIN = 5 MHz, DECIMATION BYPASS1

Figure 6-31 AC Performance vs V_CM vs Temperature

FS = 25 MSPS, FIN = 5 MHz, DECIMATION BYPASS1

Figure 6-33 DNL vs Code

FIN = 5 MHz, 50 mVpp signal on AVDD

Figure 6-35 PSRR vs Frequency

FIN = 1 MHz, 16-bit resolution, 2-w

Figure 6-37 I_IOVDD Current vs Decimation

AIN = –20 dBFS, DECIMATION BYPASS1

Figure 6-2 Single Tone FFT at F_IN = 1.1 MHz

DECIMATION BYPASS1

Figure 6-4 Single Tone FFT at F_IN = 40 MHz

AIN = -20 dBFS/tone, DECIMATION BYPASS1

Figure 6-6 Two Tone FFT at F_IN = 3,4 MHz

Decimation by 16, real

Figure 6-8 Single Tone FFT at F_IN = 1 MHz

DECIMATION BYPASS1

Figure 6-10 AC Performance vs Input Frequency

FIN = 5 MHz, DECIMATION BYPASS1

Figure 6-12 AC Performance vs Input Amplitude

DECIMATION BYPASS1

Figure 6-14 AC Performance vs Clock Amplitude

FIN = 5 MHz, DECIMATION BYPASS1

Figure 6-16 AC Performance vs AVDD

FIN = 5 MHz, DECIMATION BYPASS1

Figure 6-18 AC Performance vs VCM vs Temperature

FIN = 5 MHz, DECIMATION BYPASS1

Figure 6-20 INL vs Code

FS = 25 MSPS, DECIMATION BYPASS1

Figure 6-22 Single Tone FFT at F_IN = 1.1 MHz

FS = 25 MSPS, DECIMATION BYPASS1

Figure 6-24 Single Tone FFT at F_IN = 10 MHz

FS = 25 MSPS, DECIMATION BYPASS1

Figure 6-26 AC Performance vs Input Frequency

FS = 25 MSPS, FIN = 5 MHz, DECIMATION BYPASS1

Figure 6-28 AC Performance vs Input Amplitude

FS = 25 MSPS, FIN = 5 MHz, DECIMATION BYPASS1

Figure 6-30 AC Performance vs AVDD

FS = 25 MSPS, FIN = 5 MHz, DECIMATION BYPASS1

Figure 6-32 INL vs Code

Aggressor at -1 dBFS

Figure 6-34 Isolation vs Input Frequency

FIN = 1 MHz, 32x complex decimation, 16-bit resolution

Figure 6-36 Current vs Sampling Rate

FIN = 1 MHz, 32x complex decimation, 16-bit resolution, 2-w

Figure 6-38 I_IOVDD Current vs Load Capacitance

The ADC3660 is a low noise, ultra-low power 16-bit high-speed dual channel ADC family supporting sampling rates up to 65Msps. It offers excellent DC precision together with IF sampling support which makes it ideally suited for a wide range of applications. The ADC3660 is equipped with an internal reference option but it also supports the use of an external, high precision 1.6V voltage reference or an external 1.2V reference which is buffered and gained up internally.

An optional programmable digital down converter enables external anti-alias filter relaxation as well as output data rate reduction. The digital filter provides a 32-bit programmable NCO and supports both real or complex decimation.

The ADC3660 includes a digital output formatter which supports output resolutions from 14 to 20-bit.

The device features and control options can be set up either through pin configurations or via SPI register writes.

The analog inputs of ADC3660 are intended to be driven differentially. Both AC coupling and DC coupling of the analog inputs is supported. The analog inputs are designed for an input common mode voltage of 0.95 V which must be provided externally on each input pin. DC-coupled input signals must have a common mode voltage that meets the device input common mode voltage range.

The equivalent input network diagram is shown in Figure 8-1. All four sampling switches, on-resistance shown in red, are in same position (open or closed) simultaneously.

Figure 8-1 Equivalent Input Network

Figure 8-2 shows the analog full power input bandwidth of the ADC3660 with a 50 Ω differential termination. The -3 dB bandwidth is approximately 900 MHz and the useful input bandwidth with good AC performance is approximately 120 MHz.

The equivalent differential input resistance R_IN and input capacitance C_IN vs frequency are shown in Figure 8-3.

Figure 8-2 ADC Analog Input Bandwidth Response

Figure 8-3 Equivant R_IN, C_IN vs Input Frequency

The ADC3660 is an unbuffered ADC and thus a passive kick-back filter is recommended to absorb the glitch from the sampling operation. Depending on if the input is driven by a balun or a differential amplifier with low output impedance, a termination network may be needed. Additionally a passive DC bias circuit is needed in AC-coupled applications which can be combined with the termination network.

The front end sampling glitch filter is designed to optimize the SNR and HD3 performance of the ADC. The filter performance is dependent on input frequency and therefore the following filter designs are recommended for different input frequency ranges as shown in Figure 8-4 and Figure 8-5 (assuming 50 Ω source impedance).

Figure 8-4 Sampling glitch filter for input frequencies from DC to 30 MHz

Figure 8-5 Sampling glitch filter for input frequencies from 30 to 70 MHz

Depending on the input drive circuitry, a termination network and/or DC biasing needs to be provided.

The ADC3660 requires external DC bias using the common mode output voltage (VCM) of the ADC together with the termination network as shown in Figure 8-6. The termination is located within the glitch filter network. When using a balun on the input, the termination impedance has to be adjusted to account for the turns ratio of the transformer. When using an amplifier, the termination impedance can be adjusted to optimize the amplifier performance.

Figure 8-6 AC-Coupling: termination network provides DC bias (glitch filter example for DC - 30 MHz)

In DC coupled applications the DC bias needs to be provided from the fully differential amplifier (FDA) using VCM output of the ADC as shown in Figure 8-7. The glitch filter in this case is located between the anti-alias filter and the ADC. No termination may be needed if amplifier is located close to the ADC or if the termination is part of the anti-alias filter.

Figure 8-7 DC-Coupling: DC bias provided by FDA (glitch filter example for DC - 30 MHz)

The ADC3660 includes an internal auto-zero front end amplifier circuit which improves the 1/f flicker noise. This auto-zero feature can be enabled using SPI register writes (register 0x11, D0).

Figure 8-8 FFT at 25 MSPS with input frequency of 5 MHz (auto-zero feature enable vs disable, 4M point FFT)

Figure 8-10 FFT at 65 MSPS with input frequency of 5 MHz (auto-zero feature enable vs disable, 4M point FFT)

Figure 8-9 FFT at 25 MSPS with input frequency of 5 MHz (auto-zero feature enable vs disable, 4M point FFT)

Figure 8-11 FFT at 65 MSPS with input frequency of 5 MHz (auto-zero feature enabled vs disabled, 4M point FFT)

In order to maximize the ADC SNR performance, the external sampling clock should be low jitter and differential signaling with a high slew rate. This is especially important in IF sampling applications. For less jitter sensitive applications, the ADC3660 provides the option to operate with single ended signaling which saves additional power consumption.

The ADC3660 can be operated using a differential or a single ended clock input where the single ended clock consumes less power consumption. However clock amplitude impacts the ADC aperture jitter and consequently the SNR. For maximum SNR performance, a large clock signal with fast slew rates needs to be provided.

• Differential Clock Input: The clock input can be AC coupled externally. The ADC3660 provides internal biasing for that use case.
• ingle Ended Clock Input: This mode needs to be configured using SPI register (0x0E, D2 and D0) or with the REFBUF pin. In this mode there is no internal clock biasing and thus the clock input needs to be DC coupled around a 0.9V center. The unused input needs to be AC coupled to ground.

Figure 8-12 External and internal connection using differential (left) and single ended (right) clock input

The ADC3660 includes a register (DLL PDN (0x11, D2) which increases the signal acquisition time window for clock rates below 40 MSPS from 25% to 50% of the clock period. Increasing the sampling time provides a longer time for the driving amplifier to settle out the signal which can improve the SNR performance of the system. When powering down the DLL, the acquisition time will track the clock duty cycle (50% is recommended).

T_S: Sampling clock period

The ADC3660 provides three different options for supplying the voltage reference to the ADC. An external 1.6V reference can be directly connected to the VREF input; a voltage 1.2V reference can be connected to the REFBUF input using the internal gain buffer or the internal 1.2V reference can be enabled to generate a 1.6V reference voltage. For best performance, the reference noise should be filtered by connecting a 10 uF and a 0.1 uF ceramic bypass capacitor to the VREF pin. The internal reference circuitry of the ADC3660 is shown in Figure 8-13.

Figure 8-13 Different voltage reference options for ADC3660

The 1.6V reference for the ADC can be generated internal using the on-chip 1.2V bandgap reference along with the internal gain buffer. A 10 uF and a 0.1 uF ceramic bypass capacitor (C_VREF) should be connected between the VREF and REFGND pins as close to the pins as possible.

For highest accuracy and lowest temperature drift, the VREF input can be directly connected to an external 1.6V reference. A 10 uF and a 0.1 uF ceramic bypass capacitor (C_VREF) should connected between the VREF and REFGND pins and placed as close to the pins as possible is recommended. The load current from the external reference is about 1mA.
Note: The internal reference is also used for other functions inside the device, therefore the reference amplifier should only be powered down in power down state but not during normal operation.