DATA SHEET
LM73100 具有输入反极性保护和过压保护功能的 2.7V 至 23V、5.5A 集成式理想二极管
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1 特性
- 宽工作输入电压范围：2.7V 至 23V
- 绝对最大值为 28V
- 可耐受高达 -15 V 的负电压
- 具有低导通电阻的集成式背对背 FET：RON = 28.4mΩ（典型值）
- 具有真反向电流阻断功能的理想二极管运行状态
- 快速过压保护
-
响应时间为 1.2μs（典型值）
- 可调节过压锁定 (OVLO)
-
- 稳态期间针对瞬态过流实现快速跳变响应
- 响应时间为 500ns（典型值）
- 故障后锁存
- 模拟负载电流监测器输出 (IMON)
- 电流范围：0.5A 至 5.5A
- 精度：±15%（最大值）(IOUT ≥ 1A)
- 具有可调节欠压锁定阈值 (UVLO) 的高电平有效使能输入
- 可调节的输出压摆率控制 (dVdt)
- 过温保护
- 具有可调节阈值 (PGTH) 的电源正常状态指示 (PG)
- 小尺寸：QFN 2mm x 2mm，0.45mm 间距
2 应用
电源多路复用器/ORing
适配器输入保护
机顶盒/智能扬声器
USB PD 端口保护
PC/笔记本电脑/显示器/扩展坞
电动工具/充电器
POS 终端
3 说明
LM73100 是一款采用小型封装的高度集成电路保护和电源管理解决方案。该器件使用很少的外部元件即可提供多种保护模式，能够非常有效地抵御电压浪涌、反极性、反向电流和过多浪涌电流。
借助集成的背对背 FET 和始终阻断从输出到输入的反向电流等特性，该器件非常适合电源多路复用器/ORing 应用。该器件采用基于线性 ORing 的方案，可确保实现几乎为零的直流反向电流，并以超小的正向压降和功率耗散来模拟理想的二极管行为。
浪涌电流有特别要求的应用可以通过单个外部电容器设定输出转换率。通过在输入超过可调过压阈值时切断输出，可以保护负载免受输入过压情况的影响。该器件还可在稳态期间对瞬态过流事件提供快速跳变响应。
该器件可在模拟电流监测引脚上精确检测输出负载电流。
该器件可采用 2mm x 2mm 10 引脚 HotRod QFN 封装，旨在改善热性能并减小系统尺寸。
器件的额定工作结温范围为 –40°C 至 +125°C。
器件信息
| 器件型号 | 封装(1) | 封装尺寸（标称值） |
|---|---|---|
| LM73100RPW | QFN (10) | 2mm x 2mm |
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
简化版原理图4 Revision History
Changes from Revision * (October 2020) to Revision A (December 2020)
- 将状态从“预告信息”更改为“量产数据”Go
5 Pin Configuration and Functions
Figure 5-1 LM73100 RPW Package 10-Pin QFN Top
ViewTable 5-1 Pin Functions
| PIN | TYPE | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| EN/UVLO |
1 | Analog Input | Active High Enable for the device. A Resistor Divider on this pin from input supply to GND can be used to adjust the Undervoltage Lockout threshold. Do not leave floating. Refer to Section 7.3.2 for more details. |
|
OVLO |
2 | Analog Input | A Resistor Divider on this pin from supply to GND can be used to adjust the Overvoltage Lockout threshold. This pin can also be used as an Active Low Enable for the device. Do not leave floating. Refer to Section 7.3.3 for more details. |
|
PG |
3 | Digital Output | Power Good indication. This is an Open Drain signal which is asserted High when the internal powerpath is fully turned ON and PGTH input exceeds a certain threshold. Refer to Section 7.3.9 for more details. |
|
PGTH |
4 | Analog Input | Power Good Threshold. Refer to Section 7.3.9 for more details. |
|
IN |
5 |
Power | Power Input. |
|
OUT |
6 |
Power | Power Output. |
|
DVDT |
7 | Analog Output | A capacitor from this pin to GND sets the output turn on slew rate. Leave this pin floating for the fastest turn on slew rate. Refer to Section 7.3.4.1 for more details. |
|
GND |
8 |
Ground | This is the ground reference for all internal circuits and must be connected to system GND. |
|
IMON |
9 | Analog Output |
Analog load current monitor. The pin voltage can be used to monitor the output load current. An external resistor from this pin to ground sets the current monitor gain. Recommended to connect external clamp to limit the voltage below abs max rating in case of large current spikes. Connect to ground if not used. Do not leave floating. Refer to Section 7.3.5 for more details. |
|
DNC |
10 |
X |
Internal test pin. Do not connect anything on this pin. |
6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
| Parameter | Pin | MIN | MAX | UNIT | |
|---|---|---|---|---|---|
| VIN | Maximum Input Voltage Range, –40 ℃ ≤ TJ ≤ 125 ℃ | IN | max (–15, VOUT - 21) | 28 | V |
| Maximum Input Voltage Range, –10 ℃ ≤ TJ ≤ 125 ℃ | max (–15, VOUT - 22) | 28 | V | ||
| VOUT | Maximum Output Voltage Range, –40 ℃ ≤ TJ ≤ 125 ℃ | OUT | –0.3 | min (28, VIN + 21) | |
| Maximum Output Voltage Range, –10 ℃ ≤ TJ ≤ 125 ℃ | –0.3 | min (28, VIN + 22) | |||
| VOUT,PLS | Minimum Output Voltage Pulse (< 1 µs) | OUT | –0.8 | ||
| VEN/UVLO | Maximum Enable Pin Voltage Range (2) | EN/UVLO | –0.3 | 6.5 | V |
| VOVLO | Maximum OVLO Pin Voltage Range (2) | OVLO | –0.3 | 6.5 | V |
| VdVdT | Maximum dVdT Pin Voltage Range | dVdt | Internally Limited | V | |
| VPGTH | Maximum PGTH Pin Voltage Range (2) | PGTH | –0.3 | 6.5 | V |
| VPG | Maximum PG Pin Voltage Range | PG | –0.3 | 6.5 | V |
| VIMON | Maximum IMON Pin Voltage Range | IMON | 1.8 | V | |
| IMAX | Maximum Continuous Switch Current | IN to OUT | 5.5 | A | |
| TJ | Junction temperature | Internally Limited | °C | ||
| TLEAD | Maximum Lead Temperature | 300 | °C | ||
| TSTG | Storage temperature | –65 | 150 | °C | |
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If this pin has a pull-up up to VIN, it is recommended to use a resistance of 350 kΩ or higher to limit the current under conditions where IN can be exposed to reverse polarity.
6.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
| Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
| Parameter | Pin | MIN | MAX | UNIT | |
|---|---|---|---|---|---|
| VIN | Input Voltage Range | IN | 2.7 | 23 | V |
| VOUT | Output Voltage Range | OUT | min (23, VIN + 20) | V | |
| VEN/UVLO | Enable Pin Voltage Range | EN/UVLO | 5 (2) | V | |
| VOVLO | OVLO Pin Voltage Range | OVLO | 0.5 | 1.5 | V |
| VdVdT | dVdT Capacitor Voltage Rating | dVdt | VIN + 5 V (1) | V | |
| VPGTH | PGTH Pin Voltage Range | PGTH | 5 (3) | V | |
| VPG | PG Pin Voltage Range | PG | 5 (3) | V | |
| VIMON | IMON Pin Voltage | IMON | 1.5 | V | |
| IMAX | Continuous Switch Current, , TJ ≤ 125 ℃ | IN to OUT | 5.5 | A | |
| TJ | Junction temperature | –40 | 125 | °C | |
(1) In a PowerMUX/ORing scenario with unequal supplies, the dVdt capacitor rating for each device should be chosen based on the highest of the 2 rails.
(2) For supply voltages below 5V, it is okay to pull up the EN pin to IN directly. For supply voltages greater than 5V or systems which can be exposed to reverse polarity on input supply, it is recommended to use a pull-up resistor with a minimum value of 350 kΩ.
(3) For systems which can be exposed to reverse polarity on input supply, if this pin is referred to input supply, it is recommended to use a pull-up resistor with a minimum value of 350 kΩ to limit the current through the pin.
6.4 Thermal Information
| THERMAL METRIC (1) | LM73100 | UNIT | |
|---|---|---|---|
| RPW (QFN) | |||
| 10 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 41.7 (2) | °C/W |
| 74.5 (3) | °C/W | ||
| ΨJT | Junction-to-top characterization parameter | 1 | °C/W |
| ΨJB | Junction-to-board characterization parameter | 20 (2) | °C/W |
| 27.6 (3) | °C/W | ||
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) Based on simulations conducted with the device mounted on a custom 4-layer PCB (2s2p) with 8 thermal vias under device
(3) Based on simulations conducted with the device mounted on a JEDEC 4-layer PCB (2s2p) with no thermal vias under device
6.5 Electrical Characteristics
(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V, VEN/UVLO = 2 V, VOVLO = 0 V, dVdT = Open, RIMON = 549 Ω, PGTH = Open, PG = Open, OUT = Open. All voltages referenced to GND.
| Test Parameter | Description | MIN | TYP | MAX | UNITS |
|---|---|---|---|---|---|
| INPUT SUPPLY (IN) | |||||
| VUVP(R) | IN supply UVP rising threshold | 2.44 | 2.53 | 2.64 | V |
| VUVP(F) | IN supply UVP falling threshold | 2.35 | 2.42 | 2.55 | V |
| IQ(ON) | IN supply quiescent current, VIN = 2.7 V | 347 | 492 | µA | |
| IN supply quiescent current, VIN = 12 V | 426 | 509 | µA | ||
| IN supply quiescent current, VIN = 23 V | 459 | 612 | µA | ||
| IQ(RCB) | IN supply quiescent current during RCB, VOUT > VIN | 189.7 | 234 | µA | |
| IQ(OFF) | IN supply disabled state current (VSD(F) < VEN < VUVLO(R)) | 74.5 | 97.6 | µA | |
| ISD | IN supply shutdown current (VEN < VSD(F)) | 4.6 | 8.2 | µA | |
| IQ(OVLO) | IN supply OFF state current (OVLO condition), VOUT > VIN | 191 | µA | ||
| IINLKG(IRPP) | IN supply leakage current (VIN = –14 V, VOUT = 0 V) | -3.5 | µA | ||
| ON RESISTANCE (IN - OUT) | |||||
| RON | VIN = 12 V, IOUT = 3 A, TJ = 25 ℃ | 28.4 | mΩ | ||
| 2.7 ≤ VIN ≤ 23 V, –40 ℃ ≤ TJ ≤ 125 ℃ | 44.85 | mΩ | |||
| ENABLE/UNDERVOLTAGE LOCKOUT (EN/UVLO) | |||||
| VUVLO(R) | EN/UVLO rising threshold | 1.183 | 1.2 | 1.223 | V |
| VUVLO(F) | EN/UVLO falling threshold | 1.076 | 1.09 | 1.116 | V |
| VSD(F) | EN/UVLO falling threshold for lowest shutdown current | 0.45 | 0.74 | V | |
| IENLKG | EN/UVLO leakage current | –0.1 | 0.1 | µA | |
| OVERVOLTAGE LOCKOUT (OVLO) | |||||
| VOV(R) | OVLO rising threshold | 1.183 | 1.2 | 1.223 | V |
| VOV(F) | OVLO falling threshold | 1.076 | 1.09 | 1.116 | V |
| IOVLKG | OVLO pin leakage current, 0.5 V < VOVLO < 1.5 V | –0.1 | 0.1 | µA | |
| IOUTLKG(OVLO) | OUT leakage current (OVLO condition), VOUT > VIN | 317 | µA | ||
| FIXED FAST-TRIP (OUT) | |||||
| IFT | Fixed fast-trip current threshold | 21.9 | A | ||
| OUTPUT LOAD CURRENT MONITOR (IMON) | |||||
| GIMON | Analog load current monitor gain (IMON : IOUT), IOUT = 0.5 A to 1 A | 144 | 181 | 216 | µA/A |
| Analog load current monitor gain (IMON : IOUT), IOUT = 1 A to 5.5 A | 153 | 181 | 207 | µA/A | |
| REVERSE CURRENT BLOCKING (IN - OUT) | |||||
| VFWD | (VIN - VOUT) forward regulation voltage, IOUT = 10 mA | 4.8 | 16.4 | 28.4 | mV |
| VREVTH | (VOUT - VIN) threshold for fast BFET turn off (enter reverse current blocking) | 22.7 | 29.3 | 36.5 | mV |
| VFWDTH | (VIN - VOUT) threshold for fast BFET turn on (exit reverse current blocking) | 85.9 | 105.8 | 125 | mV |
| IREVLKG(OFF) | Reverse leakage current (unpowered condition), VOUT = 12 V, VIN = 0 V | 4.8 | µA | ||
| IREVLKG | Reverse leakage current, (VOUT - VIN) = 21.5 V | 10.10 | 15.86 | µA | |
| IOUTLKG(RCB) | OUT leakage current during RCB state while ON, (VOUT - VIN) = 1 V | 247.6 | 322 | µA | |
| POWER GOOD INDICATION (PG) | |||||
| VPGD | PG pin low voltage while de-asserted, VIN < VUVP(F), VEN < VSD, IPG = 26 µA | 0.67 | 0.9 | V | |
| PG pin low voltage while de-asserted, VIN < VUVP(F), VEN < VSD, IPG = 242 µA | 0.78 | 1 | V | ||
| PG pin low voltage while de-asserted, VIN > VUVP(R) | 0.6 | V | |||
| IPGLKG | PG pin leakage current while asserted | 0.5 | 2 | µA | |
| POWERGOOD THRESHOLD (PGTH) | |||||
| VPGTH(R) | PGTH rising threshold | 1.183 | 1.2 | 1.223 | V |
| VPGTH(F) | PGTH falling threshold | 1.076 | 1.09 | 1.116 | V |
| IPGTHLKG | PGTH leakage current | –1 | 1 | µA | |
| OVERTEMPERATURE PROTECTION (OTP) | |||||
| TSD | Thermal shutdown rising threshold, TJ↑ | 154 | °C | ||
| TSDHYS | Thermal shutdown hysteresis, TJ↓ | 10 | °C | ||
| DVDT | |||||
| IdVdt | dVdt pin charging current | 1.15 | 2.34 | 3.66 | µA |
