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  • LM73100 具有输入反极性保护和过压保护功能的 2.7V 至 23V、5.5A 集成式理想二极管

    • ZHCSLY9A October   2020  – December 2020 LM7310

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  • LM73100 具有输入反极性保护和过压保护功能的 2.7V 至 23V、5.5A 集成式理想二极管
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Switching Characteristics
    8.     14
    9. 6.8 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Input Reverse Polarity Protection
      2. 7.3.2 Undervoltage Protection (UVLO & UVP)
      3. 7.3.3 Overvoltage Lockout (OVLO)
      4. 7.3.4 Inrush Current control and Fast-trip
        1. 7.3.4.1 Slew Rate (dVdt) and Inrush Current Control
        2. 7.3.4.2 Fast-Trip During Steady State
      5. 7.3.5 Analog Load Current Monitor Output
      6. 7.3.6 Reverse Current Protection
      7. 7.3.7 Overtemperature Protection (OTP)
      8. 7.3.8 Fault Response
      9. 7.3.9 Power Good Indication (PG)
    4. 7.4 Device Functional Modes
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Single Device, Self-Controlled
      1. 8.2.1 Typical Application
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Setting Undervoltage and Overvoltage Thresholds
          2. 8.2.1.2.2 Setting Output Voltage Rise Time (tR)
          3. 8.2.1.2.3 Setting Power Good Assertion Threshold
          4. 8.2.1.2.4 Setting Analog Current Monitor Voltage (IMON) Range
        3. 8.2.1.3 Application Curves
    3. 8.3 Active ORing
    4. 8.4 Priority Power MUXing
    5. 8.5 USB PD Port Protection
    6. 8.6 Parallel Operation
  9. 9 Power Supply Recommendations
    1. 9.1 Transient Protection
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12Mechanical, Packaging, and Orderable Information
  13. 重要声明
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LM73100 具有输入反极性保护和过压保护功能的 2.7V 至 23V、5.5A 集成式理想二极管

本资源的原文使用英文撰写。 为方便起见,TI 提供了译文;由于翻译过程中可能使用了自动化工具,TI 不保证译文的准确性。 为确认准确性,请务必访问 ti.com 参考最新的英文版本(控制文档)。

1 特性

  • 宽工作输入电压范围:2.7V 至 23V
    • 绝对最大值为 28V
    • 可耐受高达 -15 V 的负电压
  • 具有低导通电阻的集成式背对背 FET:RON = 28.4mΩ(典型值)
  • 具有真反向电流阻断功能的理想二极管运行状态
  • 快速过压保护
    • 响应时间为 1.2μs(典型值)

    • 可调节过压锁定 (OVLO)
  • 稳态期间针对瞬态过流实现快速跳变响应
    • 响应时间为 500ns(典型值)
    • 故障后锁存
  • 模拟负载电流监测器输出 (IMON)
    • 电流范围:0.5A 至 5.5A
    • 精度:±15%(最大值)(IOUT ≥ 1A)
  • 具有可调节欠压锁定阈值 (UVLO) 的高电平有效使能输入
  • 可调节的输出压摆率控制 (dVdt)
  • 过温保护
  • 具有可调节阈值 (PGTH) 的电源正常状态指示 (PG)
  • 小尺寸:QFN 2mm x 2mm,0.45mm 间距

2 应用

  • 电源多路复用器/ORing

  • 适配器输入保护

  • 机顶盒/智能扬声器

  • USB PD 端口保护

  • PC/笔记本电脑/显示器/扩展坞

  • 电动工具/充电器

  • POS 终端

3 说明

LM73100 是一款采用小型封装的高度集成电路保护和电源管理解决方案。该器件使用很少的外部元件即可提供多种保护模式,能够非常有效地抵御电压浪涌、反极性、反向电流和过多浪涌电流。

借助集成的背对背 FET 和始终阻断从输出到输入的反向电流等特性,该器件非常适合电源多路复用器/ORing 应用。该器件采用基于线性 ORing 的方案,可确保实现几乎为零的直流反向电流,并以超小的正向压降和功率耗散来模拟理想的二极管行为。

浪涌电流有特别要求的应用可以通过单个外部电容器设定输出转换率。通过在输入超过可调过压阈值时切断输出,可以保护负载免受输入过压情况的影响。该器件还可在稳态期间对瞬态过流事件提供快速跳变响应。

该器件可在模拟电流监测引脚上精确检测输出负载电流。

该器件可采用 2mm x 2mm 10 引脚 HotRod QFN 封装,旨在改善热性能并减小系统尺寸。

器件的额定工作结温范围为 –40°C 至 +125°C。

器件信息
器件型号封装(1)封装尺寸(标称值)
LM73100RPWQFN (10)2mm x 2mm
(1) 如需了解所有可用封装,请参阅数据表末尾的可订购产品附录。
GUID-20200919-CA0I-VLW4-G9XT-PCQXG9SXXRZM-low.gif简化版原理图

4 Revision History

Changes from Revision * (October 2020) to Revision A (December 2020)

  • 将状态从“预告信息”更改为“量产数据”Go

5 Pin Configuration and Functions

GUID-20201214-CA0I-GSG4-VWCS-HX4W22XNFCCM-low.gif Figure 5-1 LM73100 RPW Package 10-Pin QFN Top View
Table 5-1 Pin Functions
PINTYPEDESCRIPTION
NAMENO.
EN/UVLO

1

Analog InputActive High Enable for the device. A Resistor Divider on this pin from input supply to GND can be used to adjust the Undervoltage Lockout threshold. Do not leave floating. Refer to Section 7.3.2 for more details.

OVLO

2

Analog InputA Resistor Divider on this pin from supply to GND can be used to adjust the Overvoltage Lockout threshold. This pin can also be used as an Active Low Enable for the device. Do not leave floating. Refer to Section 7.3.3 for more details.

PG

3

Digital OutputPower Good indication. This is an Open Drain signal which is asserted High when the internal powerpath is fully turned ON and PGTH input exceeds a certain threshold. Refer to Section 7.3.9 for more details.

PGTH

4

Analog InputPower Good Threshold. Refer to Section 7.3.9 for more details.

IN

5

Power

Power Input.

OUT

6

Power

Power Output.

DVDT

7

Analog OutputA capacitor from this pin to GND sets the output turn on slew rate. Leave this pin floating for the fastest turn on slew rate. Refer to Section 7.3.4.1 for more details.

GND

8

Ground

This is the ground reference for all internal circuits and must be connected to system GND.

IMON

9

Analog Output

Analog load current monitor. The pin voltage can be used to monitor the output load current. An external resistor from this pin to ground sets the current monitor gain. Recommended to connect external clamp to limit the voltage below abs max rating in case of large current spikes. Connect to ground if not used. Do not leave floating. Refer to Section 7.3.5 for more details.

DNC

10

X

Internal test pin. Do not connect anything on this pin.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
Parameter Pin MIN MAX UNIT
VIN Maximum Input Voltage Range, –40 ℃ ≤ TJ ≤ 125 ℃ IN max (–15, VOUT - 21) 28 V
Maximum Input Voltage Range, –10 ℃ ≤ TJ ≤ 125 ℃ max (–15, VOUT - 22) 28 V
VOUT Maximum Output Voltage Range, –40 ℃ ≤ TJ ≤ 125 ℃ OUT –0.3 min (28, VIN + 21)
Maximum Output Voltage Range, –10 ℃ ≤ TJ ≤ 125 ℃ –0.3 min (28, VIN + 22)
VOUT,PLS Minimum Output Voltage Pulse (< 1 µs) OUT –0.8
VEN/UVLO Maximum Enable Pin Voltage Range (2) EN/UVLO –0.3 6.5 V
VOVLO Maximum OVLO Pin Voltage Range (2) OVLO –0.3 6.5 V
VdVdT Maximum dVdT Pin Voltage Range dVdt Internally Limited V
VPGTH Maximum PGTH Pin Voltage Range (2) PGTH –0.3 6.5 V
VPG Maximum PG Pin Voltage Range PG –0.3 6.5 V
VIMON Maximum IMON Pin Voltage Range IMON 1.8 V
IMAX Maximum Continuous Switch Current IN to OUT 5.5 A
TJ Junction temperature Internally Limited °C
TLEAD Maximum Lead Temperature 300 °C
TSTG Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If this pin has a pull-up up to VIN, it is recommended to use a resistance of 350 kΩ or higher to limit the current under conditions where IN can be exposed to reverse polarity.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) ±500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
Parameter Pin MIN MAX UNIT
VIN Input Voltage Range IN 2.7 23 V
VOUT Output Voltage Range OUT min (23, VIN + 20) V
VEN/UVLO Enable Pin Voltage Range EN/UVLO 5 (2) V
VOVLO OVLO Pin Voltage Range OVLO 0.5 1.5 V
VdVdT dVdT Capacitor Voltage Rating dVdt VIN + 5 V (1) V
VPGTH PGTH Pin Voltage Range PGTH 5 (3) V
VPG PG Pin Voltage Range PG 5 (3) V
VIMON IMON Pin Voltage IMON 1.5 V
IMAX Continuous Switch Current, , TJ ≤ 125 ℃ IN to OUT 5.5 A
TJ Junction temperature –40 125 °C
(1) In a PowerMUX/ORing scenario with unequal supplies, the dVdt capacitor rating for each device should be chosen based on the highest of the 2 rails.
(2) For supply voltages below 5V, it is okay to pull up the EN pin to IN directly. For supply voltages greater than 5V or systems which can be exposed to reverse polarity on input supply, it is recommended to use a pull-up resistor with a minimum value of 350 kΩ.
(3) For systems which can be exposed to reverse polarity on input supply, if this pin is referred to input supply, it is recommended to use a pull-up resistor with a minimum value of 350 kΩ to limit the current through the pin.

6.4 Thermal Information

THERMAL METRIC (1) LM73100 UNIT
RPW (QFN)
10 PINS
RθJA Junction-to-ambient thermal resistance 41.7 (2) °C/W
74.5 (3) °C/W
ΨJT Junction-to-top characterization parameter 1 °C/W
ΨJB Junction-to-board characterization parameter 20 (2) °C/W
27.6 (3) °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) Based on simulations conducted with the device mounted on a custom 4-layer PCB (2s2p) with 8 thermal vias under device
(3) Based on simulations conducted with the device mounted on a JEDEC 4-layer PCB (2s2p) with no thermal vias under device 

6.5 Electrical Characteristics

(Test conditions unless otherwise noted) –40°C ≤ TJ ≤ 125°C, VIN = 12 V, VEN/UVLO = 2 V, VOVLO = 0 V, dVdT = Open, RIMON = 549 Ω, PGTH = Open, PG = Open, OUT = Open. All voltages referenced to GND.
Test Parameter Description MIN TYP MAX UNITS
INPUT SUPPLY (IN)
VUVP(R) IN supply UVP rising threshold 2.44 2.53 2.64 V
VUVP(F) IN supply UVP falling threshold 2.35 2.42 2.55 V
IQ(ON) IN supply quiescent current, VIN = 2.7 V 347 492 µA
IN supply quiescent current, VIN = 12 V 426 509 µA
IN supply quiescent current, VIN = 23 V 459 612 µA
IQ(RCB) IN supply quiescent current during RCB, VOUT > VIN  189.7 234 µA
IQ(OFF) IN supply disabled state current (VSD(F) < VEN < VUVLO(R)) 74.5 97.6 µA
ISD IN supply shutdown current (VEN < VSD(F)) 4.6 8.2 µA
IQ(OVLO) IN supply OFF state current (OVLO condition), VOUT > VIN 191 µA
IINLKG(IRPP) IN supply leakage current (VIN = –14 V, VOUT = 0 V) -3.5 µA
ON RESISTANCE (IN - OUT)
RON VIN = 12 V, IOUT = 3 A, TJ = 25 ℃ 28.4 mΩ
2.7 ≤ VIN ≤ 23 V, –40 ℃ ≤ TJ ≤ 125 ℃ 44.85 mΩ
ENABLE/UNDERVOLTAGE LOCKOUT (EN/UVLO)
VUVLO(R) EN/UVLO rising threshold 1.183 1.2 1.223 V
VUVLO(F) EN/UVLO falling threshold 1.076 1.09 1.116 V
VSD(F) EN/UVLO falling threshold for lowest shutdown current 0.45 0.74 V
IENLKG EN/UVLO leakage current –0.1 0.1 µA
OVERVOLTAGE LOCKOUT (OVLO)
VOV(R) OVLO rising threshold 1.183 1.2 1.223 V
VOV(F) OVLO falling threshold 1.076 1.09 1.116 V
IOVLKG OVLO pin leakage current, 0.5 V < VOVLO  < 1.5 V –0.1 0.1 µA
IOUTLKG(OVLO) OUT leakage current (OVLO condition), VOUT > VIN 317 µA
FIXED FAST-TRIP (OUT)
IFT Fixed fast-trip current threshold 21.9 A
OUTPUT LOAD CURRENT MONITOR (IMON)
GIMON Analog load current monitor gain (IMON : IOUT), IOUT = 0.5 A to 1 A 144 181 216 µA/A
Analog load current monitor gain (IMON : IOUT), IOUT = 1 A to 5.5 A 153 181 207 µA/A
REVERSE CURRENT BLOCKING (IN - OUT)
VFWD (VIN - VOUT) forward regulation voltage, IOUT = 10 mA 4.8 16.4 28.4 mV
VREVTH (VOUT - VIN) threshold for fast BFET turn off (enter reverse current blocking) 22.7 29.3 36.5 mV
VFWDTH (VIN - VOUT) threshold for fast BFET turn on (exit reverse current blocking) 85.9 105.8 125 mV
IREVLKG(OFF) Reverse leakage current (unpowered condition), VOUT = 12 V, VIN = 0 V 4.8 µA
IREVLKG Reverse leakage current, (VOUT - VIN) = 21.5 V 10.10 15.86 µA
IOUTLKG(RCB) OUT leakage current during RCB state while ON, (VOUT - VIN) = 1 V 247.6 322 µA
POWER GOOD INDICATION (PG)
VPGD PG pin low voltage while de-asserted, VIN < VUVP(F), VEN < VSD, IPG = 26 µA 0.67 0.9 V
PG pin low voltage while de-asserted, VIN < VUVP(F), VEN < VSD, IPG = 242 µA 0.78 1 V
PG pin low voltage while de-asserted, VIN > VUVP(R) 0.6 V
IPGLKG PG pin leakage current while asserted 0.5 2 µA
POWERGOOD THRESHOLD (PGTH)
VPGTH(R) PGTH rising threshold 1.183 1.2 1.223 V
VPGTH(F) PGTH falling threshold 1.076 1.09 1.116 V
IPGTHLKG PGTH leakage current –1 1 µA
OVERTEMPERATURE PROTECTION (OTP)
TSD Thermal shutdown rising threshold, TJ↑ 154 °C
TSDHYS Thermal shutdown hysteresis, TJ↓ 10 °C
DVDT
IdVdt dVdt pin charging current 1.15 2.34 3.66 µA

6.6 Timing Requirements

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
tOVLO Overvoltage lock-out response time VOVLO > VOV(R) to VOUT↓ 1.1 µs
tFT Fixed fast-trip response time IOUT > IFT to IOUT↓ 500 ns
tSWRCB Reverse Current Blocking recovery time (VIN - VOUT) > VFWDTH to VOUT ↑ 50 µs
tRCB Reverse Current Blocking fast comparator response time (VOUT - VIN) > 1.3 x VREVTH to BFET OFF 1 µs
tPGA PG Assertion de-glitch 12 µs
tPGD PG De-assertion de-glitch 12 µs

6.7 Switching Characteristics

The output rising slew rate is internally controlled and constant across the entire operating voltage range to ensure the turn on timing is not affected by the load conditions. The rising slew rate can be adjusted by adding capacitance from the dVdt pin to ground. As CdVdt is increased it will slow the rising slew rate (SR). See Slew Rate and Inrush Current Control (dVdt) section for more details. The Turn-Off Delay and Fall Time, however, are dependent on the RC time constant of the load capacitance (COUT) and Load Resistance (RL). The Switching Characteristics are only valid for the power-up sequence where the supply is available in steady state condition and the load voltage is completely discharged before the device is enabled.Typical Values are taken at TJ = 25°C unless specifically noted otherwise. RL = 100 Ω, COUT = 1 µF 
PARAMETER VIN
CdVdt = Open CdVdt = 1800 pF CdVdt = 3300 pF UNIT
SRON Output Rising slew rate 2.7 V 12.14 0.87 0.5 V/ms
12 V 28.1 1.09 0.61
23 V 44.78 1.25 0.71
tD,ON Turn on delay 2.7 V 0.09 0.6 0.97 ms
12 V 0.1 1.32 2.35
23 V 0.11 1.99 3.69
tR Rise time 2.7 V 0.17 2.51 4.33 ms
12 V 0.35 8.1 15.37
23 V 0.40 14.4 25.89
tON Turn on time 2.7 V 0.27 3.11 5.31 ms
12 V 0.45 10.08 17.72
23 V 0.50 16.41 29.57
tD,OFF Turn off delay 2.7 V 64.44 64.44 64.44 µs
12 V 25.32 25.32 25.32
23 V 23.02 23.02 23.02

GUID-0B135905-F335-4B69-A9D1-B6DE1C46ACBD-low.gifFigure 6-1 LM73100 Switching Times

6.8 Typical Characteristics

GUID-20201207-CA0I-Q0HG-H8Z7-ZKBCTW524QLR-low.gifFigure 6-2 ON-Resistance vs Supply Voltage
Figure 6-4 IN Quiescent Current vs Supply Voltage
Figure 6-6 IN Undervoltage Threshold vs Temperature
GUID-20201207-CA0I-LV2L-B8DW-6G3LQJGG52B5-low.gifFigure 6-8 EN/UVLO Shutdown Threshold vs Temperature
GUID-20201207-CA0I-HGCM-CCQW-RGLSVRTG3MVZ-low.gifFigure 6-10 OVLO Threshold vs Temperature
Figure 6-12 Reverse Comparator Threshold vs Temperature
Figure 6-14 Forward Regulation Voltage vs Supply Voltage
GUID-20201207-CA0I-1XZR-5QKW-F71HV1XM1VKK-low.gifFigure 6-16 OUT Leakage Current During ON-State Reverse Current Blocking
GUID-20201209-CA0I-HCKN-J9BD-TH5DLV4FPB0T-low.gifFigure 6-18 Analog Current Monitor Gain Accuracy
Figure 6-20 Analog Current Monitor Gain vs Load Current
GUID-20201207-CA0I-DRGC-3BWG-SHGZ8J3RPPXS-low.gifFigure 6-22 Steady State Fast-Trip Comparator Threshold vs Temperature
Figure 6-24 Time to Thermal Shut-Down During Inrush State
GUID-20201207-CA0I-PTPQ-0PNJ-M99CBGCMJL12-low.png
VEN/UVLO = 3 V, COUT = 220 μF, CdVdt = 10 nF, VIN ramped up to 12 V
Figure 6-26 Start Up with IN Supply
GUID-20201207-CA0I-SJGJ-3QCV-VNQCWF3TMX6Z-low.png
COUT = 220 μF, CdVdt = 10 nF, EN/UVLO connected to IN through resistor ladder, 12 V hot-plugged to IN
Figure 6-28 Input Hot-Plug
GUID-20201208-CA0I-M1KD-2MF0-FVWTRXH9DHQH-low.png
COUT = 220 μF, PG pulled up to 3 V, -15 V hot-plugged to IN
Figure 6-30 Input Reverse Polarity Protection - Fast Ramp
GUID-20201207-CA0I-2CQ9-F7F8-NJMFC6KBZXHG-low.png
IN= Open, COUT = 220 μF, PG pulled up to 3 V, 20 V hot-plugged to OUT
Figure 6-32 Reverse Current Blocking Response in OFF State
GUID-20201207-CA0I-RZMX-36KR-G1JMBNPJMJSZ-low.png
COUT = 220 μF, ROUT = 20 Ω, OVLO threshold = 13.2 V, VIN ramped up from 12 V to 16 V
Figure 6-34 Input Overvoltage Protection
GUID-20201207-CA0I-43WX-H4QK-CBV9HNXNKBPV-low.png
VIN = 12 V, COUT = Open, OUT stepped from Open → Short-circuit to GND
Figure 6-36 Fast-Trip Response During Steady State - Zoomed In
Figure 6-3 Forward Voltage Drop vs Load Current
Figure 6-5 IN Quiescent Current vs Temperature
Figure 6-7 EN/UVLO Threshold vs Temperature
GUID-20201207-CA0I-2VLK-4G7X-FPPDHTVJGH3X-low.gifFigure 6-9 EN/UVLO Shutdown Threshold vs Supply Voltage
GUID-20201207-CA0I-HXTC-XBPK-CCZ8LWR7BDZS-low.gifFigure 6-11 PGTH Threshold vs Temperature
GUID-20201207-CA0I-VJ6Z-F1LS-JPGK4P68LQ51-low.gifFigure 6-13 Forward Regulation Voltage vs Temperature
Figure 6-15 Forward Comparator Threshold vs Temperature
Figure 6-17 Reverse Leakage Current During OFF-State
Figure 6-19 Analog Current Monitor gain vs Temperature
GUID-20201207-CA0I-Z3J7-FHZC-FGQN2XHQLRC7-low.gifFigure 6-21 DVDT Charging Current vs Temperature
Figure 6-23 Steady State Fast-Trip Current Threshold vs Temperature
Figure 6-25 Time to thermal Shut-Down During Steady State
GUID-20201207-CA0I-ZW2M-SJQB-TZ4BBX26HLP0-low.png
VIN = 12 V, COUT = 220 μF, CdVdt = 10 nF, VEN/UVLO stepped up to 3 V
Figure 6-27 Start Up with EN
GUID-20201207-CA0I-T0DB-M19D-K8BBH3TV1XF2-low.png
VIN = 12 V, ROUT = 20 Ω, COUT = 220 μF, CdVdt = 10 nF, VEN/UVLO stepped up to 3 V
Figure 6-29 Inrush Current with RC Load
GUID-20201208-CA0I-CPDZ-WH7C-GJV8DVJ0NKLQ-low.png
COUT = 220 μF, PG pulled up to 3 V, VIN ramped down from 0 V to -15 V and then ramped up to 0 V
Figure 6-31 Input Reverse Polarity Protection - Slow Ramp
GUID-20201207-CA0I-BQ4Z-PQM5-H8VNZSJBNC4T-low.png
IN= Open, COUT = 220 μF, PG pulled up to 3 V, VOUT ramped up from 0 V to 20 V
Figure 6-33 Reverse Current Blocking Response in OFF State
GUID-20201207-CA0I-8JBM-J47C-BQGL2G6XLWZC-low.png
VIN = 12 V, COUT = Open, OUT stepped from Open → Short-circuit to GND
Figure 6-35 Fast-Trip Response During Steady State

7 Detailed Description

7.1 Overview

The LM73100 is an integrated ideal diode that is used to ensure safe power delivery in a system. The device starts its operation by monitoring the IN bus. When the input supply voltage (VIN) exceeds the undervoltage protection threshold (VUVP), the device samples the EN/UVLO pin. A high level (> VUVLO(R)) on this pin enables the internal power path (BFET+HFET) to start conducting and allow current to flow from IN to OUT. When EN/UVLO pin is held low (< VUVLO(F)), the internal power path is turned off. In case of reverse voltages appearing at the input, the power path remains OFF thereby protecting the output load.

After a successful start-up sequence, the device now actively monitors its load current and input voltage, and controls the internal HFET to ensure that the fast-trip threshold (IFT) is not exceeded and overvoltage spikes are cut-off once they cross the user adjustable overvoltage lockout threshold (VOVLO). This helps to keep the system safe from harmful levels of voltage and current.

The device has integrated reverse current blocking FET (BFET) which operates like an ideal diode. The BFET is linearly regulated to maintain a small constant forward drop (VFWD) in forward conduction mode and turned off completely to block reverse current from OUT to IN if output voltage exceeds the input voltage.

The device also has a built-in thermal sensor based shutdown mechanism to protect itself in case the device temperature (TJ) exceeds the recommended operating conditions.

 

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