响应时间为 1.2μs(典型值)
电源多路复用器/ORing
适配器输入保护
机顶盒/智能扬声器
USB PD 端口保护
PC/笔记本电脑/显示器/扩展坞
电动工具/充电器
POS 终端
LM73100 是一款采用小型封装的高度集成电路保护和电源管理解决方案。该器件使用很少的外部元件即可提供多种保护模式,能够非常有效地抵御电压浪涌、反极性、反向电流和过多浪涌电流。
借助集成的背对背 FET 和始终阻断从输出到输入的反向电流等特性,该器件非常适合电源多路复用器/ORing 应用。该器件采用基于线性 ORing 的方案,可确保实现几乎为零的直流反向电流,并以超小的正向压降和功率耗散来模拟理想的二极管行为。
浪涌电流有特别要求的应用可以通过单个外部电容器设定输出转换率。通过在输入超过可调过压阈值时切断输出,可以保护负载免受输入过压情况的影响。该器件还可在稳态期间对瞬态过流事件提供快速跳变响应。
该器件可在模拟电流监测引脚上精确检测输出负载电流。
该器件可采用 2mm x 2mm 10 引脚 HotRod QFN 封装,旨在改善热性能并减小系统尺寸。
器件的额定工作结温范围为 –40°C 至 +125°C。
器件型号 | 封装(1) | 封装尺寸(标称值) |
---|---|---|
LM73100RPW | QFN (10) | 2mm x 2mm |
Changes from Revision * (October 2020) to Revision A (December 2020)
PIN | TYPE | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
EN/UVLO |
1 | Analog Input | Active High Enable for the device. A Resistor Divider on this pin from input supply to GND can be used to adjust the Undervoltage Lockout threshold. Do not leave floating. Refer to Section 7.3.2 for more details. |
OVLO |
2 | Analog Input | A Resistor Divider on this pin from supply to GND can be used to adjust the Overvoltage Lockout threshold. This pin can also be used as an Active Low Enable for the device. Do not leave floating. Refer to Section 7.3.3 for more details. |
PG |
3 | Digital Output | Power Good indication. This is an Open Drain signal which is asserted High when the internal powerpath is fully turned ON and PGTH input exceeds a certain threshold. Refer to Section 7.3.9 for more details. |
PGTH |
4 | Analog Input | Power Good Threshold. Refer to Section 7.3.9 for more details. |
IN |
5 |
Power | Power Input. |
OUT |
6 |
Power | Power Output. |
DVDT |
7 | Analog Output | A capacitor from this pin to GND sets the output turn on slew rate. Leave this pin floating for the fastest turn on slew rate. Refer to Section 7.3.4.1 for more details. |
GND |
8 |
Ground | This is the ground reference for all internal circuits and must be connected to system GND. |
IMON |
9 | Analog Output |
Analog load current monitor. The pin voltage can be used to monitor the output load current. An external resistor from this pin to ground sets the current monitor gain. Recommended to connect external clamp to limit the voltage below abs max rating in case of large current spikes. Connect to ground if not used. Do not leave floating. Refer to Section 7.3.5 for more details. |
DNC |
10 |
X |
Internal test pin. Do not connect anything on this pin. |
Parameter | Pin | MIN | MAX | UNIT | |
---|---|---|---|---|---|
VIN | Maximum Input Voltage Range, –40 ℃ ≤ TJ ≤ 125 ℃ | IN | max (–15, VOUT - 21) | 28 | V |
Maximum Input Voltage Range, –10 ℃ ≤ TJ ≤ 125 ℃ | max (–15, VOUT - 22) | 28 | V | ||
VOUT | Maximum Output Voltage Range, –40 ℃ ≤ TJ ≤ 125 ℃ | OUT | –0.3 | min (28, VIN + 21) | |
Maximum Output Voltage Range, –10 ℃ ≤ TJ ≤ 125 ℃ | –0.3 | min (28, VIN + 22) | |||
VOUT,PLS | Minimum Output Voltage Pulse (< 1 µs) | OUT | –0.8 | ||
VEN/UVLO | Maximum Enable Pin Voltage Range (2) | EN/UVLO | –0.3 | 6.5 | V |
VOVLO | Maximum OVLO Pin Voltage Range (2) | OVLO | –0.3 | 6.5 | V |
VdVdT | Maximum dVdT Pin Voltage Range | dVdt | Internally Limited | V | |
VPGTH | Maximum PGTH Pin Voltage Range (2) | PGTH | –0.3 | 6.5 | V |
VPG | Maximum PG Pin Voltage Range | PG | –0.3 | 6.5 | V |
VIMON | Maximum IMON Pin Voltage Range | IMON | 1.8 | V | |
IMAX | Maximum Continuous Switch Current | IN to OUT | 5.5 | A | |
TJ | Junction temperature | Internally Limited | °C | ||
TLEAD | Maximum Lead Temperature | 300 | °C | ||
TSTG | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101, all pins(2) | ±500 |
Parameter | Pin | MIN | MAX | UNIT | |
---|---|---|---|---|---|
VIN | Input Voltage Range | IN | 2.7 | 23 | V |
VOUT | Output Voltage Range | OUT | min (23, VIN + 20) | V | |
VEN/UVLO | Enable Pin Voltage Range | EN/UVLO | 5 (2) | V | |
VOVLO | OVLO Pin Voltage Range | OVLO | 0.5 | 1.5 | V |
VdVdT | dVdT Capacitor Voltage Rating | dVdt | VIN + 5 V (1) | V | |
VPGTH | PGTH Pin Voltage Range | PGTH | 5 (3) | V | |
VPG | PG Pin Voltage Range | PG | 5 (3) | V | |
VIMON | IMON Pin Voltage | IMON | 1.5 | V | |
IMAX | Continuous Switch Current, , TJ ≤ 125 ℃ | IN to OUT | 5.5 | A | |
TJ | Junction temperature | –40 | 125 | °C |
THERMAL METRIC (1) | LM73100 | UNIT | |
---|---|---|---|
RPW (QFN) | |||
10 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 41.7 (2) | °C/W |
74.5 (3) | °C/W | ||
ΨJT | Junction-to-top characterization parameter | 1 | °C/W |
ΨJB | Junction-to-board characterization parameter | 20 (2) | °C/W |
27.6 (3) | °C/W |
Test Parameter | Description | MIN | TYP | MAX | UNITS |
---|---|---|---|---|---|
INPUT SUPPLY (IN) | |||||
VUVP(R) | IN supply UVP rising threshold | 2.44 | 2.53 | 2.64 | V |
VUVP(F) | IN supply UVP falling threshold | 2.35 | 2.42 | 2.55 | V |
IQ(ON) | IN supply quiescent current, VIN = 2.7 V | 347 | 492 | µA | |
IN supply quiescent current, VIN = 12 V | 426 | 509 | µA | ||
IN supply quiescent current, VIN = 23 V | 459 | 612 | µA | ||
IQ(RCB) | IN supply quiescent current during RCB, VOUT > VIN | 189.7 | 234 | µA | |
IQ(OFF) | IN supply disabled state current (VSD(F) < VEN < VUVLO(R)) | 74.5 | 97.6 | µA | |
ISD | IN supply shutdown current (VEN < VSD(F)) | 4.6 | 8.2 | µA | |
IQ(OVLO) | IN supply OFF state current (OVLO condition), VOUT > VIN | 191 | µA | ||
IINLKG(IRPP) | IN supply leakage current (VIN = –14 V, VOUT = 0 V) | -3.5 | µA | ||
ON RESISTANCE (IN - OUT) | |||||
RON | VIN = 12 V, IOUT = 3 A, TJ = 25 ℃ | 28.4 | mΩ | ||
2.7 ≤ VIN ≤ 23 V, –40 ℃ ≤ TJ ≤ 125 ℃ | 44.85 | mΩ | |||
ENABLE/UNDERVOLTAGE LOCKOUT (EN/UVLO) | |||||
VUVLO(R) | EN/UVLO rising threshold | 1.183 | 1.2 | 1.223 | V |
VUVLO(F) | EN/UVLO falling threshold | 1.076 | 1.09 | 1.116 | V |
VSD(F) | EN/UVLO falling threshold for lowest shutdown current | 0.45 | 0.74 | V | |
IENLKG | EN/UVLO leakage current | –0.1 | 0.1 | µA | |
OVERVOLTAGE LOCKOUT (OVLO) | |||||
VOV(R) | OVLO rising threshold | 1.183 | 1.2 | 1.223 | V |
VOV(F) | OVLO falling threshold | 1.076 | 1.09 | 1.116 | V |
IOVLKG | OVLO pin leakage current, 0.5 V < VOVLO < 1.5 V | –0.1 | 0.1 | µA | |
IOUTLKG(OVLO) | OUT leakage current (OVLO condition), VOUT > VIN | 317 | µA | ||
FIXED FAST-TRIP (OUT) | |||||
IFT | Fixed fast-trip current threshold | 21.9 | A | ||
OUTPUT LOAD CURRENT MONITOR (IMON) | |||||
GIMON | Analog load current monitor gain (IMON : IOUT), IOUT = 0.5 A to 1 A | 144 | 181 | 216 | µA/A |
Analog load current monitor gain (IMON : IOUT), IOUT = 1 A to 5.5 A | 153 | 181 | 207 | µA/A | |
REVERSE CURRENT BLOCKING (IN - OUT) | |||||
VFWD | (VIN - VOUT) forward regulation voltage, IOUT = 10 mA | 4.8 | 16.4 | 28.4 | mV |
VREVTH | (VOUT - VIN) threshold for fast BFET turn off (enter reverse current blocking) | 22.7 | 29.3 | 36.5 | mV |
VFWDTH | (VIN - VOUT) threshold for fast BFET turn on (exit reverse current blocking) | 85.9 | 105.8 | 125 | mV |
IREVLKG(OFF) | Reverse leakage current (unpowered condition), VOUT = 12 V, VIN = 0 V | 4.8 | µA | ||
IREVLKG | Reverse leakage current, (VOUT - VIN) = 21.5 V | 10.10 | 15.86 | µA | |
IOUTLKG(RCB) | OUT leakage current during RCB state while ON, (VOUT - VIN) = 1 V | 247.6 | 322 | µA | |
POWER GOOD INDICATION (PG) | |||||
VPGD | PG pin low voltage while de-asserted, VIN < VUVP(F), VEN < VSD, IPG = 26 µA | 0.67 | 0.9 | V | |
PG pin low voltage while de-asserted, VIN < VUVP(F), VEN < VSD, IPG = 242 µA | 0.78 | 1 | V | ||
PG pin low voltage while de-asserted, VIN > VUVP(R) | 0.6 | V | |||
IPGLKG | PG pin leakage current while asserted | 0.5 | 2 | µA | |
POWERGOOD THRESHOLD (PGTH) | |||||
VPGTH(R) | PGTH rising threshold | 1.183 | 1.2 | 1.223 | V |
VPGTH(F) | PGTH falling threshold | 1.076 | 1.09 | 1.116 | V |
IPGTHLKG | PGTH leakage current | –1 | 1 | µA | |
OVERTEMPERATURE PROTECTION (OTP) | |||||
TSD | Thermal shutdown rising threshold, TJ↑ | 154 | °C | ||
TSDHYS | Thermal shutdown hysteresis, TJ↓ | 10 | °C | ||
DVDT | |||||
IdVdt | dVdt pin charging current | 1.15 | 2.34 | 3.66 | µA |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
tOVLO | Overvoltage lock-out response time | VOVLO > VOV(R) to VOUT↓ | 1.1 | µs | ||
tFT | Fixed fast-trip response time | IOUT > IFT to IOUT↓ | 500 | ns | ||
tSWRCB | Reverse Current Blocking recovery time | (VIN - VOUT) > VFWDTH to VOUT ↑ | 50 | µs | ||
tRCB | Reverse Current Blocking fast comparator response time | (VOUT - VIN) > 1.3 x VREVTH to BFET OFF | 1 | µs | ||
tPGA | PG Assertion de-glitch | 12 | µs | |||
tPGD | PG De-assertion de-glitch | 12 | µs |
PARAMETER | VIN
|
CdVdt = Open | CdVdt = 1800 pF | CdVdt = 3300 pF | UNIT | |
---|---|---|---|---|---|---|
SRON | Output Rising slew rate | 2.7 V | 12.14 | 0.87 | 0.5 | V/ms |
12 V | 28.1 | 1.09 | 0.61 | |||
23 V | 44.78 | 1.25 | 0.71 | |||
tD,ON | Turn on delay | 2.7 V | 0.09 | 0.6 | 0.97 | ms |
12 V | 0.1 | 1.32 | 2.35 | |||
23 V | 0.11 | 1.99 | 3.69 | |||
tR | Rise time | 2.7 V | 0.17 | 2.51 | 4.33 | ms |
12 V | 0.35 | 8.1 | 15.37 | |||
23 V | 0.40 | 14.4 | 25.89 | |||
tON | Turn on time | 2.7 V | 0.27 | 3.11 | 5.31 | ms |
12 V | 0.45 | 10.08 | 17.72 | |||
23 V | 0.50 | 16.41 | 29.57 | |||
tD,OFF | Turn off delay | 2.7 V | 64.44 | 64.44 | 64.44 | µs |
12 V | 25.32 | 25.32 | 25.32 | |||
23 V | 23.02 | 23.02 | 23.02 |
VEN/UVLO = 3 V, COUT = 220 μF, CdVdt = 10 nF, VIN ramped up to 12 V |
COUT = 220 μF, CdVdt = 10 nF, EN/UVLO connected to IN through resistor ladder, 12 V hot-plugged to IN |
COUT = 220 μF, PG pulled up to 3 V, -15 V hot-plugged to IN |
IN= Open, COUT = 220 μF, PG pulled up to 3 V, 20 V hot-plugged to OUT |
COUT = 220 μF, ROUT = 20 Ω, OVLO threshold = 13.2 V, VIN ramped up from 12 V to 16 V |
VIN = 12 V, COUT = Open, OUT stepped from Open → Short-circuit to GND |
VIN = 12 V, COUT = 220 μF, CdVdt = 10 nF, VEN/UVLO stepped up to 3 V |
VIN = 12 V, ROUT = 20 Ω, COUT = 220 μF, CdVdt = 10 nF, VEN/UVLO stepped up to 3 V |
COUT = 220 μF, PG pulled up to 3 V, VIN ramped down from 0 V to -15 V and then ramped up to 0 V |
IN= Open, COUT = 220 μF, PG pulled up to 3 V, VOUT ramped up from 0 V to 20 V |
VIN = 12 V, COUT = Open, OUT stepped from Open → Short-circuit to GND |
The LM73100 is an integrated ideal diode that is used to ensure safe power delivery in a system. The device starts its operation by monitoring the IN bus. When the input supply voltage (VIN) exceeds the undervoltage protection threshold (VUVP), the device samples the EN/UVLO pin. A high level (> VUVLO(R)) on this pin enables the internal power path (BFET+HFET) to start conducting and allow current to flow from IN to OUT. When EN/UVLO pin is held low (< VUVLO(F)), the internal power path is turned off. In case of reverse voltages appearing at the input, the power path remains OFF thereby protecting the output load.
After a successful start-up sequence, the device now actively monitors its load current and input voltage, and controls the internal HFET to ensure that the fast-trip threshold (IFT) is not exceeded and overvoltage spikes are cut-off once they cross the user adjustable overvoltage lockout threshold (VOVLO). This helps to keep the system safe from harmful levels of voltage and current.
The device has integrated reverse current blocking FET (BFET) which operates like an ideal diode. The BFET is linearly regulated to maintain a small constant forward drop (VFWD) in forward conduction mode and turned off completely to block reverse current from OUT to IN if output voltage exceeds the input voltage.
The device also has a built-in thermal sensor based shutdown mechanism to protect itself in case the device temperature (TJ) exceeds the recommended operating conditions.
The LM73100 integrated ideal diode is a compact, feature rich power management device that provides detection, protection and indication in the event of system faults.