ZHCSLN8A November   2020  – May 2021 DAC61404 , DAC81404

PRODUCTION DATA  

  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
  7. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Recommended Operating Conditions
    4. 7.4  Thermal Information
    5. 7.5  Electrical Characteristics
    6. 7.6  Timing Requirements: Write, IOVDD: 1.7 V to 2.7 V
    7. 7.7  Timing Requirements: Write, IOVDD: 2.7 V to 5.5 V
    8. 7.8  Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 1.7 V to 2.7 V
    9. 7.9  Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 1.7 V to 2.7 V
    10. 7.10 Timing Requirements: Read and Daisy Chain, FSDO = 0, IOVDD: 2.7 V to 5.5 V
    11. 7.11 Timing Requirements: Read and Daisy Chain, FSDO = 1, IOVDD: 2.7 V to 5.5 V
    12. 7.12 Timing Diagrams
    13. 7.13 Typical Characteristics
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 R-2R Ladder DAC
      2. 8.3.2 Programmable-Gain Output Buffer
        1. 8.3.2.1 Sense Pins
      3. 8.3.3 DAC Register Structure
        1. 8.3.3.1 DAC Output Update
          1. 8.3.3.1.1 Synchronous Update
          2. 8.3.3.1.2 Asynchronous Update
        2. 8.3.3.2 Broadcast DAC Register
        3. 8.3.3.3 Clear DAC Operation
      4. 8.3.4 Internal Reference
      5. 8.3.5 Power-On Reset (POR)
        1. 8.3.5.1 Hardware Reset
        2. 8.3.5.2 Software Reset
      6. 8.3.6 Thermal Alarm
    4. 8.4 Device Functional Modes
      1. 8.4.1 Power-Down Mode
    5. 8.5 Programming
      1. 8.5.1 Stand-Alone Operation
      2. 8.5.2 Daisy-Chain Operation
      3. 8.5.3 Frame Error Checking
    6. 8.6 Register Map
      1. 8.6.1  NOP Register (address = 00h) [reset = 0000h]
      2. 8.6.2  DEVICEID Register (address = 01h) [reset = 0A60h or 0920h]
      3. 8.6.3  STATUS Register (address = 02h) [reset = 0000h]
      4. 8.6.4  SPICONFIG Register (address = 03h) [reset = 0AA4h]
      5. 8.6.5  GENCONFIG Register (address = 04h) [reset = 4000h]
      6. 8.6.6  BRDCONFIG Register (address = 05h) [reset = 000Fh]
      7. 8.6.7  SYNCCONFIG Register (address = 06h) [reset = 0000h]
      8. 8.6.8  DACPWDWN Register (address = 09h) [reset = FFFFh]
      9. 8.6.9  DACRANGE Register (address = 0Ah) [reset = 0000h]
      10. 8.6.10 TRIGGER Register (address = 0Eh) [reset = 0000h]
      11. 8.6.11 BRDCAST Register (address = 0Fh) [reset = 0000h]
      12. 8.6.12 DACn Register (address = 10h to 13h) [reset = 0000h]
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 Glossary
  13. 13Mechanical, Packaging, and Orderable Information

8.6 Register Map

Table 8-7 lists the memory-mapped registers for the device. All register addresses not listed should be considered as reserved locations and the register contents should not be modified.

Table 8-7 Register Map
ADDR (HEX) REGISTER TYPE RESET (HEX) BIT DESCRIPTION
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
00 NOP W 0000 NOP[15:0]
01 DEVICEID R 0A60(1)
or
0920(2)		 DEVICEID[13:0] VERSIONID[1:0]
02 STATUS R 0000 RESERVED CRC-ALM DAC-BUSY TEMP-ALM
03 SPICONFIG R/W 0AA4 RESERVED TEMPALM-EN DACBUSY-EN CRCALM-EN RESERVED DEV-PWDWN CRC-EN RSVD SDO-EN FSDO RSVD
04 GENCONFIG R/W 4000 RSVD REF-PWDWN RESERVED
05 BRDCONFIG R/W 000F RESERVED DACD-BRDCAST-EN DACC-BRDCAST-EN DACB-BRDCAST-EN DACA-BRDCAST-EN
06 SYNCCONFIG R/W 0000 RESERVED DACD-SYNC-EN DACC-SYNC-EN DACB-SYNC-EN DACA-SYNC-EN
09 DACPWDWN R/W FFFF RESERVED DACD-PWDWN DACC-PWDWN DACB-PWDWN DACA-PWDWN
0A DACRANGE W 0000 DACD-RANGE[3:0] DACC-RANGE[3:0] DACB-RANGE[3:0] DACA-RANGE[3:0]
0E TRIGGER R/W 0000 RESERVED SOFT-CLR ALM-RESET RESERVED SOFT-LDAC SOFT-RESET[3:0]
0F BRDCAST W 0000 BRDCAST-DATA[15:0]
10 DACA W 0000 DACA-DATA[15:0]
11 DACB W 0000 DACB-DATA[15:0]
12 DACC W 0000 DACC-DATA[15:0]
13 DACD W 0000 DACD-DATA[15:0]
(1) Reset code for DAC81404.
(2) Reset code for DAC61404.