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  • DLP3021-Q1 0.3 英寸 WVGA 汽车 DMD

    • ZHCSL02C March   2020  – March 2023 DLP3021-Q1

      PRODUCTION DATA  

  • CONTENTS
  • SEARCH
  • DLP3021-Q1 0.3 英寸 WVGA 汽车 DMD
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  Storage Conditions
    3. 6.3  ESD Ratings
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Electrical Characteristics
    7. 6.7  Timing Requirements
    8. 6.8  Switching Characteristics
    9. 6.9  System Mounting Interface Loads
    10. 6.10 Physical Characteristics of the Micromirror Array
    11. 6.11 Micromirror Array Optical Characteristics
    12. 6.12 Window Characteristics
    13. 6.13 Chipset Component Usage Specification
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Micromirror Array
      2. 7.3.2 Double Data Rate (DDR) Interface
      3. 7.3.3 Micromirror Switching Control
      4. 7.3.4 DMD Voltage Supplies
      5. 7.3.5 Logic Reset
      6. 7.3.6 Temperature Sensing Diode
        1. 7.3.6.1 Temperature Sense Diode Theory
      7. 7.3.7 DMD JTAG Interface
    4. 7.4 System Optical Considerations
      1. 7.4.1 Numerical Aperture and Stray Light Control
      2. 7.4.2 Pupil Match
      3. 7.4.3 Illumination Overfill and Alignment
    5. 7.5 DMD Image Performance Specification
    6. 7.6 Micromirror Array Temperature Calculation
    7. 7.7 Micromirror Landed-On/Landed-Off Duty Cycle
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
    3. 8.3 Application Mission Profile Consideration
  9. 9 Power Supply Recommendations
    1. 9.1 Power Supply Sequencing Requirements
      1. 9.1.1 Power Up and Power Down
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Temperature Diode Pins
  11. 11Device and Documentation Support
    1. 11.1 Device Support
      1. 11.1.1 Device Nomenclature
      2. 11.1.2 Device Markings
    2. 11.2 Documentation Support
      1. 11.2.1 Related Documentation
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 Trademarks
    6. 11.6 静电放电警告
    7. 11.7 Device Handling
    8. 11.8 术语表
  12. 12Mechanical, Packaging, and Orderable Information
  13. 重要声明
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DATA SHEET

DLP3021-Q1 0.3 英寸 WVGA 汽车 DMD

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 符合汽车应用标准：
    • DMD 阵列工作温度范围 -40°C 至 105°C
  • 0.3 英寸对角线微镜阵列
    • 7.6µm 微镜间距
    • ±12° 微镜倾斜角（相对于平面）
    • 采用侧面照明以减小系统尺寸
  • WVGA (864 × 480) 输入分辨率
  • 偏振无关型空间光调制器
  • 与 LED 或激光光源兼容
  • 低功耗：255mW（最大值）
  • 工作温度范围：–40°C 至 105°C
  • 气密封装
  • 可实现系统内验证的 JTAG 边界扫描
  • 与 DLPC120-Q1 汽车 DMD 控制器兼容
  • 80MHz DDR DMD 接口

2 应用

  • 汽车小灯

3 说明

DLP3021-Q1 汽车 DMD 主要面向汽车外部照明控制和显示应用，例如能够显示动态内容的地面投影。地面投影除了协调车辆通信系统和汽车个性化选项外，还可帮助实现车辆对行人 (V2P) 通信，例如倒车和车门打开警告。由于尺寸小且功耗低，采用 DLP3021-Q1 芯片组的投影仪可以支持很多投影应用。这类投影仪可以安装在车辆上的很多位置，例如后视镜、车门、尾灯以及前格栅等等。该芯片组能够与 LED 或激光器搭配使用，以生成具有 125% 以上 NTSC 色域的高饱和度颜色，并且可以与 RGB 或白色光源搭配使用。可以使用 DLP®-FPGA 配置来驱动 DLP3021-Q1 汽车 DMD，从而缩小尺寸，这样便可轻松整合到车辆中。也可以使用 DLPC120-Q1 汽车 DMD 控制器来驱动 DLP3021-Q1 汽车 DMD 并支持 24 位 RGB 视频输入，从而增加内容灵活性。

器件信息
器件型号(1)封装封装尺寸（标称值）
DLP3021-Q1FQR (64)8.55 mm × 16.80 mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
GUID-C86EE25D-A3F6-4673-916B-D0ED7306AA7F-low.gifDLP3021-Q1 系统方框图

4 Revision History

Changes from Revision B (March 2022) to Revision C (March 2023)

  • 添加了“汽车认证”特性要点Go

Changes from Revision A (May 2020) to Revision B (March 2022)

  • 根据最新的德州仪器 (TI) 和行业数据表标准对本文档进行了更新。Go
  • Deleted the environmental characteristic row T_C Case Temperature Measured at TP1 Temperature Cycle and associated footnotes in Go

Changes from Revision * (March 2020) to Revision A (May 2020)

  • 将器件状态从预告信息 更改为量产数据 Go

5 Pin Configuration and Functions

GUID-23BAF65B-501E-4BCD-8327-368175611BE6-low.gif Figure 5-1 FQR Package,64-Pin LGA(Bottom View)
Table 5-1 Pin Functions
PIN TYPE DESCRIPTION
NAME NO.
DATA(0) A2 LVCMOS input Data bus. Synchronous to rising edge and falling edge of DCLK.
DATA(1) A4
DATA(2) B2
DATA(3) B3
DATA(4) B5
DATA(5) C2
DATA(6) C3
DATA(7) B4
DATA(8) C5
DATA(9) D2
DATA(10) D3
DATA(11) D4
DATA(12) D5
DATA(13) E2
DATA(14) F5
DCLK F4 Data clock.
LOADB F3 Parallel latch load enable. Synchronous to rising edge and falling edge of DCLK.
SCTRL E4 Serial control (sync). Synchronous to rising edge and falling edge of DCLK.
TRC F2 Toggle rate control. Synchronous to rising edge and falling edge of DCLK.
DAD_BUS B15 Reset control serial bus. Synchronous to rising edge of SAC_CLK.
RESET_OEZ C15 Active low. Output enable signal for internal reset driver circuitry.
RESET_STROBE B13 Rising edge on RESET_STROBE latches in the control signals.
SAC_BUS A15 Stepped address control serial bus. Synchronous to rising edge of SAC_CLK.
SAC_CLK A14 Stepped address control clock.
TCK F15 JTAG clock.
TDI E13 JTAG data input. Synchronous to rising edge of TCK. Bond pad connects to internal pull up resistor.
TDO G15 LVCMOS output JTAG data output. Synchronous to falling edge of TCK. Tri-state failsafe output buffer.
TMS G14 LVCMOS input JTAG mode select. Synchronous to rising edge of TCK. Bond pad connects to internal pull up resistor.
TEMP_MINUS G13 Analog input Calibrated temperature diode used to assist accurate temperature measurements of DMD die.
TEMP_PLUS G2
VBIAS D15 Power Power supply for positive bias level of mirror reset signal.
VCC A5, B12, C14, D12, F13, G3 Power supply for low voltage CMOS logic. Power supply for normal high voltage at mirror address electrodes. Power supply for offset level of mirror reset signal during power down.
VOFFSET E14 Power Power supply for high voltage CMOS logic. Power supply for stepped high voltage at mirror address electrodes. Power supply for offset level of mirror reset signal.
VREF E15 Power supply for low voltage CMOS DDR interface.
VRESET D14 Power supply for negative reset level of mirror reset signal.
VSS A3, A13, B14, C4, C12, C13, D13, E3, E5, E12, F12, F14, G4, G12 Common return for all power.
RESERVED A1, A12, A16,B1, B16, F1, F16, G1, G5, G16 Reserved Do not connect.

6 Specifications

6.1 Absolute Maximum Ratings

See (2)
MIN MAX UNIT
SUPPLY VOLTAGE(1)
VREF LVCMOS logic supply voltage –0.5 4 V
VCC LVCMOS logic supply voltage –0.5 4 V
VOFFSET Mirror electrode and HVCMOS voltage –0.5 8.75 V
VBIAS Mirror electrode voltage –0.5 17 V
|VBIAS – VOFFSET| Supply voltage delta(3) 8.75 V
VRESET Mirror electrode voltage –11 0.5 V
Input voltage: other inputs –0.5 VREF + 0.3 V
fDCLK Clock frequency 60 82 MHz
ITEMP_DIODE Temperature diode current 500 µA
ENVIRONMENTAL
TARRAY Operating DMD array temperature(4) –40 105 °C
(1) All voltage values are with respect to the ground pins (VSS).
(2) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(3) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than or equal to 8.75 V.
(4) See Section 7.6 section.

6.2 Storage Conditions

Applicable for the DMD as a component or non-operating in a system. The device is not designed to be exposed to corrosive environments.
MINMAXUNIT
TstgDMD storage temperature–40125°C

6.3 ESD Ratings

VALUEUNIT
V(ESD)Electrostatic dischargeHuman-body model (HBM), per AEC Q100-002(1)All Pins±2000V
Charged-device model (CDM) per AEC Q100-011All Pins±750
Corner Pins(2)±750
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) Corner pins are A1, G1, A16, and G16.

6.4 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MINNOMMAXUNIT
SUPPLY VOLTAGE RANGE
VREFLVCMOS interface power supply voltage1.651.81.95V
VCCLVCMOS logic power supply voltage2.252.52.75V
VOFFSETMirror electrode and HVCMOS voltage8.258.58.75V
VBIASMirror electrode voltage15.51616.5V
|VBIAS – VOFFSET|Supply voltage delta(2)8.75V
VRESETMirror electrode voltage–9.5–10–10.5V
VP VT+Positive going threshold voltage0.4 × VREF0.7 × VREFV
VN VT–Negative going threshold voltage 0.3 × VREF0.6 × VREFV
VH ∆VTHysteresis voltage (Vp – Vn)0.1 × VREF0.4 × VREFV
IOH_TDOHigh level output current @ Voh = 2.25 V, TDO, Vcc = 2.25 V–2mA
IOL_TDOLow level output current @ Vol = 0.4 V, TDO, Vcc = 2.25 V2mA
TEMPERATURE DIODE
ITEMP_DIODEMax current source into temperature diode(4)120µA
ENVIRONMENTAL
TARRAY(5)Operating DMD array temperature - steady state(1)–40105°C
ILLUV(3)Illumination, wavelength < 395 nm2.0mW/cm2
ILLOVERFILLIllumination overfill maximum heat load in area shown in Figure 6-1(6)TARRAY ≤ 75°C26mW/mm2
ILLOVERFILLIllumination overfill maximum heat load in area shown in Figure 6-1(6)TARRAY > 75°C20
(1) DMD active array temperature can be calculated as shown in Section 7.6 section and assumes uniform illumination across the array.
(2) To prevent excess current, the supply voltage delta |VBIAS – VOFFSET| must be less than or equal to 8.75 V.
(3) The maximum operation conditions for DMD array temperature and illumination UV shall not be implemented simultaneously.
(4) Temperature diode is to assist in the calculation of the DMD array temperature during operation.
(5) Operating profile information for device micromirror landed duty-cycle and temperature may be provided if requested.
(6) The active area of the DLP3021-Q1 device is surrounded by an aperture on the inside of the DMD window surface that masks structures of the DMD device assembly from normal view. The aperture is sized to anticipate several optical conditions. Overfill light illuminating the area outside the active array can scatter and create adverse effects to the performance of an end application using the DMD. The illumination optical system should be designed to minimize light flux incident outside the active array. Depending on the particular system's optical architecture and assembly tolerances, the amount of overfill light on the outside of the active array may cause system performance degradation. Overfill illumination in excess of this specification may also impact thermal performance.
GUID-7DE6C98F-6498-4EE7-854D-7B9918987383-low.gifFigure 6-1 Illumination Overfill Diagram

6.5 Thermal Information

THERMAL METRIC(1) DLP3021-Q1 UNIT
FQR (LGA)
64 PINS
Thermal resistance Active area to test point 1 (TP1)(1) 7.0 °C/W
(1) The DMD is designed to conduct absorbed and dissipated heat to the back of the package. The cooling system must be capable of maintaining the package within the temperature range specified in the Section 6.4. The total heat load on the DMD is largely driven by the incident light absorbed by the active area, although other contributions include light energy absorbed by the window aperture and electrical power dissipation of the array. Optical systems should be designed to minimize the light energy falling outside the window clear aperture since any additional thermal load in this area can significantly degrade the reliability of the device.

6.6 Electrical Characteristics

Over operating free-air temperature range (unless otherwise noted)(2)
PARAMETER TEST CONDITIONS(1) MIN TYP MAX UNIT
VOH High level output voltage VCC = 2.25 V 1.7 V
IOH = –8 mA
VOH2 High level output voltage(6) VREF = 1.8 V 1.44 V
IOH = –2 mA
VOL Low level output voltage VCC = 2.75 V 0.4 V
IOL = 8 mA
VOL2 Low level output voltage(6) VREF = 1.8 V 0.36 V
IOL = 2 mA
IOZ Output high impedance current VREF = 1.95 V –10 µA
VOL = 0 V
VREF = 1.95 V 10
VOH = VREF
IIL Low level input current(3) VREF = 1.95 V –5 µA
VI = 0 V
IIH High level input current(3) VREF = 1.95 V 6 µA
VI = VREF
IIL2 Low level input current(4) VREF = 1.95 V –785 µA
VI = 0 V
IIH2 High level input current(4) VREF = 1.95 V 6 µA
VI = VREF
IIL3 Low level input current(5) VREF = 1.95 V –5 µA
VI = 0 V
IIH3 High level input current(5) VREF = 1.95 V 785 µA
VI = VREF
CURRENT
IREF Current at VREF = 1.95 V fDCLK = 80 MHz 2.80 mA
Icc Current at VCC = 2.75 V fDCLK = 80 MHz 59.90 mA
IOFFSET Current at VOFFSET = 8.75 V 2.93 mA
IBIAS Current at VBIAS = 16.5 V 2.30 mA
IRESET Current at VRESET = –10.5 V –2.00 mA
POWER
PREF Power at VREF = 1.95 V fDCLK = 80 MHz 5.46 mW
PCC Power at VCC = 2.75 V fDCLK = 80 MHz 164.73 mW
POFFSET Power at VOFFSET = 8.75 V 25.64 mW
PBIAS Power at VBIAS = 16.5 V 37.95 mW
PRESET Power at VRESET = –10.5 V 21.00 mW
PTOTAL Total power at nominal conditions fDCLK = 80 MHz 254.77 mW
CAPACITANCE
CIN Input pin capacitance ƒ = 1 MHz 20 pF
CA Analog pin capacitance (TEMP_PLUS and TEMP_MINUS pins) ƒ = 1 MHz 65 pF
Co Output pin capacitance ƒ = 1 MHz 20 pF
(1) All voltage values are with respect to the ground pins (VSS).
(2) Device electrical characteristics are over Section 6.4 unless otherwise noted.
(3) Specification is for LVCMOS input pins, which do not have pull up or pull down resistors. See Section 5 section.
(4) Specification is for LVCMOS input pins which do have pull up resistors (JTAG: TDI, TMS). See Section 5 section.
(5) Specification is for LVCMOS input pins which do have pull down resistors. See Section 5 section.
(6) Specification is for LVCMOS JTAG output pin TDO.

6.7 Timing Requirements

Over Section 6.4 unless otherwise noted.
MIN NOM MAX UNIT
DMD MIRROR AND SRAM CONTROL LOGIC SIGNALS
tSU Setup time SAC_BUS low before SAC_CLK↑ 1.0 ns
tH Hold time SAC_BUS low after SAC_CLK↑ 1.0 ns
tSU Setup time DAD_BUS high before SAC_CLK↑ 1.0 ns
tH Hold time DAD_BUS after SAC_CLK↑ 1.0 ns
tC Cycle time SAC_CLK 12.5 16.67 ns
tW Pulse width 50% to 50% reference points: SAC_CLK high or low 5.0 ns
tR Rise time 20% to 80% reference points: SAC_CLK 2.5 ns
tF Fall time 80% to 20% reference points: SAC_CLK 2.5 ns
DMD DATA PATH AND LOGIC CONTROL SIGNALS
tSU Setup time DATA(14:0) before DCLK↑ or DCLK↓ 1.0 ns
tH Hold time DATA(14:0) after DCLK↑ or DCLK↓ 1.0 ns
tSU Setup time SCTRL before DCLK↑ or DCLK↓ 1.0 ns
tH Hold time SCTRL after DCLK↑ or DCLK↓ 1.0 ns
tSU Setup time TRC before DCLK↑ or DCLK↓ 1.0 ns
tH Hold time TRC after DCLK↑ or DCLK↓ 1.0 ns
tSU Setup time LOADB low before DCLK↑ 1.0 ns
tH Hold time LOADB low after DCLK↓ 1.0 ns
tSU Setup time RESET_STROBE high before DCLK↑ 1.0 ns
tH Hold time RESET_STROBE after DCLK↑ 3.5 ns
tC Cycle time DCLK 12.5 16.67 ns
tW Pulse width 50% to 50% reference points: DCLK high or low 5.0 ns
tW(L) Pulse width 50% to 50% reference points: LOADB low 7.0 ns
tW(H) Pulse width 50% to 50% reference points: RESET_STROBE high 7.0 ns
tR Rise time 20% to 80% reference points: DCLK, DATA, SCTRL, TRC, LOADB 2.5 ns
tF Fall time 80% to 20% reference points: DCLK, DATA, SCTRL, TRC, LOADB 2.5 ns
JTAG BOUNDARY SCAN CONTROL LOGIC SIGNALS
fTCK Clock frequency TCK 10 MHz
tC Cycle time TCK 100 ns
tW Pulse width 50% to 50% reference points: TCK high or low 10 ns
tSU Setup time TDI valid before TCK↑ 5 ns
tH Hold time TDI valid after TCK↑ 25 ns
tSU Setup time TMS valid before TCK↑ 5 ns
tH Hold time TMS valid after TCK↑ 25 ns
tR Rise time 20% to 80% reference points: TCK, TDI, TMS 2.5 ns
tR Fall time 80% to 20% reference points: TCK, TDI, TMS 2.5 ns
GUID-7FF76588-9753-4307-A188-F36B998D5F37-low.gif Figure 6-2 DMD Mirror and SRAM Control Logic Timing Requirements
GUID-3431A18E-EE00-4669-989E-DDB5D19FA02A-low.gif Figure 6-3 DMD Data Path and Control Logic Timing Requirements
GUID-8D9E2C27-4AFC-4C83-9BFC-D3113005BC9F-low.gif Figure 6-4 JTAG Boundary Scan Control Logic Timing Requirements

6.8 Switching Characteristics

Over operating free-air temperature range (unless otherwise noted).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tPDOutput propagation, clock to Q (see Figure 6-4)CL = 11 pF, from (Input) falling edge of TCK to (Output) TDO, see Figure 6-4325ns
GUID-98E696B9-25D7-4FBC-9970-3925B8F55BE0-low.gif
See Section 7.3.1 section for more information.
Figure 6-5 Test Load Circuit for Output Propagation Measurement

6.9 System Mounting Interface Loads

PARAMETERMINNOMMAXUNIT
Uniformly distributed within the Thermal Interface Area shown in Figure 6-670N
Uniformly distributed within the Electrical Interface Area shown in Figure 6-6100N
GUID-2B62BA33-AA13-4715-B79E-207A927194DD-low.gifFigure 6-6 System Interface Loads

6.10 Physical Characteristics of the Micromirror Array

PARAMETERVALUEUNIT
NNumber of active columnsSee Figure 6-7684micromirrors
MNumber of active rowsSee Figure 6-7608micromirrors
εMicromirror (pixel) pitch – diagonalSee Figure 6-87.6µm
PMicromirror (pixel) pitch – horizontal and verticalSee Figure 6-810.8µm
Micromirror active array widthP × M + P / 2; see Figure 6-76.5718mm
Micromirror active array height(P × N) / 2 + P / 2; see Figure 6-73.699mm
Micromirror active borderPond of micromirror (POM)(1)10micromirrors/side
(1) The structure and qualities of the border around the active array includes a band of partially functional micromirrors called the POM. These micromirrors are structurally and/or electrically prevented from tilting toward the bright or ON state, but still require an electrical bias to tilt toward OFF.
GUID-3FAB58DD-283D-4FB8-8C1E-2D1B645FE441-low.gifFigure 6-7 Micromirror Array Physical Characteristics
GUID-2340D11A-0B8E-4F90-B4A3-2E8D2C93F654-low.gifFigure 6-8 Mirror (Pixel) Pitch

 
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