THP210 是一款超低失调电压、低噪声、高电压、精密、全差分放大器,可轻松过滤和驱动全差分信号链。THP210 还可用于将单端源转换为高分辨率模数转换器 (ADC) 所需的差分输出。双极性超级 ß 输入专为实现出色的失调电压、低噪声和 THD 而设计,可在极低的静态电流和输入偏置电流下产生极低的噪声系数。该器件专为要求低失调电压和功耗以及高信噪比 (SNR) 的信号调节电路而设计。
THP210 具有高压电源功能,支持高达 ±18V 的电源电压。高压差分信号链可通过该功能提高裕量和动态范围,而无需为差分信号的每个极性添加单独的放大器。极低的电压和电流噪声使得 THP210 可用于高增益配置,而对信号保真度的影响微乎其微。
器件型号 | 封装 | 封装尺寸(标称值) |
---|---|---|
THP210 | VSSOP (8) | 3.00mm × 3.00mm |
SOIC (8) | 4.90mm x 3.91mm |
Changes from Revision B (October 2020) to Revision C (March 2021)
Changes from Revision A (May 2020) to Revision B (October 2020)
Changes from Revision * (February 2020) to Revision A (May 2020)
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
IN– | 1 | I | Inverting (negative) amplifier input |
IN+ | 8 | I | Noninverting (positive) amplifier input |
OUT– | 5 | O | Inverting (negative) amplifier output |
OUT+ | 4 | O | Noninverting (positive) amplifier output |
PD | 7 | I | Power down. PD = logic low = power off mode. PD = logic high = normal operation. The logic threshold is referenced to VS+. If power down is not needed, pull up PD. |
VOCM | 2 | I | Output common-mode voltage control input |
VS– | 6 | I | Negative power-supply input |
VS+ | 3 | I | Positive power-supply input |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
VS | Supply voltage | Single supply | 40 | V | |
Dual supply | ±20 | V | |||
IN+, IN–, differential voltage(2) | ±0.5 | V | |||
IN+, IN–, VOCM, PD, OUT+, OUT− voltage(3) | VVS– – 0.5 | VVS+ + 0.5 | V | ||
IN+, IN− current | –10 | 10 | mA | ||
OUT+, OUT− current | –50 | 50 | mA | ||
Output short-circuit(4) | Continuous | ||||
TA | Operating temperature | –40 | 150 | °C | |
TJ | Junction temperature | –40 | 175 | °C | |
Tstg | Storage temperature | –65 | 150 | °C |
VALUE | UNIT | |||
---|---|---|---|---|
V(ESD) | Electrostatic discharge | Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
Charged device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 |
MIN | NOM | MAX | UNIT | |||
---|---|---|---|---|---|---|
VS | Supply voltage | Single-supply | 3 | 36 | V | |
Dual-supply | ±1.5 | ±18 | ||||
TA | Specified temperature | –40 | 125 | °C |
THERMAL METRIC(1) | THP210 | UNIT | ||
---|---|---|---|---|
D (SOIC) | DGK (VSSOP) | |||
8 PINS | 8 PINS | |||
RθJA | Junction-to-ambient thermal resistance | 129.1 | 181.1 | °C/W |
RθJC(top) | Junction-to-case (top) thermal resistance | 69.4 | 68.3 | °C/W |
RθJB | Junction-to-board thermal resistance | 72.5 | 102.8 | °C/W |
ψJT | Junction-to-top characterization parameter | 20.7 | 10.6 | °C/W |
ψJB | Junction-to-board characterization parameter | 71.8 | 101.1 | °C/W |
RθJC(bot) | Junction-to-case (bottom) thermal resistance | N/A | N/A | °C/W |
PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
---|---|---|---|---|---|---|
OFFSET VOLTAGE | ||||||
VIO | Input-referred offset voltage | 10 | ±40 | µV | ||
TA = –40°C to +125°C | ±75 | |||||
Input offset voltage drift | TA = –40°C to +125°C | 0.1 | ±0.35 | µV/°C | ||
PSRR | Power-supply rejection ratio | ±0.025 | ±0.25 | µV/V | ||
TA = –40°C to +125°C | ±0.5 | |||||
INPUT BIAS CURRENT | ||||||
IB | Input bias current | ±0.2 | ±2 | nA | ||
TA = –40°C to +125°C | ±4 | |||||
Input bias current drift | TA = –40°C to +125°C | ±2 | ±15 | pA/°C | ||
IOS | Input offset current | ±0.2 | ±1 | nA | ||
TA = –40°C to +125°C | ±3 | |||||
Input offset current drift | TA = –40°C to +125°C | 1 | ±10 | pA/°C | ||
NOISE | ||||||
en | Input differential voltage noise | f = 1 kHz | 3.7 | nV/√Hz | ||
f = 10 Hz | 4 | |||||
f = 0.1 to 10 Hz | 0.1 | µVPP | ||||
ei | Input current noise, each input | f = 1 kHz | 300 | fA/√Hz | ||
f = 10 Hz | 400 | |||||
f = 0.1 to 10 Hz | 13.4 | pAPP | ||||
INPUT VOLTAGE | ||||||
Common-mode voltage range | TA = –40°C to +125°C | VVS– + 1 | VVS+ – 1 | V | ||
CMRR | Common-mode rejection ratio | VVS– + 1 V ≤ VICM ≤ VVS+ – 1 V |
140 |
dB | ||
VVS– + 1 V ≤ VICM ≤ VVS+ – 1 V, VS = ±18 V | 126 | 140 | ||||
VVS– + 1 V ≤ VICM ≤ VVS+ – 1 V, VS = ±18 V, TA = –40°C to +125°C | 120 | |||||
INPUT IMPEDANCE | ||||||
Input impedance differential mode | VICM = 0 V | 1 || 1 | GΩ || pF | |||
OPEN-LOOP GAIN | ||||||
AOL | Open-loop voltage gain | VS = ±2.5 V, VVS– + 0.2 V < VO < VVS+ – 0.2 V | 115 | 120 | dB | |
VS = ±2.5 V, VVS– + 0.3 V < VO < VVS+ – 0.3 V, TA = –40°C to +125°C | 110 | 120 | ||||
VS = ±15 V, VVS– + 0.6 V < VO < VVS+ – 0.6 V | 115 | 120 | ||||
VS = ±15 V, VVS– + 0.6 V < VO < VVS+ – 0.6 V, TA = –40°C to +125°C |
110 | 120 | ||||
FREQUENCY RESPONSE | ||||||
SSBW | Small-signal bandwidth | VO = 100 mVPP | 7 | MHz | ||
GBP | Gain-bandwidth product | VO = 100 mVPP, gain = –10 V/V | 9.2 | MHz | ||
FBP | Full-power bandwidth | VO = 1 VPP | 2.4 | MHz | ||
SR | Slew rate | 10-V step | 15 | V/µs | ||
Settling time | To 0.1% of final value, VO = 10-V step | 1 | µs | |||
To 0.01% of final value, VO= 10-V step | 1.2 | |||||
THD+N | Total harmonic distortion and noise | Differential input, f = 1 kHz, VO = 10 VPP | –120 | dB | ||
THD+N | Total harmonic distortion and noise | Single-ended input, f = 1 kHz, VO = 10 VPP | –115 | |||
THD+N | Total harmonic distortion and noise | Differential input, f = 10 kHz, VO = 10 VPP | –112 | |||
Total harmonic distortion and noise | Single-ended input, f = 10 kHz, VO = 10 VPP | –107 | ||||
HD2 | Second-order harmonic distortion | Differential input, f = 1 kHz, VO = 10 VPP | –120 | |||
Single-ended input, f = 1 kHz, VO = 10 VPP | –126 | |||||
HD3 | Third-order harmonic distortion | Differential input, f = 1 kHz, VO = 10 VPP | –120 | |||
Single-ended input, f = 1 kHz, VO = 10 VPP | –119 | |||||
Overdrive recovery time | gain = –5 V/V, 2x output overdrive, dc-coupled | 3.3 | µs | |||
ZO | Open-loop output impedance | f = 100 kHz (differential) | 14 | Ω | ||
CLOAD | Capacitive load drive | Differential capacitive load, no output isolation resistors, phase margin = 30° | 50 | pF | ||
OUTPUT | ||||||
VOL | Negative output voltage swing from rail | VS = ±2.5 V | 100 | mV | ||
VS = ±2.5 V, TA = –40°C to +125°C | 100 | |||||
VS = ±18 V | 230 | |||||
VS = ±18 V, TA = –40°C to +125°C | 270 | |||||
VOH | Positive output voltage swing from rail | VS = ±2.5 V | 100 | |||
VS = ±2.5 V, TA = –40°C to +125°C | 100 | |||||
VS = ±18 V | 230 | |||||
VS = ±18 V, TA = –40°C to +125°C | 270 | |||||
ISC | Short-circuit current | ±31 | mA | |||
OUTPUT COMMON-MODE VOLTAGE | ||||||
Small-signal bandwidth from VOCM pin | VVOCM = 100 mVPP | 2 | MHz | |||
Large-signal bandwidth from VOCM pin | VVOCM = 0.6 VPP | 5.7 | ||||
Slew rate from VOCM pin | VVOCM = 0.5-V step, rising | 4.2 | V/µs | |||
VVOCM = 0.5-V step, falling | 5.5 | |||||
DC output balance | VVOCM fixed midsupply (VO = ±1 V) | 78 | dB | |||
VOCM Input voltage range | VS = ±2.5 V | VVS– + 1 | VVS+ – 1 | V | ||
VS = ±18 V | VVS– + 2 | VVS+ – 2 | ||||
VOCM input impedance | 2.5 || 1 | MΩ || pF | ||||
VOCM offset from mid-supply | VVOCM pin floating, VO = VICM = 0 V | ±1 | mV | |||
VOCM common-mode offset voltage | VVOCM = VICM, VO = 0 V | ±1 | ±6 | |||
VVOCM = VICM, VO = 0 V, TA = –40°C to +125°C | ±10 | |||||
VOCM common-mode offset voltage drift | VVOCM = VICM, VO = 0 V, TA = –40°C to +125°C | ±20 | ±60 | µV/°C | ||
POWER SUPPLY | ||||||
IQ | Quiescent operating current | 0.95 | 1.05 | mA | ||
TA = –40°C to +125°C | 1.4 | |||||
POWER DOWN | ||||||
V PD(HI) | Power-down enable voltage | TA = –40°C to +125°C | VVS+ – 0.5 | V | ||
V PD(LOW) | Power-down disable voltage | TA = –40°C to +125°C | VVS+ – 2.0 | |||
PD bias current | V PD = VVS+ – 2 V | 1 | 2 | µA | ||
Powerdown quiescent current | 10 | 20 | µA | |||
Turn-on time delay | VIN = 100 mV, Time to VO = 90% of final value | 10 | µs | |||
Turn-off time delay | VIN = 100 mV, Time to VO = 10% of original value | 15 |
at VVS = ±15 V, TA = 25°C, VVOCM = VVICM = 0 V, RF = 2 kΩ, RL = 10 kΩ, gain = –1 V/V, and VPD = VVS+ (unless otherwise noted)
VS = ±1.5 V, N = 190, mean = –2.66 µV, std dev = 8.81 µV |
VS = ±15 V |
VS = ±18 V, VOCM = 0 V |
f = 1 kHz, VS = ±15 V |
VS = ±15 V, CL = 50 pF |
VS = ±15 V |
AV = 1 |
VS = ±15 V, N = 120, mean = –1.13 µV, std dev = 5.61 µV |
VS = ±18 V, VOCM = floating |
VOUT = 3 VRMS, VS = ±15 V |
VS = ±15 V, CL = 50 pF |
VS = ±15 V |
VS = ±15 V |
VS = ±15 V |
AV = 10 |
The THP210 is a fully differential amplifier (FDA) configuration that offers high dc precision, very low noise and harmonic distortion in a single, low-power amplifier. The FDA is a flexible device where the main aim is to provide a purely differential output signal centered on a user-configurable, common-mode voltage that is usually matched to the input common-mode voltage required by an analog-to-digital converter (ADC). The circuit used for characterization of the differential-to-differential performance is seen in Figure 7-1
A similar circuit is used for single-ended to differential measurements, as shown in Figure 7-2.
The characterization plots fix the RF (RF1 = RF2) value at 2 kΩ, unless otherwise noted. This value can be adjusted to match the system design parameters with the following considerations in mind:
The THP210 is a low-noise, low-distortion fully-differential amplifier (FDA) that features Texas Instrument's super-beta bipolar input devices. Super-beta input devices feature very low input bias current as compared to standard bipolar technology. The low input bias current and current noise makes the THP210 an excellent choice for high-performance applications that require low-noise, differential-signal processing without significant current consumption. This device is also designed for analog-to-digital input circuits that require low offset and low noise in a single fully-differential amplifier. The THP210 features high-voltage capability, which allows the device to be used in ±15-V supply circuits without any additional voltage clamping or regulators. Because this device is unity-gain stable, the device allows high-voltage input signals to be attenuated to the low-voltage ADC domain without requiring additional compensation techniques.
The THP210 is designed on a modern bipolar process that features TI's super-beta input transistors. Traditional bipolar transistors feature excellent voltage noise and offset drift, but suffer a tradeoff in high input bias current (IB) and high input bias current noise. Super-beta transistors offer the benefits of low voltage noise and low offset drift with an order of magnitude reduction in input bias current and reduction in input bias current noise. For many filter circuits, input bias current noise can dominate in circuits where higher resistance input resistors are used. The THP210 enables a fully-differential, low-noise amplifier design without restrictions of low input resistance at a power level unmatched by traditional single-ended amplifiers.
The THP210 features a power-down circuit to disable the amplifier when a low-power mode is required by the system. In the power-down state, the amplifier outputs are in a high-impedance state, and the amplifier total quiescent current is reduced to less than 20 µA.
The THP210 offers considerable flexibility in the configuration and selection of resistor values. Low input bias current and bias current noise allows for larger gain resistor values with minimal impact to noise or offset, see Section 9.1.3 for more details.
The design starts with the selection of the feedback resistor value. The 2-kΩ feedback resistor value used for the characterization curves is a good compromise among power, noise, and phase margin considerations. With the feedback resistor values selected (and set equal on each side), the input resistors are set to obtain the desired gain, with input impedance also set with these input resistors. Differential I/O designs provide an input impedance that is the sum of the two input resistors. Single-ended input to differential output designs present a more complicated input impedance. Most characteristic curves implement the single-ended to differential design as the more challenging requirement over differential-to-differential I/O designs.
During overload or fault conditions, many bipolar-based amplifiers draw significant (three to five times) quiescent current if the output voltage is clipped (meaning the output voltage becomes limited by the negative or positive supply rail).
The primary cause for this condition is that common-emitter output stages can consume excessive base current (up to 100x) when overdriven into saturation. In addition, the overload condition causes the feedback to be broken, which causes the slew boost to be permanently on. Depending on the slew boost circuit, this increases the tail current up to 4x.
The THP210 has an intelligent overload detection scheme that eliminates this problem, meaning that there is virtually no additional current consumption in the case of an overload event, represented in Figure 8-1. The protection circuit continuously monitors both the input and output stages of the amplifier. Figure 8-1 shows a measurements of the overload power limit behavior. If a large input voltage step (referred to as ΔVIN) is detected, the protection circuit checks for the presence of a rapid change in the voltage at the output (referred to as ΔVO). If the output is not changing because the output is clipped at supply rail, the protection circuit disables the slew-boost circuit and limit the base current of the predriver to prevent output saturation. After the overload condition is removed, the amplifier rapidly recovers to normal operating condition. Figure 8-1 indicates that in case of an overloaded output the current consumption at the supply pins (referred to I(VS+) and I(VS–)) does not exceed the limitations, and quickly recovers as soon as the overload condition has been removed.
The stability of the amplifiers is of key importance when designing application circuits with fully differential amplifiers. This stability becomes especially important when driving capacitive loads, such as the input for successive-approximation-register (SAR) analog-to-digital converters (ADCs). A trade-off is made between the bandwidth of an amplifier and keeping power consumption low; in many cases, FDAs are not unity gain stable. Currently, many FDAs are primarily designed to support high-speed ADCs, and thus, are typically decompensated. This decompensation comes with the drawback that the noise performance degrades because of noise gain peaking. Additional components and compensation techniques are required to handle these challenges and prevent potential instability of the FDA. For detailed analysis of how stability is defined and affected, see TI Precision Labs – Fully Differential Amplifiers – FDA Stability and Simulating Phase Margin.
The THP210 is unity-gain stable; therefore, this device can be used in gain configurations with gains > 1, and also in attenuating configurations with gains < 1, without requiring compensation techniques and sacrificing dynamic performance. This device can be of prime use for applications that need to interface large input signals to the low-voltage ADC domain.