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  • THP210 超低失调电压、高电压、低噪声、精密、全差分放大器

    • ZHCSKT9C January   2020  – March 2021 THP210

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  • THP210 超低失调电压、高电压、低噪声、精密、全差分放大器
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Characterization Configuration
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Super-Beta Input Bipolar Transistors
      2. 8.3.2 Power Down
      3. 8.3.3 Flexible Gain Setting
      4. 8.3.4 Amplifier Overload Power Limit
      5. 8.3.5 Unity Gain Stability
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
      1. 9.1.1 I/O Headroom Considerations
      2. 9.1.2 DC Precision Analysis
        1. 9.1.2.1 DC Error Voltage at Room Temperature
        2. 9.1.2.2 DC Error Voltage Over Temperature
      3. 9.1.3 Noise Analysis
      4. 9.1.4 Mismatch of External Feedback Network
      5. 9.1.5 Operating the Power-Down Feature
      6. 9.1.6 Driving Capacitive Loads
      7. 9.1.7 Driving Differential ADCs
        1. 9.1.7.1 RC Filter Selection (Charge Kickback Filter)
        2. 9.1.7.2 Settling Time Driving the ADC Sample-and-Hold Operating Behavior
        3. 9.1.7.3 THD Performance
    2. 9.2 Typical Applications
      1. 9.2.1 MFB Filter
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curve
      2. 9.2.2 ADS891x With Single-Ended RC Filter Stage
        1. 9.2.2.1 Design Requirements
          1. 9.2.2.1.1 Measurement Results
      3. 9.2.3 Attenuation Configuration Drives the ADS8912B
        1. 9.2.3.1 Design Requirements
          1. 9.2.3.1.1 Measurement Results
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
      1. 11.1.1 Board Layout Recommendations
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 Development Support
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 静电放电警告
    7. 12.7 术语表
  13. 13Mechanical, Packaging, and Orderable Information
  14. 重要声明
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DATA SHEET

THP210 超低失调电压、高电压、低噪声、精密、全差分放大器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 输入失调电压：±40µV（最大值）
  • 输入失调电压温漂：0.35µV/°C（最大值）
  • 低电源电流：±18V 下为 950µA
  • 低输入偏置电流：2nA（最大值）
  • 低输入偏置电流温漂：15pA/°C（最大值）
  • 增益带宽积：9.2MHz
  • 差分输出压摆率：15V/µs
  • 低输入电压噪声：1kHz 时为 3.7nV/√Hz
  • 低 THD + N：10kHz 时为 -120dB
  • 宽输入和输出共模范围
  • 宽单电源工作电压范围：3V 至 36V
  • 低电源电流断电特性：< 20µA
  • 过载功率限制
  • 电流限制
  • 封装：8 引脚 VSSOP，8 引脚 SOIC
  • 温度范围：–40°C 至 +125°C

2 应用

  • 数据采集 (DAQ)
  • 模拟输入模块
  • 变电站自动化
  • 半导体测试
  • 实验室和现场仪表

3 说明

THP210 是一款超低失调电压、低噪声、高电压、精密、全差分放大器，可轻松过滤和驱动全差分信号链。THP210 还可用于将单端源转换为高分辨率模数转换器 (ADC) 所需的差分输出。双极性超级 ß 输入专为实现出色的失调电压、低噪声和 THD 而设计，可在极低的静态电流和输入偏置电流下产生极低的噪声系数。该器件专为要求低失调电压和功耗以及高信噪比 (SNR) 的信号调节电路而设计。

THP210 具有高压电源功能，支持高达 ±18V 的电源电压。高压差分信号链可通过该功能提高裕量和动态范围，而无需为差分信号的每个极性添加单独的放大器。极低的电压和电流噪声使得 THP210 可用于高增益配置，而对信号保真度的影响微乎其微。

器件信息(1)
器件型号 封装 封装尺寸（标称值）
THP210 VSSOP (8) 3.00mm × 3.00mm
SOIC (8) 4.90mm x 3.91mm
(1) 如需了解所有可用封装，请参阅数据表末尾的封装选项附录。

 

GUID-28A3231B-EBAA-4ADC-9A3E-211292821908-low.gif精密、低噪声、低功耗、全差分放大器增益模块和接口
GUID-99EBC41D-4832-4E4B-9F2A-7AE5D94E3DEB-low.gif低输入失调电压

4 Revision History

Changes from Revision B (October 2020) to Revision C (March 2021)

  • Changed PD pin description to clarify use of pin Go
  • Changed Figure 6-1, Input Offset Voltage Histogram Go
  • Changed Figure 6-2, Input Offset Voltage Histogram Go
  • Changed Figure 6-19, Output Impedance vs Frequency Go
  • Changed Y-axis unit from nV/√HZ to V/√HZ for Figure 9-5, Calculated Noise Densities vs Gain Settings Go
  • Changed Y-axis unit from nV/√HZ to V/√HZ for Figure 9-6, Calculated Noise Densities vs Gain Settings Go

Changes from Revision A (May 2020) to Revision B (October 2020)

  • 更新了整个文档中的表格、图和交叉参考的编号格式。Go
  • 添加了 D (SOIC-8) 封装和相关内容Go
  • Changed Figure 7-1, Differential Source to a Differential Gain of a 1-V/V Test Circuit, for clarityGo
  • Changed layout example circuit drawing for clarityGo

Changes from Revision * (February 2020) to Revision A (May 2020)

  • 将器件状态从预告信息（预发布）更改为量产数据（正在供货）Go

5 Pin Configuration and Functions

GUID-FC790CF0-5C0D-4F27-8127-FE589AE79530-low.gifFigure 5-1 D (SOIC-8) and DGK (VSSOP-8) Packages, Top View
Pin Functions
PIN I/O DESCRIPTION
NAME NO.
IN– 1 I Inverting (negative) amplifier input
IN+ 8 I Noninverting (positive) amplifier input
OUT– 5 O Inverting (negative) amplifier output
OUT+ 4 O Noninverting (positive) amplifier output
PD 7 I Power down.
PD = logic low = power off mode.
PD = logic high = normal operation.
The logic threshold is referenced to VS+.
If power down is not needed, pull up PD.
VOCM 2 I Output common-mode voltage control input
VS– 6 I Negative power-supply input
VS+ 3 I Positive power-supply input

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VS Supply voltage Single supply 40 V
Dual supply  ±20 V
IN+, IN–, differential voltage(2) ±0.5 V
IN+, IN–, VOCM, PD, OUT+, OUT− voltage(3) VVS– – 0.5 VVS+ + 0.5 V
IN+, IN− current –10 10 mA
OUT+, OUT− current –50 50 mA
Output short-circuit(4) Continuous
TA Operating temperature –40 150 °C
TJ Junction temperature –40 175 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Input pins IN+ and IN– are connected with anti-parallel diodes in between the two terminals.  Differential input signals that are greater than 0.5 V or less than –0.5 V must be current-limited to 10 mA or less.
(3) Input terminals are diode-clamped to the supply rails (VS+, VS–). Input signals that swing more than 0.5 V greater or less the supply rails must be current-limited to 10 mA or less.
(4) Short-circuit to VS / 2.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

 
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