具有 –10V 输入能力的 UCC27614 单通道 30V、10A 低侧栅极驱动器
- ZHCSKO8C June 2021 – January 2022 UCC27614
  
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具有 –10V 输入能力的 UCC27614 单通道 30V、10A 低侧栅极驱动器

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

典型 10A 灌电流，10A 拉电流输出
输入和使能引脚可承受高达 –10V 的电压
绝对最大 VDD 电压：30V
宽 VDD 工作电压范围：4.5V 至 26V，具有 UVLO 功能
采用 2mm X 2mm SON8 封装
典型值为 17.5ns 的传播延迟
SOIC8 封装的 EN（使能）引脚
IN– 引脚可用于启用/禁用功能
VDD 独立输入阈值（兼容 TTL）
可用作反相或同相驱动器
工作结温范围：–40°C 至 150°C

2 应用

电信开关模式电源
功率因数校正 (PFC) 电路
太阳能电源
电机驱动器
高频线路驱动器
脉冲变压器驱动器
高功率缓冲器

简化版应用示意图

3 说明

UCC27614 是一款单通道、高速、低侧栅极驱动器，能够有效地驱动 MOSFET、IGBT、SiC 和 GaN 电源开关。UCC27614 的典型峰值驱动强度为 10A，这有助于缩短电源开关的上升和下降时间、降低开关损耗并提高效率。UCC27614 器件的短传播延迟可改善系统的死区优化、控制环路响应，提高脉宽利用率和瞬态性能，从而提高功率级效率。

UCC27614 可以在输入端处理 –10V 的电压，通过平缓的接地弹跳提高系统稳健性。输入与电源电压无关，可以连接大多数控制器输出，从而更大程度地提高控制灵活性。独立的使能信号支持在不依赖主控制逻辑的情况下对功率级进行控制。如果在系统中检测到故障，栅极驱动器可以快速关断功率级（需要关断动力总成）。使能功能还可提高系统稳健性。许多高频开关电源在电源器件的栅极都存在高频噪音，这种噪音会进入栅极驱动器的输出引脚，造成驱动器故障。UCC27614 具有瞬态反向电流和反向电压功能，因此在这种情况下具有优异的性能。

如果 VDD 电压低于指定的 UVLO 阈值，强大的内部下拉 MOSFET 可使输出保持低电平。此有源下拉特性可进一步改善系统稳健性。UCC27614 器件采用 2-mm × 2mm 封装并提供 10A 驱动电流，可提高系统功率密度。这种小型封装还可优化栅极驱动器放置并改进布局。

器件信息

器件型号	封装⁽¹⁾	封装尺寸（标称值）
UCC27614	SON (8)	2.0mm x 2.0mm
UCC27614	SOIC (8)	4.90mm × 3.91mm

(1) 如需了解所有可用封装，请见产品说明书末尾的可订购产品附录。

4 Revision History

Changes from Revision B (November 2021) to Revision C (January 2022)

从整个数据表中删除了“预告信息”通知Go
Added additional DESCRIPTION information.Go

5 Pin Configuration and Functions

Figure 5-1 8-Pin SONDSG PackageTop View

Figure 5-2 8-Pin SOICD PackageTop View

Table 5-1 Pin Functions

PIN			TYPE⁽¹⁾	DESCRIPTION
NAME	SON DSG NO.	SOIC D NO.	TYPE⁽¹⁾	DESCRIPTION
EN	—	3	I	Enable or disable control pin. If not used, connect to VDD.
GND	2,3	4,5	G	Device ground or reference
IN	—	2	I	Non-inverting PWM input
IN+	1	—	I	Non-inverting PWM input. If not used, connect to VDD.
IN-	8	—	I	Inverting PWM input. If not used, connect to GND.
OUT	4,5	6,7	O	Output of the driver
VDD	6,7	1,8	P	Driver bias supply. Connect the positive node of the voltage source to this pin through an impedance for high common mode noise rejection. Bypass this pin with two ceramic capacitors, generally >=1 µF and 0.1 µF, which are referenced to GND pin of this device.
	Thermal Pad	—	—	Connect to GND through large copper plane. This pad is not a low-impedance path to GND.

(1) I/O = Digital input/output, IA = Analog input, AO= Analog output, P = Power connection

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾⁽³⁾

		MIN	MAX	UNIT
Supply voltage	VDD	–0.3	30	V
Output Voltage (DC)	VOUT	–0.3	VDD +0.3	V
Output Voltage (200-ns Pulse)	VOUT	–2	VDD +3	V
Input Voltage IN, EN, IN+, IN–		–10	30	V
Operating junction temperature, T_J		–40	150	°C
Lead temperature	Soldering, 10 s		300	°C
Lead temperature	Reflow		260	°C
Storage temperature, T_stg		–65	150	°C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See Section 6.4 of the data sheet for thermal limitations and considerations of packages.

(3) These devices are sensitive to electrostatic discharge; follow proper device handling procedures.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002⁽²⁾	±1000	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range. All voltages are with reference to GND (unless otherwise noted)

	MIN	NOM	MAX	UNIT
Supply voltage, VDD	4.5	12	26	V
Input voltage, IN, IN+, IN-, EN	–10		26	V
Output Voltage, OUT	0		VDD	V
Operating junction temperature, T_J	–40		150	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		UCC27614	UCC27614	UNIT
		SON (DSG)	SOIC (D)
		8 PINS	8 PINS
R_θJA	Junction-to-ambient thermal resistance	67.9	126.4	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	81.1	67.0
R_θJB	Junction-to-board thermal resistance	33.4	69.9
ψ_JT	Junction-to-top characterization parameter	2.4	19.2
ψ_JB	Junction-to-board characterization parameter	33.4	69.1
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	12.2	n/a

(1) For more information about traditional and new thermal metrics, see Semiconductor and IC Package Thermal Metrics Application Report (SPRA953).

6.5 Electrical Characteristics

Unless otherwise noted, VDD = 12 V, T_A = T_J = –40°C to 150°C, 1-µF capacitor from VDD to GND, No load on the output. Typical condition specifications are at 25°C.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
BIAS CURRENTS
I_VDDq	VDD quiescent supply current	V_IN+/V_IN = 3.3 V, V_IN- = 0 V, EN=VDD, VDD = 3.4 V		305	500	μA
I_VDD	VDD static supply current	V_IN+/V_IN = 3.3 V, V_IN- = 0 V, EN = VDD		0.64	0.92	mA
I_VDD	VDD static supply current	V_IN+/V_IN = 0 V, V_IN- = 0 V, EN = VDD		0.71	1.0	mA
I_VDDO	VDD dynamic operating current	f_SW = 1000 kHz, EN = VDD, V_IN+/V_IN = 0 V to 3.3 V PWM, V_IN- = 0 V			4.0	mA
I_DIS	VDD disable current	V_IN+/V_IN = 0 V, V_IN- = 3.3 V, EN = 0 V		0.75	1.0	mA
UNDERVOLTAGE LOCKOUT (UVLO)
V_{VDD_ON}	VDD UVLO rising threshold		3.8	4.1	4.4	V
V_{VDD_OFF}	VDD UVLO falling threshold		3.5	3.8	4.1	V
V_{VDD_HYS}	VDD UVLO hysteresis			0.3		V
INPUT (IN, IN+)
V_{IN_H}	Input signal high threshold, output high	Output high, IN- = LOW, EN=HIGH	1.8	2	2.3	V
V_{IN_L}	Input signal low threshold, output low	Output low, IN- = LOW, EN=HIGH	0.8	1	1.2	V
V_{IN_HYS}	Input signal hysteresis			1		V
R_IN	INx pin Pulldown resistance	IN+/IN = 3.3 V		120		kΩ
INPUT (IN-)
V_{IN-_H}	Input signal high threshold, output low	Output low, IN+ = HIGH, EN = high	1.8	2	2.3	V
V_{IN-_L}	Input signal low threshold, output high	Output high, IN+ = HIGH, EN = high	0.8	1	1.2	V
V_{IN-_HYS}	Input signal hysteresis			1		V
R_IN-	IN- pin pullup resistance	IN- = 0 V		200		kΩ
ENABLE (EN)
V_{EN_H}	Enable signal high threshold	Output high, IN+/IN = high, IN- =0 V	1.8	2	2.3	V
V_{EN_L}	Enable signal low threshold	Output low, IN+/IN = high, IN- = 0 V	0.8	1	1.2	V
V_{EN_HYS}	Enable signal hysteresis			1		V
R_EN	EN pin pullup resistance	EN = 0 V		200		kΩ
OUTPUT (OUT)
I_SRC⁽¹⁾	Peak output source current	VDD = 12 V, C_VDD = 10 µF, C_L = 0.1 µF, f = 1 kHz		10		A
I_SNK⁽¹⁾	Peak output sink current	VDD = 12 V, C_VDD = 10 µF, C_L = 0.1 µF, f = 1 kHz		–10		A
R_OH⁽²⁾	OUTH, pullup resistance	I_OUT = –50 mA See: Section 7.3.4		2.5	4.5	Ω
R_OL	OUTL, pulldown resistance	I_OUT = 50 mA		0.34	0.55	Ω

(1) Parameter not tested in production.

(2) Output pullup resistance here is a DC measurement that measures resistance of PMOS structure only, not N-channel structure.

6.6 Switching Characteristics

Unless otherwise noted, VDD = V_EN = 12 V, IN- = GND, T_A = T_J = –40°C to 150°C, 1-µF capacitor from VDD to GND, No load on the output. Typical condition specifications are at 25°C ⁽¹⁾

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
t_R	Rise time	C_LOAD = 1.8 nF, 20% to 80%, V_IN = 0 V to 3.3 V	4.5	6	ns
t_F	Fall time	C_LOAD = 1.8 nF, 90% to 10%, V_IN = 0 V to 3.3 V	4	5.5	ns
t_D1	Turnon propagation delay	C_LOAD = 1.8 nF, V_{IN_H} of the input rise to 10% of output rise, V_IN= 0 V to 3.3 V, Fsw=500 kHz, 50% duty cycle, T_J = 125°C	17.5	27	ns
t_D2	Turn-off propagation delay	C_LOAD = 1.8 nF, V_{IN_L} of the input fall to 90% of output fall, V_IN = 0 V to 3.3 V, Fsw=500 kHz, 50% duty cycle, T_J = 125°C	17.5	27	ns
t_{PD_EN}	Enable propagation delay	C_LOAD = 1.8 nF, V_{EN_H} of the enable rise to 10% of output rise, V_IN = 0 V to 3.3 V, Fsw=500 kHz, 50% duty cycle, T_J = 125°C	17.5	27	ns
t_{PD_DIS}	Disable propagation delay	C_LOAD = 1.8 nF, V_{EN_L} of the enable fall to 90% of output fall, V_IN = 0 V to 3.3 V, Fsw = 500 kHz, 50% duty cycle, T_J = 125°C	17.5	27	ns
t_{VDD+_OUT}	VDD UVLO ON delay	VDD = 0 V to 4.5 V in 100 ns. Measured delay from VDD = 4.5 V to 10% of OUT	3.2	6	µs
t_{VDD-_OUT}	VDD UVLO OFF delay	VDD = 4.5 V to 3.4 V in 100 ns. Measured delay from VDD = 3.4 V to 90% of OUT		7.5	us
t_PWmin	Minimum input pulse width that passes to the output	C_LOAD = 1.8 nF, V_IN = 0 V to 3.3 V, Fsw = 500 kHz, Vo > 1.5 V	9	15	ns

(1) Switching parameters are not tested in production.

6.7 Timing Diagrams

Figure 6-1 Single Input Version, IN = PWM

Figure 6-2 Dual Input Version, IN+ = PWM, IN- = GND

Figure 6-3 Dual Input Version, IN- = PWM, IN+ = High (or VDD)

6.8 Typical Characteristics

Unless otherwise specified, VDD = 12 V, IN+ = 3.3 V, IN- = GND, T_J = 25 °C, No load

Figure 6-4 Peak Source Current vs VDD

C_LOAD = 1.8 nF

Figure 6-6 Output Rise Time vs VDD

C_LOAD = 1.8 nF

Figure 6-8 Output Rise and Fall Time vs Temperature

C_LOAD = 1.8 nF

Figure 6-10 Falling (Turnoff) Propagation Delay vs VDD

Figure 6-12 Operating Supply Current vs VDD

Figure 6-14 Input Threshold vs VDD

Figure 6-16 Input Threshold Hysteresis vs Temperature

Figure 6-18 Output Pullup Resistance vs Temperature

Figure 6-20 Output Pulldown Resistance vs Temperature

Figure 6-22 UVLO Hysteresis vs Temperature

Figure 6-5 Peak Sink Current vs VDD

C_LOAD = 1.8 nF

Figure 6-7 Output Fall Time vs VDD

C_LOAD = 1.8 nF

Figure 6-9 Rising (Turnon) Propagation Delay vs VDD

C_LOAD = 1.8 nF

Figure 6-11 Propagation Delay vs Temperature

Figure 6-13 Operating Static Supply Current vs Temperature

Figure 6-15 Input Threshold vs Temperature

Figure 6-17 Output Pullup Resistance vs VDD

Figure 6-19 Output Pulldown Resistance vs VDD

Figure 6-21 UVLO Threshold vs Temperature

7 Detailed Description

7.1 Overview

The UCC27614 device is a single-channel, high-speed, gate drivers capable of effectively driving MOSFET, SiC MOSFET, and IGBT power switches with 10-A source and 10-A sink (symmetrical drive) peak current. A strong source and sink capability boost immunity against a parasitic Miller turnon effect. The UCC27614 device can be directly connected to the gate driver transformer or line driver transformer as the inputs of UCC27614 can handle –10V. The driver has a good transient handling capability on its output due to reverse currents, as well as rail-to-rail drive capability and small propagation delay, typically 17.5 ns.

The input threshold of UCC27614 is compatible to TTL low-voltage logic, which is fixed and independent of VDD supply voltage. The driver can also work with CMOS based controllers as long as the threshold requirement is met. The 1-V typical hysteresis offers excellent noise immunity.

The driver has an EN pin with fixed TTL compatible threshold. EN is internally pulled up; pulling EN low disables the driver, while leaving EN open provides normal operation. The EN pin can be used as an additional input with the same performance as the IN, IN+, and IN- pins.

Table 7-1 UCC27614 Features and Benefits

FEATURE	BENEFIT
–10 V IN and EN capability	Enhanced signal reliability and device robustness in noisy environments that experience ground bounce on the gate driver.
High source and sink current capability, 10 A	High current capability helps drive large gate charge loads to minimize switching losses.
Low 17.5 ns (typ) propagation delay.	Extremely low pulse transmission distortion
Wide VDD operating range of 4.5 V to 26 V	Flexibility in system design
VDD UVLO protection	Outputs are held Low in UVLO condition, which ensures predictable, glitch-free operation at power up and power down.
VDD UVLO protection	UVLO of 4 V (typical) allows use in high switching frequency applications at low bias voltage to reduce switching losses.
Outputs held low when input pin (INx) in floating condition	Safety feature, especially useful in passing abnormal condition tests during safety certification
EN can float	Safe operation when the output of the controller, ties to the EN pin in tristate
Strong sink current (10 A) and low pulldown impedance (0.34 Ω)	High immunity to high dV/dt Miller turnon events
TTL compatible input threshold logic with wide hysteresis	Enhanced noise immunity, while retaining compatibility with microcontroller logic level input signals (3.3 V, 5 V) optimized for digital power

7.2 Functional Block Diagram

Typical

EN/IN- pullup resistance is 200 kΩ and IN/IN+ pulldown resistance is 120 kΩ.

7.3 Feature Description

7.3.1 VDD Undervoltage Lockout

The UCC27614 device offers an undervoltage lockout threshold of 4 V. The device's hysteresis range helps to avoid any chattering due to the presence of noise on the bias supply. 0.3 V of typical UVLO hysteresis is expected for 4-V UVLO devices. There is no significant driver output turnon delay due to the UVLO feature, and 5 μs of UVLO delay is expected. The UVLO turn-off delay is also minimized as much as possible. The UVLO delay is designed to minimize chattering that may occur due to very fast transients that may appear on VDD. When the bias supply is below UVLO thresholds, the outputs are held actively low irrespective of the state of input pins and enable pin. The device accepts a wide range of slew rates on its VDD pin, and VDD noise within the hysteresis range does not affect the output state of the driver (neither ON nor OFF).

Figure 7-1 Power Up