采用小尺寸封装的 TLV751 双通道 500mA 高精度可调节 LDO
- ZHCSKJ1A December 2019 – February 2020 TLV751
  
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采用小尺寸封装的 TLV751 双通道 500mA 高精度可调节 LDO

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1 特性

输入电压范围：1.5V 至 6.0V
输出电压范围：
- 可调节电压范围：0.55V 至 5.5V
- 固定电压范围：0.65V 至 5.0V
低压降：
- 500mA 时为 130mV（最大值）(3.3 V_OUT)
高输出精度：1.5%（温度范围内最大值）
I_Q：25µA（典型值）
内置软启动功能，具有单调 V_OUT 上升
封装：
- 2mm × 2mm WSON-10 (DSQ)
有源输出放电

2 应用

3 说明

TLV751 是一款双通道、可调节的 500mA 低压降 (LDO) 稳压器。该器件采用小型 10 引脚 2mm × 2mm WSON 封装，具有 25µA 的静态电流，同时提供快速的线路和负载瞬态响应。TLV751 具有 130mV 的低压降，有助于提高总功率效率。

TLV751 具有宽输入和输出电压范围以及出色的输出电流能力，当用于小型印刷电路板 (PCB) 上时，可帮助支持各类应用，如传感器电源、辅助电源轨和具有更低内核电压的现代微控制器。

TLV751 可与小型陶瓷输出电容器搭配使用，从而减小整体解决方案尺寸。精密带隙和误差放大器在整个温度范围内具有高精度，最大值为 1.5%。该器件包括集成的热关断、电流限制、有源输出放电和欠压锁定 (UVLO) 功能。TLV751 的内部过流保护限制功能可在发生短路事件时减少热耗散。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
TLV751	WSON (10)	2.00mm × 2.00mm

如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
预览器件。

Device Images

典型应用

4 修订历史记录

Changes from * Revision (December 2019) to A Revision

Changed pins 6, 8, 9, and 10 in Pin Configuration and Functions sectionGo

5 Pin Configuration and Functions

DSQ Package

10-Pin Adjustable WSON

Top View

DSQ Package

10-Pin Adjustable WSON

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NAME	DSQ	I/O	DESCRIPTION
EN1	3	Input	Enable pin. Drive EN1 greater than V_EN1(HI) to turn on the regulator. Drive EN1 less than V_EN1(LO) to put the low-dropout (LDO) regulator into shutdown mode.
EN2	5	Input	Enable pin. Drive EN2 greater than V_EN2(HI) to turn on the regulator. Drive EN2 less than V_EN2(LO) to put the LDO into shutdown mode.
FB1/ NC	1	—	For the adjustable TLV75101, this pin is used as an input to the control loop error amplifier and is used to set the output voltage of the LDO. For the fixed TLV751xxxyyy, this is not connected internally.
FB2 / NC	7	—	For the adjustable TLV75101, this pin is used as an input to the control loop error amplifier and is used to set the output voltage of the LDO. For the fixed TLV751xxxyyy, this is not connected internally.
GND	2, 4	—	Ground pin
IN1	9	Input	Input pin. For best transient response and to minimize input impedance, use the recommended value or larger ceramic capacitor from IN to ground; see the Recommended Operating Conditions table and the Input and Output Capacitor Selection section. Place the input capacitor as close to the output of the device as possible.
IN2	6	Input	Input pin. For best transient response and to minimize input impedance, use the recommended value or larger ceramic capacitor from IN to ground; see the Recommended Operating Conditions table and the Input and Output Capacitor Selection section. Place the input capacitor as close to the output of the device as possible.
OUT1	10	Output	Regulated output voltage pin. A capacitor is required from OUT to ground for stability. For best transient response, use the nominal recommended value or larger ceramic capacitor from OUT to ground; see the Recommended Operating Conditions table and the Input and Output Capacitor Selection section. Place the output capacitor as close to output of the device as possible.
OUT2	8	Output	Regulated output voltage pin. A capacitor is required from OUT to ground for stability. For best transient response, use the nominal recommended value or larger ceramic capacitor from OUT to ground; see the Recommended Operating Conditions table and the Input and Output Capacitor Selection section. Place the output capacitor as close to output of the device as possible.
Thermal pad		—	Connect the thermal pad to a large area GND plane for improved thermal performance.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
Voltage	Supply, V_IN	–0.3	6.5	V
	Enable, V_EN	–0.3	6.5
	Feedback, V_FB	–0.3	2
Voltage	Output, V_OUT	–0.3	V_IN + 0.3⁽²⁾
Temperature	Operating junction, T_J	–40	150	°C
Temperature	Storage, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.

(2) The absolute maximum rating is V_IN + 0.3V or 6.5 V, whichever is smaller.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safemanufacturing with a standard ESD control process. Manufacturing with less than 500-V HBM ispossible with the necessary precautions.

(2) JEDEC document JEP157 states that 250-V CDM allows safemanufacturing with a standard ESD control process. Manufacturing with less than 250-V CDM ispossible with the necessary precautions.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	MAX	UNIT
V_IN	Input voltage	1.5	6.0	V
V_OUT	Output voltage	0.55	5.5	V
I_OUT	Output current	0	500	mA
C_IN	Input capacitor	1		µF
C_OUT	Output capacitor⁽¹⁾	1	220	µF
V_EN	Enable voltage⁽²⁾	0	6.0	V
f_EN	Enable toggle frequency		10	kHz
T_J	Junction temperature	–40	125	°C

(1) Minimum derated capacitance of 0.47 µF is required for stability

(2) If V_EN > V_IN, when V_EN> V_UVLO rising (min), the input pin (IN) must sink 1 mA of current to avoid the device being turn on with floating input pin.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TLV751P	UNIT
		DSQ (WSON)
		10 PINS
R_θJA	Junction-to-ambient thermal resistance	74.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	90.5	°C/W
R_θJB	Junction-to-board thermal resistance	39.7	°C/W
ψ_JT	Junction-to-top characterization parameter	3.8	°C/W
ψ_JB	Junction-to-board characterization parameter	39.7	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	17	°C/W

(1) For more information about traditional and new thermalmetrics, see the Semiconductor and ICPackage Thermal Metrics application report.

6.5 Electrical Characteristics

At operating temperature range (T_J = –40°C to +125°C),V_IN = V_OUT(NOM) + 0.5 V or 1.5 V (whichever isgreater), I_OUT = 1 mA, V_EN =V_IN, and C_IN = C_OUT = 1 uF(unless otherwise noted); all typical values are at T_J = 25°C

PARAMETER		TEST CONDITIONS		MIN	TYP	MAX	UNIT
V_FB	Feedback voltage	T_J = 25°C			0.55		V
	Output accuracy⁽¹⁾	T_J= 25°C		–0.5%		0.5%
	Output accuracy⁽¹⁾	–40°C ≤ T_J ≤ +125°C; V_OUT(NOM) + 0.5 V⁽²⁾ ≤ V_I_N ≤ 6.0 V		–1.5%		1.5%
	Line regulation	V_OUT(NOM) + 0.5 V⁽²⁾ ≤ V_I_N ≤ 6.0 V			2		mV
	Load regulation	0.1 mA ≤ I_OUT ≤ 500 mA, V_IN = V_OUT + 0.5 V⁽³⁾			0.030		V/A
I_GND	Ground current	I_OUT = 0 mA	T_J = 25°C	10	25	31	µA
I_GND	Ground current	I_OUT = 0 mA	–40°C ≤ T_J ≤ +125°C			35	µA
I_SHDN	Shutdown current	V_EN ≤ 0.3 V, 1.5 V ≤ V_IN ≤ 6.0 V			0.1	1	µA
I_FB	Feedback pin current				0.01	0.1	µA
I_CL	Output current limit	V_IN = 2 V with V_OUT < 1 V; otherwise V_IN = V_OUT(NOM) + 1.0 V	V_OUT = V_OUT(NOM) – 0.2 V, V_OUT< 1.5 V	530	720	865	mA
I_CL	Output current limit		V_OUT = 0.9 V × V_OUT(NOM), V_OUT≥ 1.5 V	530	720	865	mA
I_SC	Short-circuit current limit	V_IN = 2 V with V_OUT < 1 V; otherwise V_IN = V_OUT(NOM) + 1.0 V	V_OUT = 0 V		310	400	mA
V_DO	Dropout voltage	I_OUT = 500 mA, –40°C ≤ T_J ≤ +125°C, V_OUT = 0.95 × V_OUT(NOM)	0.65 V ≤ V_OUT < 0.8 V		720	880	mV
			0.8 V ≤ V_OUT < 1.0 V		585	750
			1.0 V ≤ V_OUT < 1.2 V		420	570
			1.2 V ≤ V_OUT < 1.5 V		285	400
			1.5 V ≤ V_OUT < 1.8 V		180	240
			1.8 V ≤ V_OUT < 2.5 V		140	190
			2.5 V ≤ V_OUT < 3.3 V		102	140
			3.3 V ≤ V_OUT ≤ 5.5 V		95	130
PSRR	Power-supply rejection ratio	V_IN = V_OUT(NOM) + 1.0 V, I_OUT = 50 mA	f = 1 kHz		50		dB
			f = 100 kHz		45
			f = 1 MHz		30
V_n	Output noise voltage	BW = 10 Hz to 100 kHz, V_OUT = 0.9 V			53		µV_RMS
V_UVLO	Undervoltage lockout	V_IN rising		1.21	1.33	1.47	V
V_UVLO	Undervoltage lockout	V_IN falling		1.17	1.29	1.42	V
V_{UVLO, HYST}	Undervoltage lockout hysteresis	V_IN hysteresis			45		mV
t_STR	Startup time	From EN low-to-high transition to V_OUT = V_OUT(NOM) × 95%			500	700	µs
V_EN(HI)	EN pin high voltage			1.0			V
V_EN(LO)	EN pin low voltage					0.3	V
I_EN	Enable pin current	V_IN = EN = 6.0 V			10		nA
R_{PULL DOWN}	Pulldown resistance	V_IN = 6.0 V			95		Ω
T_SD	Thermal shutdown	Shutdown, temperature increasing			170		°C
T_SD	Thermal shutdown	Reset, temperature decreasing			155		°C

(1) When the device is connected to external feedback resistors at the FB pin, external resistor tolerances are not included.

(2) V_IN = 1.5 V for V_OUT < 1.0 V.

(3) V_IN = 2.0 V for V_OUT < 1.5 V.

6.6 Typical Characteristics

at operating temperature range T_J = 25°C, V_IN = V_OUT(NOM) + 0.5 V or 1.5 V (whichever is greater), I_OUT = 1 mA, V_EN = V_IN, and C_IN = C_OUT = 1 µF (unless otherwise noted)

V_OUT = 3.3 V, I_OUT = 1 mA

Figure 1. 3.3-V Line Regulation vs V_IN

V_OUT = 5.5 V, I_OUT = 1 mA

Figure 3. 5.5-V Line Regulation vs V_IN

Figure 5. 0.55-V Dropout Voltage vs I_OUT

I_OUT = 500 mA

Figure 7. V_DO vs V_OUT

V_EN = 0 V

Figure 9. I_SHDN vs V_IN

V_IN = 3.8 V, V_OUT = 3.3 V

Figure 11. 3.3-V Load Regulation vs I_OUT

V_IN = 6 V, V_OUT = 5.5 V

Figure 13. 5-V Load Regulation vs I_OUT

Figure 15. V_EN(HI) and V_EN(LO) vs Temperature

Figure 17. 3.3-V Foldback Current Limit vs I_OUT

V_OUT = 3.3 V, I_OUT = 1 mA, V_IN slew rate = 1 V/µs

Figure 19. 3.3-V Line Transient

V_IN = 2 V, V_OUT = 0.55 V, I_OUT slew rate = 1 A/µs

Figure 21. 0.55-V, 1-mA to 500-mA Load Transient

V_IN = 3.8 V, V_OUT = 3.3 V, I_OUT = 1 mA

Figure 23. V_IN Power-Up

V_OUT = 3.3 V, I_OUT = 500 mA, C_OUT = 2.2 µF

Figure 25. PSRR vs Frequency and V_IN

V_OUT = 3.3 V, I_OUT = 250 mA, C_OUT = 2.2 µF

Figure 27. PSRR vs Frequency and V_IN

I_OUT = 500 mA, C_OUT = 2.2 µF

Figure 29. PSRR vs Frequency

V_IN = 3.8 V, V_OUT = 3.3 V, I_OUT = 500 mA

Figure 31. PSRR vs Frequency and C_FF

V_IN = 3.8 V, V_OUT = 3.3 V, C_OUT = 2.2 µF,
V_RMS BW = 10 Hz to 100 kHz

Figure 33. Output Spectral Noise Density vs Frequency

V_IN = 3.8 V, V_OUT = 3.3 V, I_OUT = 100 mA, C_FF = 0 µF,
V_RMS BW = 10 Hz to 100 kHz

Figure 35. Output Spectral Noise Density vs
Frequency and C_OUT

V_OUT = 0.55 V, I_OUT = 1 mA

Figure 2. 0.55-V Line Regulation vs V_IN

Figure 4. 3.3-V Dropout Voltage vs I_OUT

Figure 6. 5.5-V Dropout Voltage vs I_OUT

Figure 8. I_GND vs I_OUT

V_OUT = 3.3 V, I_OUT = 0 mA

Figure 10. I_GND vs V_IN

V_IN = 2 V, V_OUT = 0.55 V

Figure 12. 0.55-V Load Regulation vs I_OUT

Figure 14. V_OUT vs I_OUT Pulldown Resistor

V_EN = 5.5 V

Figure 16. I_EN vs V_IN

V_OUT = 0.55 V, I_OUT = 1 mA, V_IN slew rate = 1 V/µs

Figure 18. 0.55-V Line Transient

V_IN = 3.8 V, V_OUT = 3.3 V, I_OUT slew rate = 1 A/µs

Figure 20. 3.3-V, 1-mA to 500-mA Load Transient

V_IN = 5.5 V, V_OUT = 5 V, I_OUT slew rate = 1 A/µs

Figure 22. 5-V, 1-mA to 500-mA Load Transient

V_IN = 3.8 V, V_OUT = 3.3 V, I_OUT = 1 mA

Figure 24. Startup With EN

V_OUT = 3.3 V, I_OUT = 500 mA, C_OUT = 2.2 µF

Figure 26. PSRR vs Frequency and V_IN

V_OUT = 3.3 V, I_OUT = 250 mA, C_OUT = 2.2 µF

Figure 28. PSRR vs Frequency and V_IN

V_IN = 3.8 V, V_OUT = 3.3 V, I_OUT = 500 mA

Figure 30. PSRR vs Frequency and C_OUT

V_IN = 3.8 V, V_OUT = 3.3 V, C_OUT = 2.2 µF

Figure 32. PSRR vs Frequency and I_LOAD

V_IN = 3.8 V, V_OUT = 3.3 V, I_OUT = 500 mA, C_OUT = 2.2 µF,
V_RMS BW = 10 Hz to 100 kHz

Figure 34. Output Spectral Noise Density vs
Frequency and C_FF

I_OUT = 500 mA, C_OUT = 2.2 µF, V_RMS BW = 10 Hz to 100 kHz

Figure 36. Output Spectral Noise Density vs Frequency

7 Detailed Description

7.1 Overview

The TLV751 low-dropout regulator (LDO) consumes low quiescent current and delivers excellent line and load transient performance. These characteristics, combined with low noise and good PSRR with low dropout voltage, make this device ideal for portable consumer applications.

This regulator offers foldback current limit, shutdown, and thermal protection. The operating junction temperature for this device is –40°C to +125°C.

7.2 Functional Block Diagram

TLV751 FunctionalBlockDiagram_SBVS326_noPG.gif

7.3 Feature Description

7.3.1 Undervoltage Lockout (UVLO)

The TLV751 uses an undervoltage lockout (UVLO) circuit that disables the output until the input voltage is greater than the rising UVLO voltage (V_UVLO). This circuit ensures that the device does not exhibit any unpredictable behavior when the supply voltage is lower than the operational range of the internal circuitry. When V_IN is less than V_UVLO, the output is connected to ground with a pulldown resistor (R_PULLDOWN).