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  • UCC21750 适用于 SiC/IGBT 并具有主动保护、隔离式模拟感应和高 CMTI 的 10A 拉电流/灌电流增强型隔离式单通道栅极驱动器

    • ZHCSKF2C February   2019  – January 2023 UCC21750

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  • UCC21750 适用于 SiC/IGBT 并具有主动保护、隔离式模拟感应和高 CMTI 的 10A 拉电流/灌电流增强型隔离式单通道栅极驱动器
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety Limiting Values
    8. 6.8  Electrical Characteristics
    9. 6.9  Safety-Related Certifications
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay
      1. 7.1.1 Regular Turn-OFF
    2. 7.2 Input Deglitch Filter
    3. 7.3 Active Miller Clamp
      1. 7.3.1 Internal On-chip Active Miller Clamp
    4. 7.4 Undervoltage Lockout (UVLO)
      1. 7.4.1 VCC UVLO
      2. 7.4.2 VDD UVLO
    5. 7.5 Desaturation (DESAT) Protection
      1. 7.5.1 DESAT Protection with Soft Turn-OFF
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  Power Supply
      2. 8.3.2  Driver Stage
      3. 8.3.3  VCC and VDD Undervoltage Lockout (UVLO)
      4. 8.3.4  Active Pulldown
      5. 8.3.5  Short Circuit Clamping
      6. 8.3.6  Internal Active Miller Clamp
      7. 8.3.7  Desaturation (DESAT) Protection
      8. 8.3.8  Soft Turn-Off
      9. 8.3.9  Fault (FLT, Reset, and Enable (RST/EN)
      10. 8.3.10 Isolated Analog to PWM Signal Function
    4. 8.4 Device Functional Modes
  9. 9 Applications and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Input Filters for IN+, IN–, and RST/EN
        2. 9.2.2.2 PWM Interlock of IN+ and IN–
        3. 9.2.2.3 FLT, RDY, and RST/EN Pin Circuitry
        4. 9.2.2.4 RST/EN Pin Control
        5. 9.2.2.5 Turn-On and Turn-Off Gate Resistors
        6. 9.2.2.6 Overcurrent and Short Circuit Protection
        7. 9.2.2.7 Isolated Analog Signal Sensing
          1. 9.2.2.7.1 Isolated Temperature Sensing
          2. 9.2.2.7.2 Isolated DC Bus Voltage Sensing
        8. 9.2.2.8 Higher Output Current Using an External Current Buffer
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Device Support
      1. 12.1.1 第三方产品免责声明
    2. 12.2 Documentation Support
      1. 12.2.1 Related Documentation
    3. 12.3 接收文档更新通知
    4. 12.4 支持资源
    5. 12.5 Trademarks
    6. 12.6 静电放电警告
    7. 12.7 术语表
  13. 13Mechanical, Packaging, and Orderable Information
  14. 重要声明
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DATA SHEET

UCC21750 适用于 SiC/IGBT 并具有主动保护、隔离式模拟感应和高 CMTI 的 10A 拉电流/灌电流增强型隔离式单通道栅极驱动器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 5.7kV RMS 单通道隔离式栅极驱动器
  • 高达 2121Vpk 的 SiC MOSFET 和 IGBT
  • 33V 最大输出驱动电压 (VDD – VEE)
  • ±10A 驱动强度和分离输出
  • 150V/ns 最小 CMTI
  • 具有 200ns 快速响应时间的 DESAT 保护
  • 4A 内部有源米勒钳位
  • 发生故障时的 400mA 软关断
  • 具有 PWM 输出的隔离式模拟传感器
    • 采用 NTC、PTC 或热敏二极管的温度感应
    • 高电压直流链路或相电压
  • 过流警报 FLT 和通过 RST/EN 重置
  • 针对 RST/EN 的快速启用和禁用响应
  • 抑制输入引脚上的 <40ns 噪声瞬态和脉冲
  • RDY 上的 12V VDD UVLO（具有电源正常指示功能）
  • 具有高达 5V 过冲/欠冲瞬态电压抗扰度的输入/输出
  • 130 ns（最大）传播延迟和 30 ns（最大）脉冲/器件间偏移
  • SOIC-16 DW 封装，爬电距离和间隙 > 8mm
  • 工作结温范围：-40°C 至 +150°C
  • 安全相关认证：
    • 符合 DIN EN IEC 60747-17 (VDE 0884-17) 标准的增强型绝缘
    • UL 1577 组件认证计划

2 应用

  • 工业电机驱动
  • 服务器、电信和工业电源
  • 不间断电源 (UPS)
  • 光伏逆变器

3 说明

UCC21750 是一款电隔离单通道栅极驱动器，设计用于直流工作电压高达 2121V 的 SiC MOSFET 和 IGBT，具有先进的保护功能、出色的动态性能和稳健性。UCC21750 具有高达 ±10A 的峰值拉电流和灌电流。

输入侧通过 SiO2 电容隔离技术与输出侧相隔离，支持高达 1.5kVRMS 的工作电压、12.8kVPK 的浪涌抗扰度，隔离层寿命超过 40 年，并提供较低的器件间偏移，共模噪声抗扰度 (CMTI) 大于 150V/ns。

UCC21750 包括先进的保护特性，如快速过流和短路检测、分流电流检测支持、故障报告、有源米勒钳位、输入和输出侧电源 UVLO（用于优化 SiC 和 IGBT 开关行为和稳健性）。可以利用隔离式模拟至 PWM 传感器更轻松地感测温度或电压，从而进一步提高驱动器的多功能性并简化系统设计工作量、尺寸和成本。

器件信息
器件型号 封装(1) 封装尺寸（标称值）
UCC21750 DW SOIC-16 10.3mm × 7.5mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
器件引脚配置
GUID-D6D4F95A-8BC2-4CD1-97E9-B519E7136F9C-low.gif

4 Revision History

Changes from Revision B (December 2019) to Revision C (January 2023)

  • 向特性中添加了安全相关认证Go
  • Added what to do with unused pins to pin functions table.Go
  • Changed recommended value of decoupling capacitors. Go
  • Added recommended decoupling capacitor layout placement. Go
  • Changed test conditions per DIN EN IEC 60747-17 (VDE 0884-17) Go
  • Changed Ichg lower limit to 430uAGo
  • Changed VAin lower limit to 0.6VGo
  • Changed direction of ICLMPI in VCLP-CLMPI test conditionGo
  • Added test condition for soft turn-off currentGo
  • Deleted short circuit clamping max conditionGo
  • Deleted VDESATL Go
  • Changed from 150ns to 120ns Go
  • Changed from 150ns to 148nsGo
  • Deleted 9600 V from Value column in the VIOTM rowGo
  • Changed VDE and UL to certifiedGo
  • Changed DESAT figureGo
  • Changed DESAT soft turn-off figureGo
  • Added function state showing gate driver turning on. Changed RDY condition when VCC is PD. Go
  • Added Section 9.2.3 Go

Changes from Revision A (May 2019) to Revision B (December 2019)

  • 将销售状态从“预告信息”更改为“量产数据”。Go
  • Deleted test voltage, 9600V, from value columnGo

5 Pin Configuration and Functions

GUID-D6D4F95A-8BC2-4CD1-97E9-B519E7136F9C-low.gif Figure 5-1 UCC21750 DW SOIC (16) Top View
Table 5-1 Pin Functions
PIN I/O(1) DESCRIPTION
NAME NO.
AIN 1 I Isolated analog sensing input, parallel a small capacitor to COM for better noise immunity. Tie to COM if unused.
DESAT 2 I Desaturation current protection input. Tie to COM if unused.
COM 3 P Common ground reference, connecting to emitter pin for IGBT and source pin for SiC-MOSFET.
OUTH 4 O Gate driver output pullup
VDD 5 P Positive supply rail for gate drive voltage. Bypass with a >10-μF capacitor to COM to support specified gate driver source peak current capability. Place decoupling capacitor close to the pin.
OUTL 6 O Gate driver output pull down
CLMPI 7 I Internal active miller clamp, connecting this pin directly to the gate of the power transistor. Leave floating or tie to VEE if unused.
VEE 8 P Negative supply rail for gate drive voltage. Bypass with a >10-μF capacitor to COM to support specified gate driver sink peak current capability. Place decoupling capacitor close to the pin.
GND 9 P Input power supply and logic ground reference.
IN+ 10 I Non-inverting gate driver control input. Tie to VCC if unused.
IN– 11 I Inverting gate driver control input. Tie to GND if unused.
RDY 12 O Power good for VCC-GND and VDD-COM. RDY is open drain configuration and can be paralleled with other RDY signals.
FLT 13 O Active low fault alarm output upon over current or short circuit. FLT is in open drain configuration and can be paralleled with other faults.
RST/EN 14 I The RST/EN serves two purposes:
1) Enable / shutdown of the output side. The FET is turned off by a regular turn-off, if terminal EN is set to low;
2) Resets the DESAT condition signaled on FLT pin. if terminal RST/EN is set to low for more than 1000ns. A reset of signal FLT is asserted at the rising edge of terminal RST/EN.
For automatic RESET function, this pin only serves as an EN pin. Enable / shutdown of the output side. The FET is turned off by a regular turn-off, if terminal EN is set to low.
VCC 15 P Input power supply from 3 V to 5.5 V. Bypass with a >1-μF capacitor to GND. Place decoupling capacitor close to the pin.
APWM 16 O Isolated analog sensing PWM output. Leave floating if unused.
(1) P = Power, G = Ground, I = Input, O = Output

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
PARAMETERMINMAXUNIT
VCCVCC – GND–0.36V
VDDVDD – COM–0.336V
VEEVEE – COM–17.50.3V
VMAXVDD – VEE–0.336V
IN+, IN–, RST/ENDCGND–0.3VCCV
Transient, less than 100 ns(2)GND–5.0VCC+5.0V
DESATReference to COMCOM–0.3VDD+0.3V
AINReference to COM–0.35V
OUTH, OUTL , CLMPIDCVEE–0.3VDDV
Transient, less than 100 ns(2)VEE–5.0VDD+5.0V
RDY, FLT, APWMGND–0.3VCCV
IFLT, IRDYFLT, and RDY pin input current20mA
IAPWMAPWM pin output current20mA
TJJunction temperature range–40150°C
TstgStorage temperature range–65150°C
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) Values are verified by characterization on bench.

6.2 ESD Ratings

VALUEUNIT
V(ESD)Electrostatic dischargeHuman-body model (HBM), per AEC Q100-002(1) ±4000V
Charged-device model (CDM), per AEC Q100-011 ±1500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

 
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