DATA SHEET
具有超低 IQ 的 TPSM265R1 65V 输入、100mA 电源模块
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1 特性
- 3V 至 65V 的宽输入电压范围
- 输出电压选项：
- 可调节电压：1.223V 至 15V
- 固定电压：3.3V 或 5V
- 100mA 输出电流
- 10.5µA 静态电流
- ±1% 内部电压基准
- PFM 运行模式
- –40°C 至 125°C 的环境温度范围
- 可实现低 EMI 的有效压摆率控制
- 符合 CISPR11 (EN55011) EMI 标准
- 单调启动至预偏置输出
- 电源正常状态标志
- 具有迟滞功能的精密使能和输入 UVLO
- 具有迟滞功能的热关断保护
- 2.8mm x 3.7mm x 1.9mm 封装
- 使用 WEBENCH® Power Designer 并借助 TPSM265R1 创建定制稳压器设计
2 应用
3 说明
TPSM265R1 是一款紧凑、易用的模块，其运行时具有宽输入电压范围，最大连续输入电压高达 65V。该模块完全集成了一个控制器、多个 MOSFET 和一个输出电感器。该模块设计用于在小型 PCB 封装中快速、简便地实施电源设计。此模块具有 3.3V 和 5V 两种固定输出电压选项，和一个 1.223V 至 15V 的可调节输出电压选项。每种选项的负载电流额定值均为 100mA。TPSM265R1 在脉冲频率调制 (PFM) 模式下运行，从而提高了轻载条件下的效率。其控制方案无需环路补偿，并可提供出色的线路和负载瞬态响应。
虽然 TPSM265R1 采用简易的小尺寸设计，但其可提供多种功能。精密使能端、可调 UVLO 和迟滞功能可满足特定的上电和断电要求。可选/可调的启动时序选项包括最短延迟（无软启动）、内部固定值 (900µs) 以及可使用电容器进行外部编程的软启动。可以使用开漏 PGOOD 指示器进行排序和输出电压监控。其超小型 2.8mm × 3.7mm × 1.9mm 封装非常适合空间受限型应用。
器件信息
| 器件型号(1) | 输出 | 封装 |
|---|---|---|
| TPSM265R1 | 1.223V 至 15V | uSiP |
| TPSM265R1V3 | 3.3V | |
| TPSM265R1V5 | 5V |
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
典型原理图（固定输出）
典型效率 (VOUT = 15V)5 Pin Configuration and Functions
Figure 5-1 10-Pin uSiP Exposed Thermal PadSIL-10C
Package(Top View)Table 5-1 Pin Functions
| PIN | TYPE(1) | DESCRIPTION | |
|---|---|---|---|
| NO. | NAME | ||
| 1 | VOUT | O | Output voltage pin. The VOUT pin is connected to the internal output inductor. Connect the VOUT pin to an external output capacitor and the output load. The output capacitor connections must be made as close as possible to the VOUT and GND pin 11 of the module. See Section 10.2. |
| 2 | SS | I | Soft-start programming pin. If the SS pin is floating, the output voltage ramp up time is approximately 1 ms after the device is enabled by the EN pin. If a 100-kΩ resistor is placed from the SS pin to GND, the internal soft start is disabled and the output voltage ramps up immediately after the device is enabled with the EN pin. Other output voltage ramp up times can be obtained by connecting an appropriate capacitance from the SS pin to GND. |
| 3, 6, 11 | GND | G | Ground pins. Connect all GND pins to the system ground plane. Pin 3 is not connected to GND internal to the module. Connect pin 3 directly to pin 11 on the host PCB. See Section 10.2. |
| 4, 5 | VIN | I | Input supply pins. The VIN pins are connected to the internal controller and power MOSFETs. Connect the VIN pins to an external input capacitor and the input power source. The input capacitor connections must be made as close as possible to the VIN pins and GND pin 6 of the module. See Section 10.2. |
| 7 | HYS | O | Enable hysteresis pin. The open-drain HYS pin can be used along with external resistors to program the hysteresis of a user-defined UVLO using the EN pin. HYS is internally pulled to GND when EN is below its turnon threshold and HYS goes open drain when EN is above its turnon threshold. |
| 8 | SENSE+/FB | I | Output voltage feedback pin. For fixed output voltage options, the SENSE+ pin must be externally connected to VOUT. For the adjustable output voltage option, the FB pin must be connected to an external resistor divider that is connected between VOUT and GND. |
| 9 | EN | I | Enable pin. The module is enabled when the EN pin is pulled high and disabled when the EN pin is pulled low. An external resistor divider can be connected to the EN pin to act as an external UVLO. |
| 10 | PGOOD | O | Power Good pin. The open-drain PGOOD pin is pulled low when the SENSE+ or FB pin is below the VOUT regulation target. An external 10-kΩ to 100-kΩ pullup resistor can be used to pull the PGOOD pin high when VOUT meets the regulation target. |
(1) G = Ground, I = Input, O = Output
6 Specifications
6.1 Absolute Maximum Ratings
Over operating junction temperature range (unless otherwise noted) (1)
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| Input voltage | VIN, EN | –0.3 | 68 | V |
| SENSE+, PGOOD | –0.3 | 16 | V | |
| HYS | –0.3 | 7 | V | |
| FB, SS | –0.3 | 3.6 | V | |
| Output voltage | VOUT | –0.3 | 16 | V |
| Operating junction temperature, TJ | –40 | 125 | °C | |
| Storage temperature, Tstg | –55 | 150 | °C | |
| Peak reflow case temperature | 260 | °C | ||
| Maximum number of reflows allowed | 3 | |||
| Mechanical shock | Mil-STD-883D, Method 2002.3, 1 msec, 1/2 sine, mounted | 1500 | G | |
| Mechanical vibration | Mil-STD-883D, Method 2007.2, 20 to 2000 Hz | 20 | G | |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
6.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2500 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±1000 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
Over operating ambient temperature range (unless otherwise noted)
| MIN | NOM | MAX | UNIT | |||
|---|---|---|---|---|---|---|
| Input voltage | VIN | 3(1) | 65 | V | ||
| PGOOD | 12 | V | ||||
| HYS | 5 | V | ||||
| Output voltage | VOUT | Adjustable option | 1.223 | 15 | V | |
| Fixed 5 V option | 5 | V | ||||
| Fixed 3.3 V option | 3.3 | V | ||||
| Output current | Iout | 100 | mA | |||
| TA | Operating ambient temperature | –40 | 125 | °C | ||
| CIN | Input capacitance | Ceramic | 1(2) | µF | ||
| COUT | Output capacitance | Ceramic | 10(3) | µF | ||
(1) The minimum input voltage is 3.0 V or (VOUT + 1 V), whichever is greater.
(2) See Section 8.2.2.3 of the data sheet for more information.
(3) See Section 7.3.3 of the data sheet for more information.
6.4 Thermal Information
| THERMAL METRIC(1) | TPSM265R1 | UNIT | |
|---|---|---|---|
| SIL-10C | |||
| 10 PINS | |||
| RθJA | Junction-to-ambient thermal resistance | 49.7 | °C/W |
| ψJT | Junction-to-top characterization parameter | 2.3 | °C/W |
| ψJB | Junction-to-board characterization parameter | 28.7 | °C/W |
(1) For more information about traditional and new thermal
metrics, see the Semiconductor and IC Package Thermal Metrics Application
Report.
6.5 Electrical Characteristics
Limits apply over TA = –40°C to +125°C, VIN = 12 V,
VOUT = 5 V, (unless otherwise noted); CIN1 = 1 µF,
100-V, 1206 ceramic, CIN2 = 33 µF, 100-V, electrolytic (optional),
and COUT = 47 µF, 16-V, 1210 ceramic. Minimum and maximum limits are
specified through production test or by design. Typical values represent the
most likely parametric norm and are provided for reference only.
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | ||
|---|---|---|---|---|---|---|---|
| SUPPLY VOLTAGE | |||||||
| VIN | Input supply voltage range | Over IOUT range | 3(1) | 65 | V | ||
| UVLO | VIN UVLO rising threshold | VIN rising | 2.60 | 2.75 | 2.95 | V | |
| VIN UVLO falling threshold | VIN falling | 2.35 | 2.45 | 2.60 | V | ||
| IQ(VIN) | VIN operating non-switching supply current | VFB = 1.5 V, TA = 25°C | 10.5 | 15 | µA | ||
| ISD(VIN) | VIN shutdown supply current | VEN = 0 V, TA = 25°C | 4.6 | 6.0 | µA | ||
| ENABLE | |||||||
| VEN(rise) | EN voltage rising threshold | EN voltage rising | 1.163 | 1.212 | 1.262 | V | |
| VEN(fall) | EN voltage falling threshold | EN voltage falling | 1.109 | 1.144 | 1.178 | V | |
| VEN(hyst) | EN voltage hysteresis | 68 | mV | ||||
| VEN(sd) | EN shutdown threshold | EN voltage falling | 0.3 | 0.6 | V | ||
| RHYS | HYS on-resistance | VEN = 1 V | 80 | 200 | Ω | ||
| IHYS(LKG) | HYS off-state leakage current | VEN = 1.5 V, VHYS = 5.5 V | 10 | 100 | nA | ||
| FEEDBACK (Adjustable option) | |||||||
| VFB | Feedback voltage(2)(4) | Lower regulation threshold | 1.205 | 1.223 | 1.241 | V | |
| Upper regulation threshold | 1.220 | 1.233 | 1.246 | V | |||
| Hysteresis | 10 | mV | |||||
| Line regulation | Over VIN range, TA = 25°C, IOUT = 0 A | 0.3% | |||||
| Load regulation | Over IOUT range, TA = 25°C | 0.3% | |||||
| Temperature variation | -40°C ≤ TA = TJ ≤ 125°C, IOUT = 0 A | 0.5% | |||||
| IFB | Input bias current into FB pin | VFB = 1 V | 100 | nA | |||
| OUTPUT VOLTAGE (Fixed 5 V option) | |||||||
| VOUT | Output voltage set-point | SENSE+ connected to VOUT | 4.9 | 5.0 | 5.1 | V | |
| Line regulation | Over VIN range, TA = 25°C, IOUT = 0 A | 0.3% | |||||
| Load regulation | Over IOUT range, TA = 25°C | 0.3% | |||||
| Temperature variation | -40°C ≤ TA = TJ ≤ 125°C, IOUT = 0 A | 0.5% | |||||
| ISENSE+ | SENSE+ input current | 6.7 | µA | ||||
| eff | Efficiency | VOUT = 5.0 V, IOUT = 50 mA | 83.0% | ||||
| OUTPUT VOLTAGE (Fixed 3.3 V option) | |||||||
| VOUT | Output voltage set-point | SENSE+ connected to VOUT | 3.23 | 3.3 | 3.37 | V | |
| Line regulation | Over VIN range, TA = 25°C, IOUT = 0 A | 0.3% | |||||
| Load regulation | Over IOUT range, TA = 25°C | 0.3% | |||||
| Temperature variation | -40°C ≤ TA = TJ ≤ 125°C, IOUT = 0 A | 0.5% | |||||
| ISENSE+ | SENSE+ input current | 3.9 | µA | ||||
| eff | Efficiency | VOUT = 3.3 V, IOUT = 50 mA | 77.2% | ||||
| CURRENT | |||||||
| IOUT | Output current | See SOA curves for any thermal derating | 0 | 100 | mA | ||
| IOCL | Overcurrent limit threshold | VOUT foldback | 130 | mA | |||
| SOFT-START | |||||||
| ISS | Soft-start charge current | VSS = 1 V | 10 | µA | |||
| TSS | Soft-start rise time | SS pin open | 900 | µs | |||
| POWER GOOD | |||||||
| PGOOD | PGOOD threshold | PGOOD high, VOUT rising | 94% | ||||
| PGOOD | PGOOD threshold | PGOOD low, VOUT falling | 87% | ||||
| IPGOOD(LKG) | PGOOD leakage current | VPGOOD = 5.5 V, PGOOD high | 10 | 100 | nA | ||
| RPGOOD | PGOOD ON-resistance | PGOOD low | 80 | 200 | Ω | ||
| Min VIN for valid PGOOD output | IPGOOD = 0.1 mA, VPGOOD < 0.5 V | 1.2 | 1.65 | V | |||
| THERMAL SHUTDOWN | |||||||
| TSDN | Thermal shutdown threshold (3) | Temperature rising | 170 | °C | |||
| THYST | Thermal shutdown hysteresis (3) | 10 | °C | ||||
(1) The recommended minimum input voltage is 3.0 V or
(VOUT + 1 V), whichever is greater.
(2) The FB pin has both lower and upper thresholds associated with
the hysteretic control scheme of the module.
(3) Specified by design. Not production tested.
(4) The overall output voltage tolerance will be affected by the
tolerance of the external RFBT and RFBB resistors.
6.6 Typical Characteristics (VIN = 5 V)
Refer to Section 8.2 for circuit designs. TA = 25°C unless otherwise noted.
Figure 6-1 Efficiency
| Applies to a device soldered to a 50-mm × 75-mm, 4-layer PCB |
Figure 6-2 Efficiency Log Scale
| COUT = 47 µF, 16-V, ceramic |
6.7 Typical Characteristics (VIN = 12 V)
Refer to Section 8.2 for circuit designs. TA = 25°C unless otherwise noted.
Figure 6-6 Efficiency
| Applies to a device soldered to a 50-mm × 75-mm, 4-layer PCB |
Figure 6-7 Efficiency Log Scale
| COUT = 47 µF, 16-V, ceramic |
6.8 Typical Characteristics (VIN = 24 V)
Refer to the Section 8.2 for circuit designs. TA = 25°C unless otherwise noted.
Figure 6-11 Efficiency
| Applies to a device soldered to a 50 mm × 75 mm, 4-layer PCB |
Figure 6-12 Efficiency Log Scale
| COUT = 47 µF, 16-V, ceramic |
6.9 Typical Characteristics (VIN = 48 V)
Refer to Section 8.2 for circuit designs. TA = 25°C unless otherwise noted.
Figure 6-16 Efficiency
| Applies to a device soldered to a 50-mm × 75-mm, 4-layer PCB |
Figure 6-17 Efficiency Log Scale
| COUT = 47 µF, 16-V, ceramic |
6.10 Typical Characteristics (VIN = 65 V)
Refer to Section 8.2 for circuit designs. TA = 25°C unless otherwise noted.
Figure 6-21 Efficiency
| Applies to a device soldered to a 50-mm × 75-mm, 4-layer PCB |
Figure 6-22 Efficiency Log Scale
| COUT = 47 µF, 16-V, ceramic |
7 Detailed Description
7.1 Overview
The TPSM265R1 converter is an easy-to-use, synchronous buck, DC-DC power module that operates from a 3-V to 65-V supply voltage. The device is intended for step-down conversions from 3.3-V, 5-V, 12-V, 24-V, and 48-V unregulated, semi-regulated, or fully-regulated supply rails. With integrated power controller, inductor, and MOSFETs, the TPSM265R1 delivers up to 100-mA DC load current, with high efficiency and ultra-low input quiescent current, in a very small solution size. Although designed for simple implementation, this device offers flexibility to optimize its usage according to the target application. Operation in pulse frequency modulation (PFM) mode achieves exceptional light-load efficiency performance. Control-loop compensation is not required, reducing design time and external component count.
The TPSM265R1 incorporates several features for comprehensive system requirements, including an open-drain Power Good circuit for power-rail sequencing and fault reporting, internally-fixed, or externally-adjustable soft start, monotonic start-up into prebiased loads, precision enable with customizable hysteresis for programmable line undervoltage lockout (UVLO), and thermal shutdown with automatic recovery. These features enable a flexible and easy-to-use platform for a wide range of applications. The pin arrangement is designed for simple layout, requiring as few as two external components.
7.2 Functional Block Diagram
