• 3V 至 65V 的宽输入电压范围
• 输出电压选项：
  • 可调节电压：1.223V 至 15V
  • 固定电压：3.3V 或 5V
• 100mA 输出电流
• 10.5µA 静态电流
• ±1% 内部电压基准
• PFM 运行模式
• –40°C 至 125°C 的环境温度范围
• 可实现低 EMI 的有效压摆率控制
• 符合 CISPR11 (EN55011) EMI 标准
• 单调启动至预偏置输出
• 电源正常状态标志
• 具有迟滞功能的精密使能和输入 UVLO
• 具有迟滞功能的热关断保护
• 2.8mm x 3.7mm x 1.9mm 封装
• 使用 WEBENCH® Power Designer 并借助 TPSM265R1 创建定制稳压器设计

• 现场发送器和过程传感器
• 位置 和 接近传感器
• PLC、DCS 和 PAC
• 伺服驱动器电源模块
• 负输出应用

Refer to Section 8.2 for circuit designs. T_A = 25°C unless otherwise noted.

Figure 6-1 Efficiency

Figure 6-3 Power Dissipation

Applies to a device soldered to a 50-mm × 75-mm, 4-layer PCB

Figure 6-5 Safe Operating Area

Figure 6-2 Efficiency Log Scale

COUT = 47 µF, 16-V, ceramic

Figure 6-4 Output Voltage Ripple

Refer to Section 8.2 for circuit designs. T_A = 25°C unless otherwise noted.

Figure 6-6 Efficiency

Figure 6-8 Power Dissipation

Applies to a device soldered to a 50-mm × 75-mm, 4-layer PCB

Figure 6-10 Safe Operating Area

Figure 6-7 Efficiency Log Scale

COUT = 47 µF, 16-V, ceramic

Figure 6-9 Output Voltage Ripple

Refer to the Section 8.2 for circuit designs. T_A = 25°C unless otherwise noted.

Figure 6-11 Efficiency

Figure 6-13 Power Dissipation

Applies to a device soldered to a 50 mm × 75 mm, 4-layer PCB

Figure 6-15 Safe Operating Area

Figure 6-12 Efficiency Log Scale

COUT = 47 µF, 16-V, ceramic

Figure 6-14 Output Voltage Ripple

Refer to Section 8.2 for circuit designs. T_A = 25°C unless otherwise noted.

Figure 6-16 Efficiency

Figure 6-18 Power Dissipation

Applies to a device soldered to a 50-mm × 75-mm, 4-layer PCB

Figure 6-20 Safe Operating Area

Figure 6-17 Efficiency Log Scale

COUT = 47 µF, 16-V, ceramic

Figure 6-19 Output Voltage Ripple

Refer to Section 8.2 for circuit designs. T_A = 25°C unless otherwise noted.

Figure 6-21 Efficiency

Figure 6-23 Power Dissipation

Applies to a device soldered to a 50-mm × 75-mm, 4-layer PCB

Figure 6-25 Safe Operating Area

Figure 6-22 Efficiency Log Scale

COUT = 47 µF, 16-V, ceramic

Figure 6-24 Output Voltage Ripple

The TPSM265R1 converter is an easy-to-use, synchronous buck, DC-DC power module that operates from a 3-V to 65-V supply voltage. The device is intended for step-down conversions from 3.3-V, 5-V, 12-V, 24-V, and 48-V unregulated, semi-regulated, or fully-regulated supply rails. With integrated power controller, inductor, and MOSFETs, the TPSM265R1 delivers up to 100-mA DC load current, with high efficiency and ultra-low input quiescent current, in a very small solution size. Although designed for simple implementation, this device offers flexibility to optimize its usage according to the target application. Operation in pulse frequency modulation (PFM) mode achieves exceptional light-load efficiency performance. Control-loop compensation is not required, reducing design time and external component count.

The TPSM265R1 incorporates several features for comprehensive system requirements, including an open-drain Power Good circuit for power-rail sequencing and fault reporting, internally-fixed, or externally-adjustable soft start, monotonic start-up into prebiased loads, precision enable with customizable hysteresis for programmable line undervoltage lockout (UVLO), and thermal shutdown with automatic recovery. These features enable a flexible and easy-to-use platform for a wide range of applications. The pin arrangement is designed for simple layout, requiring as few as two external components.

The TPSM265R1 has three voltage feedback options: fixed 3.3 V, fixed 5 V, and adjustable 1.223 V to 15 V. The fixed 3.3-V and 5-V versions include internal feedback resistors that sense the output directly through the SENSE+ pin; the adjustable voltage option senses the output through an external resistor divider connected from the output to the FB pin.

Setting the output voltage of the adjustable option requires two resistors: R_FBT and R_FBB (see Figure 7-1). Connect R_FBT between VOUT, at the regulation point, and the FB pin. Connect R_FBB between the FB pin and GND (pin 6). A resistor divider programs the ratio from output voltage V_OUT to FB. The recommended value of R_FBT is 100 kΩ. The value for R_FBB can be calculated using Equation 1.

Equation 1.

Figure 7-1 FB Resistor Divider

Selecting an R_FBT value of 100 kΩ is recommended for most applications. A larger R_FBT consumes less DC current, which is mandatory if light-load efficiency, is critical. However, R_FBT larger than 1 MΩ is not recommended as the feedback path becomes more susceptible to noise. High feedback resistance generally requires more careful layout of the feedback path. It is important to keep the feedback trace as short as possible while keeping the feedback trace away from the noisy area of the PCB. For more layout recommendations, see Section 10.

The TPSM265R1 requires a minimum of 1 µF of ceramic type input capacitance. Use only high-quality ceramic type X5R or X7R capacitors with sufficient voltage rating. TI recommends adding additional capacitance for applications with transient load requirements. The voltage rating of input capacitors must be greater than the maximum input voltage. To compensate for the derating of ceramic capacitors, TI recommends a voltage rating of twice the maximum input voltage or placing multiple capacitors in parallel. Table 7-2 includes a preferred list of capacitors by vendor.

The minimum amount of required output capacitance for the TPSM265R1 is 10 µF of ceramic type. TI recommends adding additional capacitance for applications with transient load requirements. See Table 7-3 for a preferred list of output capacitors by vendor.

The EN pin provides precision ON and OFF control for the TPSM265R1. Once the EN pin voltage exceeds the threshold voltage, the device starts operation. The simplest way to enable the TPSM265R1 is to connect EN directly to VIN. This allows the TPSM265R1 to start up when VIN is within its valid operating range. An external logic signal can also be used to drive the EN input to toggle the output on and off and for system sequencing or protection.

The TPSM265R1 implements internal undervoltage lockout (UVLO) circuitry on the VIN pin. The device is disabled when the VIN pin voltage is below the internal VIN UVLO threshold. The internal VIN UVLO rising threshold is 2.95 V (max) with a typical hysteresis of 300 mV.

If an application requires a higher UVLO threshold, the EN input supports adjustable UVLO by connecting a resistor divider from VIN to the EN pin. The EN pin connects to an internal comparator referenced to a 1.212-V bandgap voltage with 68-mV hysteresis. However, applications requiring specific power-up and power-down requirements can program the hysteresis voltage independently using the HYS pin. Figure 7-2 shows the resistor divider connection to establish a precision UVLO level with fixed internal hysteresis. Figure 7-3 shows the resistor divider connection used to set the precision UVLO level as well as the adjustable hysteresis.

Figure 7-2 Programmable V_IN UVLO with Fixed Hysteresis

Figure 7-3 Programmable V_IN UVLO with Adjustable Hysteresis

Use Equation 2 and Equation 3 to calculate the input UVLO voltages turnon and turnoff voltages, respectively.

Equation 2.

Equation 3.

There is also a low I_Q shutdown mode when EN is pulled below 0.6 V (typ). If EN is below this shutdown threshold, the internal LDO regulator powers off, shutting down the bias currents of the TPSM265R1. The TPSM265R1 operates in standby mode when the EN voltage is between the shutdown and precision enable thresholds.

The TPSM265R1 operates in Pulse Frequency Modulation (PFM) mode. The TPSM265R1 behaves as a hysteretic voltage regulator operating within upper and lower feedback regulation thresholds with typical 10 mV of hysteresis. Figure 7-4 is a representation of the relevant voltage waveforms and inductor current waveform. The TPSM265R1 provides the required switching pulses to recharge the output capacitance, followed by a sleep period where most of the internal circuits are shut off. The load current is supported by the output capacitor during this time, and the TPSM265R1 current consumption approaches the sleep quiescent current of 10.5 μA (typ). The sleep period duration depends on load current and output capacitance.

Figure 7-4 PFM Mode SW Node Voltage, Feedback Voltage, and Inductor Current Waveforms

The TPSM265R1 provides a PGOOD signal to indicate when the output voltage is within regulation. Use the PGOOD signal for output monitoring, fault protection, or start-up sequencing of downstream converters. PGOOD is an open-drain output that requires a pullup resistor to a DC supply not greater than 12 V. Typical range of pullup resistance is 10 kΩ to 100 kΩ. If necessary, use a resistor divider to decrease the voltage from a higher voltage pullup rail.

When the output voltage exceeds 94% of the setpoint, the internal PGOOD switch turns off and PGOOD can be pulled high by the external pullup. If the FB voltage falls below 87% of the setpoint, the internal PGOOD switch turns on, and PGOOD is pulled low to indicate that the output voltage is out of regulation. The rising edge of PGOOD has a built-in deglitch delay of 5 µs.

The TPSM265R1 has a flexible and easy-to-use soft-start control pin, SS. The soft-start feature prevents inrush current when power is first applied. Soft start is achieved by slowly ramping up the target regulation voltage when the device is powered up or enabled. Selectable and adjustable start-up timing options include minimum delay (no soft start), 900-µs internally fixed soft start, and an externally programmable soft start.

Leaving the SS pin open enables the internal soft-start control ramp with a soft-start interval of 900 µs. The soft-start time can be increased by connecting an external capacitor, C_SS, from SS to GND. Applications with a large amount of output capacitance or higher output voltage can benefit from increasing the soft-start time. Longer soft-start time reduces the supply current needed to charge the output capacitors and supply any output loading. An internal current source, I_SS, of 10 µA charges C_SS and generates a ramp to control the ramp rate of the output voltage. Use Equation 4 to calculate the C_SS capacitance for a desired soft-start time, t_SS.

Equation 4.

C_SS is discharged by an internal FET when V_OUT is shut down by EN, UVLO, or thermal shutdown.

It is desirable in some applications for the output voltage to reach its nominal setpoint in the shortest possible time. Connecting a 100-kΩ resistor from SS to GND disables the soft-start circuit, and the TPSM265R1 operates in current limit during start-up to rapidly charge the output capacitance.

To prevent discharge of a prebiased output voltage, the TPSM265R1 is capable of start-up into prebiased output conditions. When a prebiased voltage is present at start-up, the TPSM265R1 waits until the soft-start ramp voltage is above the prebiased voltage before it begins switching and then follows the soft-start ramp to the regulation setpoint.

The TPSM265R1 is protected from overcurrent conditions using cycle-by-cycle current limiting of the peak inductor current. The current is compared every switching cycle to the current limit threshold. During an overcurrent condition, the output voltage decreases.

Thermal shutdown is an integrated self-protection used to limit junction temperature and prevent damage related to overheating. Thermal shutdown turns off the device when the junction temperature exceeds 170°C (typ) to prevent further power dissipation and temperature rise. Junction temperature decreases after shutdown, and the TPSM265R1 restarts when the junction temperature falls to 160°C (typ).

The EN pin provides ON and OFF control for the TPSM265R1. When V_EN is below approximately 0.6 V, the device is in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in shutdown mode drops to 4.6 µA at V_IN = 12 V. The TPSM265R1 also employs internal bias rail undervoltage protection. If the internal bias supply voltage is below its UV threshold, the regulator remains off.

The internal bias rail LDO has a lower enable threshold than the regulator itself. When V_EN is above 0.6 V and below the precision enable threshold (1.212 V typically), the internal LDO is on and regulating. The precision enable circuitry is turned on once the internal V_CC is above its UV threshold. The switching action and voltage regulation are not enabled until V_EN rises above the precision enable threshold.

The TPSM265R1 is in active mode when V_EN and the internal bias rail are above their relevant thresholds, FB has fallen below the lower hysteresis level, and boundary conduction mode is recharging the output capacitor to the upper hysteresis level. There is a 4-µs wake-up delay from sleep to active states.

The TPSM265R1 is in sleep mode when V_EN and the internal bias rail are above the relevant threshold levels, V_FB has exceeded the upper hysteresis level, and the output capacitor is sourcing the load current. In sleep mode, the TPSM265R1 operates with very low quiescent current.