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  • 具有电压前馈功能的 TPS40077 4.5V 至 28V 输入、电压模式、同步降压控制器

    • ZHCSJU9E January   2007  – June 2019 TPS40077

      PRODUCTION DATA.  

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  • 具有电压前馈功能的 TPS40077 4.5V 至 28V 输入、电压模式、同步降压控制器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化应用示意图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Electrical Characteristics
    5. 6.5 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Minimum Pulse Duration
      2. 7.3.2  Slew Rate Limit On VDD
      3. 7.3.3  Setting The Switching Frequency (Programming The Clock Oscillator)
      4. 7.3.4  Loop Compensation
      5. 7.3.5  Shutdown and Sequencing
      6. 7.3.6  Boost and LVBP Bypass Capacitance
      7. 7.3.7  Internal Regulators
      8. 7.3.8  Power Dissipation
      9. 7.3.9  Boost Diode
      10. 7.3.10 Synchronous Rectifier Control
    4. 7.4 Programming
      1. 7.4.1 Programming The Ramp Generator Circuit and UVLO
      2. 7.4.2 Programming Soft Start
      3. 7.4.3 Programming Short-Circuit Protection
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Buck Regulator 8-V to 16-V Input, 1.8-V Output at 10 A
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Power Train Components
            1. 8.2.1.2.1.1  Output Inductor, LOUT
            2. 8.2.1.2.1.2  Output Capacitor, COUT, ELCO and MLCC
            3. 8.2.1.2.1.3  Input Capacitor, CIN ELCO and MLCC
            4. 8.2.1.2.1.4  Switching MOSFET, QSW
            5. 8.2.1.2.1.5  Rectifier MOSFET, QSR
            6. 8.2.1.2.1.6  Timing Resistor, RT
            7. 8.2.1.2.1.7  Feed-Forward and UVLO Resistor, RKFF
            8. 8.2.1.2.1.8  Soft-Start Capacitor, CSS
            9. 8.2.1.2.1.9  Short-Circuit Protection, RILIM and CILIM
            10. 8.2.1.2.1.10 Boost Voltage, CBOOST and DBOOST (Optional)
            11. 8.2.1.2.1.11 Closing the Feedback Loop, RZ1, RP1, RPZ2, RSET1, RSET2, CZ2, CP2, and CPZ1
        3. 8.2.1.3 Application Curves
    3. 8.3 Additional System Examples
  9. 9 Layout
    1. 9.1 Layout Guidelines
  10. 10器件和文档支持
    1. 10.1 器件支持
      1. 10.1.1 第三方产品免责声明
    2. 10.2 文档支持
      1. 10.2.1 相关文档
    3. 10.3 接收文档更新通知
    4. 10.4 社区资源
    5. 10.5 商标
    6. 10.6 静电放电警告
    7. 10.7 Glossary
  11. 11机械、封装和可订购信息
  12. 重要声明
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DATA SHEET

具有电压前馈功能的 TPS40077 4.5V 至 28V 输入、电压模式、同步降压控制器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 在 4.5V 至 28V 输入范围内运行
  • 固定频率高达 1MHz 的可编程电压模式控制器
  • 预测性栅极驱动反跨导电路
  • <1% 内部 700mV 基准电压
  • 用于高侧和同步 N 沟道金属氧化物半导体场效应晶体管 (MOSFET) 的内部栅极驱动输出
  • 16 引脚 PowerPAD™封装
  • 热关断保护
  • 与预偏置功能兼容
  • 功率级关断功能
  • 可编程高侧感应短路保护

2 应用

  • 电源模块
  • 网络/电信
  • PCI Express
  • 工业
  • 服务器

3 说明

TPS40077 是一款中压、宽输入电压（4.5V 至 28V）同步降压控制器，可以为多种用户可编程功能的设计提供灵活性，包括软启动、欠压锁定 (UVLO)、工作频率、电压前馈以及高侧 FET 检测短路保护。

TPS40077 使用第二代预测性栅极驱动器来驱动外部 N 沟道 MOSFET，以便最大限度降低低侧 FET 的体二极管的导电能力，并最大限度提高效率。其支持预偏置输出，方式是在闭环软启动所需的电压大于预偏置电压之前，禁止打开低侧 FET。电压前馈功能可在发生输入瞬变时即时响应，并在宽输入电压工作范围内提供恒定的 PWM 增益以降低补偿要求。可编程的短路保护提供了故障电流限制和断续恢复功能，可最大限度降低输出短路时的功率耗散。16 引脚 PowerPAD 封装带来良好的热性能和紧凑的外形。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
TPS40077 HTSSOP (16) 5.00mm x 4.40mm
  1. 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

Device Images

简化应用示意图

TPS40077 v09041_lus714.gif

4 修订历史记录

Changes from D Revision (April 2009) to E Revision

  • 添加了特性 说明 部分、器件功能模式、应用和实施 部分、电源建议 部分、布局 部分、器件和文档支持 部分以及 机械、封装和可订购信息 部分；编辑性更改Go
  • Deleted Ordering Information tableGo
  • Moved Package Dissipation Ratings table to Power DissipationGo

5 Pin Configuration and Functions

16-Pin HTSSOP with PowerPAD
TPS40077 p0047-01_lus714.gif
1. For more information on the PWP package, see the PowerPAD Thermally Enhanced Package technical brief (SLMA002).

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 KFF I A resistor connected from this pin to VIN programs the amount of feed-forward voltage. The current fed into this pin is internally divided by 25 and used to control the slope of the PWM ramp and program UVLO. Nominal voltage at this pin is maintained at 400 mV.
2 RT I A resistor is connected from this pin to ground to set the internal oscillator and switching frequency.
3 LVBP O 4.2-V reference used for internal device logic only. This pin should be bypassed by a 0.1-μF ceramic capacitor. External loads that are less than 1 mA and electrically quiet may be applied.
4 PGD O This is an open-drain output that pulls to ground when soft start is active, or when the FB pin is outside a ±10% band around VREF.
5 SGND — Signal ground reference for the device. Low-level quiet circuitry around the IC should connect to this pin. This pin should be connected to the thermal pad under the IC, and that thermal pad should connect to the PGND pin. Do not allow power currents to flow in the thermal pad or in the SGND part of the ground for best results.
6 SS I Soft-start programming pin. A capacitor connected from this pin to GND programs the soft-start time. The capacitor is charged with an internal current source of 12 μA. The resulting voltage ramp on the SS pin is used as a second noninverting input to the error amplifier. The voltage at this error amplifier input is approximately 1 V less than that on the SS pin. Output voltage regulation is controlled by the SS voltage ramp until the voltage on the SS pin reaches the internal offset voltage of 1 V plus the internal reference voltage of 700 mV. If SS is pulled below 225 mV, the device goes into a shutdown state where the power FETSs are turned off and the prebias circuitry is reset. If the programmed UVLO voltage is below 6 V, connect a 330-kΩ resistor in parallel with the SS capacitor. Also provides timing for fault recovery attempts.
7 FB I Inverting input to the error amplifier. In normal operation, the voltage on this pin is equal to the internal reference voltage, 0.7 V.
8 COMP O Output of the error amplifier, input to the PWM comparator. A feedback network is connected from this pin to the FB pin to compensate the overall loop. The COMP pin is internally clamped to 3.4 V.
9 PGND — Power ground reference for the device. There should be a low-impedance path from this pin to the source(s) of the lower MOSFET(s).
10 LDRV O Gate drive for the N-channel synchronous rectifier. This pin switches from DBP (MOSFET on) to ground (MOSFET off). For proper operation, the total gate charge of the MOSFET connected to LDRV should be less than 50 nC.
11 DBP O 8-V reference used for the gate drive of the N-channel synchronous rectifier. This pin should be bypassed to ground with a 1-μF ceramic capacitor.
12 SW I This pin is connected to the switched node of the converter. It is used for short-circuit sensing and gate-drive timing information and is the return for the high-side driver. A 1.5-Ω resistor is required in series with this pin for protection against substrate current issues.
13 HDRV O Floating gate drive for the high-side N-channel MOSFET. This pin switches from BOOST (MOSFET on) to SW (MOSFET off).
14 BOOST I The peak voltage on BOOST is equal to the SW node voltage plus the voltage present at DBP less the bootstrap diode drop. This drop can be 1.4 V for the internal bootstrap diode or 300 mV for an external Schottky diode. The voltage differential between this pin and SW is the available drive voltage for the high-side FET.
15 VDD I Supply voltage for the device.
16 ILIM I Short-circuit-protection programming pin. This pin is used to set the short circuit detection threshold. An internal current sink from this pin to ground sets a voltage drop across an external resistor connected from this pin to VDD. The voltage on this pin is compared to the voltage drop (VVDD – VSW) across the high side N-channel MOSFET during conduction. Just prior to the beginning of a switching cycle, this pin is pulled to approximately VDD/2 and released when SW is within 2 V of VDD or after a timeout (the precondition time), whichever occurs first. Placing a capacitor across the resistor from ILIM to VDD allows the ILIM threshold to decrease during the switch-on time, effectively programming the ILIM blanking time. See Application Information.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input voltage, VVDD VDD, ILIM 30 V
COMP, FB, KFF, PGD, LVBP –0.3 6
SW –0.3 40
SW, transient (<50 ns) –2.5
Output voltage, VOUT COMP, KFF, RT, SS –0.3 6 V
VBOOST 50
DBP 10.5
LVBP 6
Output current source, IOUT (LDRV, HDRV) 1.5 A
Output current sink, IOUT LDRV, HDRV 2 A
KFF 10
Output current RT 1 mA
LVBP 1.5
Lead temperature, 1.6 mm (1/16 inch) from case (10 s) 260 °C
Operating junction temperature, TJ –40 125 °C
Storage temperature, Tstg –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

 
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