ZHCSJU5C February   2019  – December 2024 CC3135

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 应用
  4. 3 说明
  5. 4 功能方框图
  6. 5 Device Comparison
    1. 5.1 Related Products
  7. 6 Pin Configuration and Functions
    1. 6.1 Pin Diagram
    2. 6.2 Pin Attributes
    3. 6.3 Signal Descriptions
      1.      12
    4. 6.4 Connections for Unused Pins
  8. 7 Specifications
    1. 7.1  Absolute Maximum Ratings
    2. 7.2  ESD Ratings
    3. 7.3  Power-On Hours (POH)
    4. 7.4  Recommended Operating Conditions
    5. 7.5  Current Consumption Summary: 2.4 GHz RF Band
    6. 7.6  Current Consumption Summary: 5 GHz RF Band
    7. 7.7  TX Power Control for 2.4 GHz Band
    8. 7.8  TX Power Control for 5 GHz
    9. 7.9  Brownout and Blackout Conditions
      1.      24
    10. 7.10 Electrical Characteristics for DIO Pins
      1.      26
      2.      27
    11. 7.11 Electrical Characteristics for Pin Internal Pullup and Pulldown
    12. 7.12 WLAN Receiver Characteristics
      1.      30
      2.      31
    13. 7.13 WLAN Transmitter Characteristics
      1.      33
      2.      34
    14. 7.14 WLAN Transmitter Out-of-Band Emissions
      1.      36
      2.      37
    15. 7.15 BLE/2.4 GHz Radio Coexistence and WLAN Coexistence Requirements
    16. 7.16 Thermal Resistance Characteristics for RGK Package
    17. 7.17 Timing and Switching Characteristics
      1. 7.17.1 Power Supply Sequencing
      2. 7.17.2 Device Reset
      3. 7.17.3 Reset Timing
        1. 7.17.3.1 nRESET (32-kHz Crystal)
        2.       45
        3. 7.17.3.2 nRESET (External 32-kHz Crystal)
          1.        47
      4. 7.17.4 Wakeup From HIBERNATE Mode
        1.       49
      5. 7.17.5 Clock Specifications
        1. 7.17.5.1 Slow Clock Using Internal Oscillator
          1.        52
        2. 7.17.5.2 Slow Clock Using an External Clock
          1.        54
        3. 7.17.5.3 Fast Clock (Fref) Using an External Crystal
          1.        56
        4. 7.17.5.4 Fast Clock (Fref) Using an External Oscillator
          1.        58
      6. 7.17.6 Interfaces
        1. 7.17.6.1 Host SPI Interface Timing
          1.        61
        2. 7.17.6.2 Flash SPI Interface Timing
          1.        63
        3. 7.17.6.3 DIO Interface Timing
          1. 7.17.6.3.1 DIO Output Transition Time Parameters (Vsupply = 3.3 V)
            1.         66
          2. 7.17.6.3.2 DIO Input Transition Time Parameters
            1.         68
    18. 7.18 External Interfaces
      1. 7.18.1 SPI Flash Interface
      2. 7.18.2 SPI Host Interface
      3. 7.18.3 Host UART Interface
        1. 7.18.3.1 5-Wire UART Topology
        2. 7.18.3.2 4-Wire UART Topology
        3. 7.18.3.3 3-Wire UART Topology
  9. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Device Features
      1. 8.2.1 WLAN
      2. 8.2.2 Network Stack
      3. 8.2.3 Security
      4. 8.2.4 Host Interface and Driver
      5. 8.2.5 System
    3. 8.3 FIPS 140-2 Level 1 Certification
    4. 8.4 Power-Management Subsystem
      1. 8.4.1 VBAT Wide-Voltage Connection
    5. 8.5 Low-Power Operating Modes
      1. 8.5.1 Low-Power Deep Sleep
      2. 8.5.2 Hibernate
      3. 8.5.3 Shutdown
    6. 8.6 Memory
      1. 8.6.1 External Memory Requirements
    7. 8.7 Restoring Factory Default Configuration
    8. 8.8 Hostless Mode
  10. 9 Applications, Implementation, and Layout
    1. 9.1 Application Information
      1. 9.1.1 BLE/2.4GHz Radio Coexistence
      2. 9.1.2 Antenna Selection
      3. 9.1.3 Typical Application
    2. 9.2 PCB Layout Guidelines
      1. 9.2.1 General PCB Guidelines
      2. 9.2.2 Power Layout and Routing
        1. 9.2.2.1 Design Considerations
      3. 9.2.3 Clock Interface Guidelines
      4. 9.2.4 Digital Input and Output Guidelines
      5. 9.2.5 RF Interface Guidelines
  11. 10Device and Documentation Support
    1. 10.1  第三方产品免责声明
    2. 10.2  Tools and Software
    3. 10.3  Firmware Updates
    4. 10.4  Device Nomenclature
    5. 10.5  Documentation Support
    6. 10.6  支持资源
    7. 10.7  Trademarks
    8. 10.8  静电放电警告
    9. 10.9  Export Control Notice
    10. 10.10 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information
    1. 12.1 Packaging Information
    2. 12.2 Tape and Reel Information

7.18.3.3 3-Wire UART Topology

The 3-wire UART topology requires only the following lines (see Figure 7-20):

  • RX
  • TX
  • CTS
CC3135 3-Wire UART TopologyFigure 7-20 3-Wire UART Topology

 

Using this topology requires meeting one of the following conditions:

  • The host always stays awake or active.
  • The host goes to sleep but the UART module has receiver start-edge detection for auto-wake-up and does not lose data.
  • The host can always receive any amount of data transmitted by the SimpleLink™ device because there is no flow control in this direction.

Because there is no full flow control, the host cannot stop the SimpleLink™ device to send its data; thus, the following parameters must be carefully considered:

  • Maximum baud rate
  • RX character interrupt latency and low-level driver jitter buffer
  • Time consumed by the user's application