ZHCSJL1C September   2010  – April 2019 TPS61251

PRODUCTION DATA.  

  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 说明 （续）
  6. 6 Device Options
  7. 7 Pin Configuration and Functions
    1.     Pin Functions
  8. 8 Specifications
    1. 8.1 Absolute Maximum Ratings
    2. 8.2 ESD Ratings
    3. 8.3 Recommended Operating Conditions
    4. 8.4 Thermal Information
    5. 8.5 Electrical Characteristics
    6. 8.6 Typical Characteristics
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Current Limit Operation
      2. 9.3.2 Soft Start
      3. 9.3.3 Enable
      4. 9.3.4 Undervoltage Lockout (UVLO)
      5. 9.3.5 Power Good
      6. 9.3.6 Input Overvoltage Protection
      7. 9.3.7 Load Disconnect and Reverse Current Protection
      8. 9.3.8 Thermal Regulation
      9. 9.3.9 Thermal Shutdown
    4. 9.4 Device Functional Modes
      1. 9.4.1 Power-Save Mode
      2. 9.4.2 Snooze Mode
      3. 9.4.3 100% Duty-Cycle Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
        1. 10.2.2.1 Custom Design With WEBENCH® Tools
        2. 10.2.2.2 Output Voltage Setting
        3. 10.2.2.3 Average Input Current Limit
        4. 10.2.2.4 Maximum Output Current
        5. 10.2.2.5 Inductor Selection
        6. 10.2.2.6 Output Capacitor
        7. 10.2.2.7 Input Capacitor
        8. 10.2.2.8 Checking Loop Stability
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
    3. 12.3 Thermal Consideration
  13. 13器件和文档支持
    1. 13.1 器件支持
      1. 13.1.1 第三方产品免责声明
    2. 13.2 开发支持
      1. 13.2.1 使用 WEBENCH® 工具创建定制设计
    3. 13.3 接收文档更新通知
    4. 13.4 社区资源
    5. 13.5 商标
    6. 13.6 静电放电警告
    7. 13.7 术语表
  14. 14机械、封装和可订购信息

10.2.2.2 Output Voltage Setting

The output voltage can be calculated using Equation 4.

Equation 4. TPS61251 eq4_vout_lvsaf7.gif

To minimize the current through the feedback divider network and therefore increase efficiency during snooze mode operation, R2 must be > 240 k. To keep the network robust against noise the resistor divider can also be in the lower 100-k values. In this case, R1 is 1000 kΩ and R2 is 280 kΩ.

An external feed forward capacitor C1 is required for optimum load transient response. The value of C1 must be 1000 pF. The connection from FB pin to the resistor divider should be kept short and away from noise sources, such as the inductor or the SW line.