TCAN4550-Q1 带有集成控制器和收发器的汽车控制器区域网灵活数据速率 (CAN FD) 系统基础芯片
- ZHCSJK5D January 2018 – June 2022 TCAN4550-Q1
  
  PRODUCTION DATA

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TCAN4550-Q1 带有集成控制器和收发器的汽车控制器区域网灵活数据速率 (CAN FD) 系统基础芯片

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

符合面向汽车应用的 AEC-Q100 标准
- 温度等级 1：–40°C 至 125°C，T_A
功能安全质量管理型
- 有助于进行功能安全系统设计的文档
带有集成 CAN FD 收发器和串行外设接口 (SPI) 的 CAN FD 控制器
CAN FD 控制器支持 ISO 11898-1:2015 和 Bosch M_CAN 修订版 3.2.1.1
符合 ISO 11898-2:2016 的要求
支持 CAN FD 数据速率高达 8Mbps，且 SPI 时钟速率高达 18MHz
向后兼容经典 CAN
工作模式：正常、待机、睡眠和失效防护
为微处理器提供 3.3V 至 5V 输入/输出逻辑支持
在 CAN 总线上具有宽工作范围
- ±58V 总线故障保护
- ±12V 共模电压
集成的低压降稳压器为 CAN 收发器提供 5V 电压，并为外部器件提供高达 70mA 的电流
优化了未上电时的性能
- 总线和逻辑终端为高阻抗
  （运行总线或应用上无负载）
- 上电和断电无干扰运行

2 应用

3 说明

TCAN4550-Q1 是带有集成 CAN FD 收发器的 CAN FD 控制器，支持高达 8Mbps 的数据速率。此 CAN FD 控制器符合 ISO11898-1:2015 高速控制器局域网 (CAN) 数据链路层的规范，并满足 ISO11898–2:2016 高速 CAN 规范的物理层要求。

TCAN4550-Q1 通过串行外设接口 (SPI) 在 CAN 总线和系统处理器之间提供了一个接口，同时支持经典 CAN 和 CAN FD，并为不支持 CAN FD 的处理器提供端口扩展或 CAN 支持。TCAN4550-Q1 提供 CAN FD 收发器功能：传输到总线的差分传输能力和从总线接收的差分接收能力。该器件支持通过本地唤醒 (LWU) 进行唤醒以及使用实现 ISO11898-2:2016 唤醒模式 (WUP) 的 CAN 总线进行总线唤醒。

为了保证器件和 CAN 总线的稳健耐用性，此器件包括很多保护特性。这些特性包括失效防护模式、内部显性状态超时、宽总线工作范围和超时看门狗，等等。

器件信息

器件型号	封装⁽¹⁾	封装尺寸（标称值）
TCAN4550-Q1	VQFN (20)	4.50mm x 3.50mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

简化版原理图，CLKIN 来自 MCU

简化版原理图，晶振

4 Revision History

Changes from Revision C (October 2020) to Revision D (June 2022)

更改了数据表标题Go
通篇将英文的“wake up”（唤醒）更改为“wake-up”（唤醒）Go
Changed description of the OSCI (pin 1) and OSC2 (pin 2) in the Pin Functions tableGo
Added a second paragraph to the OSC1 and OSC2 Pins sectionGo
Changed register Timestamp Prescalar to: Timestamp Prescaler Go
Changed bit 23 from: RSVD to: SMS in Table 8-20 Go
Changed bit 9 description from: Transmission Completed to: Transmission Cancellation FinishedGo
Changed bit 32:24 to: 30:24 in Table 8-56 Go
Changed bullet: This is where the termination is split into two resistors, R5 and R6 To: This is where the termination is split into two resistors, R4 and R5 in the Layout Guidelines Go
Added bullet for R8 in the Layout Guidelines Go
Changed the Layout Example: added resistor R8 to Pin 1.Go

Changes from Revision B (November 2019) to Revision C (October 2020)

Changed UV_SUP rising max from 5.9 to 5.7 and added min value of 5.2Go
Added UV_SUP falling max value of 5.0Go
Changed bit 2:0 To: 3:0 in Table 8-29 Go

Changes from Revision A (April 2019) to Revision B (November 2019)

添加了“功能安全质量管理型”首页项目符号Go
Changed V_IO value I_IL for SDI, SCK and nCS inputs in test conditions cell value from 0 V to 5.25 VGo
Changed Power Up Timing diagram VSUP ramp voltage level for INH turn on and timing.Go
Added INH Brownout Behavior section in Application section.Go

Changes from Revision * (October 2017) to Revision A (April 2019)

将文档状态从预告信息 更改为量产数据Go
Changed footnote Gauranteed to Specied throughout the electric table.Go
Added V_IO values for t_SOV.Go
Changed Power Up Timing diagram VSUP ramp voltage level for INH turn on and timing. Go
Deleted CLKOUT from the GPIO1 circuit in Figure 8-2 Go
Deleted CLKOUT: Off from Sleep Mode section in Figure 8-14 Go
Deleted CLKOUT: Off From Sleep Mode section in Figure 8-15 Go
Deleted bits 15 and 14 from GPO1_CONFIG from in Table 8-16 Go
Changed CLKOUT_GPIO1_CONFIG To: GPIO1_CONFIG for GPO1_CONFIG in Table 8-16 Go
Changed the name of offset 1048 From: TDCE To: TDCR Go

5 Pin Configuration and Functions

Figure 5-1 RGY Package
20 Pin (VQFN)
(Top View)

Table 5-1 Pin Functions

PIN		TYPE⁽¹⁾	DESCRIPTION
NO.	NAME	TYPE⁽¹⁾	DESCRIPTION
1	OSC1	I/O	External crystal oscillator output or single-ended clock input
2	nWKRQ	DO	Wake request (active low)
3	GPIO1	DI/O	Configurable input/output function pin through SPI
4	SCLK	DI	SPI clock input
5	SDI	DI	SPI target data input from controller output
6	SDO	DO	SPI target data output to controller input
7	nCS	DI	SPI chip select
8	nINT	DO	Interrupt pin to MCU (active low)
9	GPO2	DO	Configurable output function pin through SPI
10	CANL	HV Bus I/O	Low level CAN bus line
11	CANH	HV Bus I/O	High level CAN bus line
12	WAKE	HVI	Wake input, high voltage input
13	GND	GND	Ground connection
14	V_SUP	HV Supply In	Supply from battery
15	INH	HVO	Inhibit to control system voltage regulators and supplies (open drain)
16	V_CCOUT	Supply Out	5 V regulated output
17	V_IO	Supply In	Digital I/O voltage supply
18	FLTR	—	Internal regulator filter, requires external capacitor to ground
19	RST	DI	Device reset
20	OSC2	I	External crystal oscillator input; when using single-ended input clock to OSC1 this pin should be connected to ground.

(1) Note: DI = Digital Input; DO = Digital Output; HV = High Voltage; Thermal PAD and GND Pins must be soldered to GND

6 Specification

6.1 Absolute Maximum Ratings

over operating free-air temperature range for – 40 ℃ ≤ T_A ≤ 125 ℃ (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
V_SUP	Supply voltage	–0.3	42	V
V_IO	Supply voltage I/O level shifter	–0.3	6	V
V_CCOUT	5 V output supply	–0.3	6	V
V_BUS	CAN bus I/O voltage (CANH, CANL)	–58	58	V
V_WAKE	WAKE pin input voltage	–0.3	42	V
V_INH	Inhibit pin output voltage	–0.3	42	V
V_{Logic_Input}	Logic input terminal voltage	–0.3	6	V
V_SO	Digital output terminal voltage	–0.5	6	V
I_O(SO)	Digital output current		8	mA
I_O(INH)	Inhibit output current		4	mA
I_O(WAKE)	Wake current if due to ground shift V_(WAKE) ≤ V_(GND) – 0.3 V		3	mA
T_J	Junction temperature	–40	150	°C
T_stg	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM) classification level 3A per AEC Q100-002 All terminal except for CANH and CANL. ⁽¹⁾ WAKE terminals which are with respect to ground only ⁽²⁾		±4000	V
V_(ESD)	Electrostatic discharge	Human body model (HBM) classification level H2 for CANH and CANL ⁽²⁾		±15000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM) classification level C5, per AEC Q100-011	All terminals	±750	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(2) Terminals stressed with respect to GND

6.3 ESD Ratings, IEC ESD and ISO Transient Specification

			VALUE	UNIT
V_(ESD)	Electrostatic discharge according to IBEE CAN EMC ⁽¹⁾	Contact discharge	±8000	V
V_(ESD)	Electrostatic discharge according to IBEE CAN EMC ⁽¹⁾	Air discharge	±15 000	V
V_(ESD)	Electrostatic discharge according to SAEJ2962-2 ⁽²⁾	Contact discharge	±8000	V
V_(ESD)	Electrostatic discharge according to SAEJ2962-2 ⁽²⁾	Air discharge	±15 000
ISO7637 Transients according to IBEE CAN EMC test spec CAN bus terminals (CANH and CANL), V_SUP and WAKE ⁽³⁾		Pulse 1	-100
		Pulse 2	75
		Pulse 3a	-150
		Pulse 3b	100

(1) IEC 61000-4-2 is a system-level ESD test. Results given here are specific to the IBEE LIN EMC Test specification conditions per IEC TS 62228. Different system-level configurations may lead to different results

(2) SAEJ2962-2 Testing performed at 3^rd party US3 approved EMC test facility, test report available upon request.

(3) ISO7637 is a system-level transient test. Results given here are specific to the IBEE CAN EMC Test specification conditions. Different system-level configurations may lead to different results.

6.4 Recommended Operating Conditions

over operating free-air temperature range for – 40 ℃ ≤ T_A ≤ 125 ℃ (unless otherwise noted)

		MIN	TYP	MAX	UNIT
V_SUP	Supply voltage	5.5		30	V
V_IO	Logic pin supply voltage	3.135		5.25	V
I_OH(DO)	Digital terminal high-level output current	–2			mA
I_OL(DO)	Digital terminal low-level output current			2	mA
I_{O (INH)}	INH output current			1	mA
C_(FLTR)	Filter pin capacitance See Section 10	300			nF
C_(VCCOUT)	V_CCOUT supply capacitance See Section 10	10			µF
C_WAKE	External WAKE pin capacitance	10			nF
T_SDR	Thermal shutdown rising	160			℃
T_SDF	Thermal shutdown falling			150	℃
T_SD(HYS)	Thermal shutdown hysteresis		10		℃

6.5 Thermal Information

THERMAL METRIC⁽¹⁾		TCAN4550	UNIT
		PKG DES (RGY)
		20 PINS
R_θJA	Junction-to-ambient thermal resistance	35.2	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	28.1	°C/W
R_θJB	Junction-to-board thermal resistance	12.8	°C/W
Ψ_JT	Junction-to-top characterization parameter	0.3	°C/W
Ψ_JB	Junction-to-board characterization parameter	12.7	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	1.1	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.6 Supply Characteristics

over operating free-air temperature range for – 40 ℃ ≤ T_A ≤ 125 ℃ (unless otherwise noted)

PARAMETER			TEST CONDITIONS	MIN	TYP	MAX	UNIT
I_SUP	Supply current, normal mode	Dominant	See Figure 7-3 R_L = 60 Ω, C_L = open. typical bus load. V_CCOUT = no load			80	mA
		Dominant	See Figure 7-3 R_L = 50 Ω, C_L = open, high bus load. V_CCOUT = no load			90	mA
		Dominant with bus fault	See Figure 7-3 CANH = - 25 V, R_L = open, C_L = open V_CCOUT = no load			180	mA
		Recessive	See Figure 7-3 R_L = 60 Ω, C_L = open, R_CM = open, V_CCOUT = no load			15	mA
	Supply current, standby mode		See Figure 7-3 R_L = 60 Ω, C_L = open, -40°C < T_A < 85°C, V_CCOUT = no load, CANH/L terminated to 2.5 V			3.5	mA
	Supply current, standby mode		See Figure 7-3 RL = 60 Ω, C_L = open, -40°C < T_A < 85°C, V_CCOUT = no load CANH/L terminated to GND ± 100 mV			3.4	mA
I_SUP	Supply current, sleep mode		SPI bus, OSC/CLKIN disabled: -40°C < T_A < 85°C, V_IO = 0		25	42	µA
I_VIO	I/O supply current normal mode dominant	I/O supply current	CLKIN = 40 MHz, V_IO = 5 V			800	µA
I_VIO	I/O supply current normal mode dominant	I/O supply current	Crystal = 40 MHz, V_IO = 5 V			3	mA
I_VIO	I/O supply current, sleep mode	I/O supply current	Sleep Mode V_IO = 5 V; OSC1 = CLKIN = 0 V and OSC2 = GND ⁽²⁾			9	µA
I_VCCOUT	V_CCOUT supply current		Normal Mode: V_CCOUT = 5 V; -40°C < T_A < 85°C See Section Section 8.3.3			70	mA
UV_SUP	Under voltage detection on V_SUP rising ramp for protected mode		See Section Section 8.4.6.7	5.2	5.5	5.7	V
UV_SUP	Under voltage detection on V_SUP falling ramp for protected mode		See Section Section 8.4.6.7	4.5	4.7	5.0	V
UV_IO	Under voltage detection on V_IO rising ramp for protected mode		See Section Section 8.4.6.7		2.45	2.6	V
UV_IO	Under voltage detection on V_IO falling ramp for protected mode		See Section Section 8.4.6.7	2.1	2.25		V
t_UV/TSD	Under voltage filter time and thermal shutdown timer ⁽¹⁾		Upon a UV_IO event this timer starts and provides time for V_IO input to return. See section Section 8.4.6.6 for description of thermal shut down.	200		500	ms

(1) Specified by design

(2) When a crystal is used this current will be higher until the crystal's capacitors bleed off their energy. How much current and length of time to bleed of the energy is system dependent and will not be specified.

6.7 Electrical Characteristics

over operating free-air temperature range for – 40 ℃ ≤ T_A ≤ 125 ℃ (unless otherwise noted)

PARAMETER		TEST CONDITIONS ⁽¹⁾	MIN	TYP	MAX	UNIT
CAN DRIVER ELECTRICAL CHARACTERISTICS
V_O(D)	Bus output voltage (dominant) CANH	See Figure 7-3 and Figure 7-4, TXD_INT = 0 V, EN = 0 V, 50 Ω ≤ R_L ≤ 65 Ω, C_L = open, R_CM = open	2.75		4.5	V
V_O(D)	Bus output voltage (dominant) CANL		0.5		2.25	V
V_O(R)	Bus output voltage (recessive)	See Figure 7-1 and Figure 7-4, TXD_INT = V_IO, R_L = open (no load), R_CM = open	2	2.5	3	V
V_(DIFF)	Maximum differential voltage rating	See Figure 7-1 and Figure 7-4	–5.0		10	V
V_O(STB)	Bus output voltage (Standby Mode) CANH	See Figure 7-1 and Figure 7-4, TXD_INT = V_IO, R_L = open (no load), R_CM = open	–0.1		0.1	V
	Bus output voltage (Standby Mode) CANL		–0.1		0.1	V
	Bus output voltage (Standby Mode) CANH - CANL		–0.2		0.2	V
V_OD(D)	Differential output voltage (dominant)	See Figure 7-1 and Figure 7-4, TXD_INT = 0 V, 50 Ω ≤ R_L ≤ 65 Ω, C_L = open, R_CM = open	1.5		3	V
		See Figure 7-1 and Figure 7-4, TXD_INT = 0 V, 45 Ω ≤ R_L ≤ 70 Ω, C_L = open, R_CM = open	1.4		3	V
		See Figure 7-1 and Figure 7-4, TXD_INT = 0 V, R_L = 2.24 kΩ, C_L = open, R_CM = open	1.5		5	V
V_OD(R)	Differential output voltage (recessive)	See Figure 7-1 and Figure 7-4, TXD_INT = V_IO, R_L = 60 Ω, C_L = open, R_CM = open	–120		12	mV
V_OD(R)	Differential output voltage (recessive)	See Figure 7-1 and Figure 7-4, TXD_INT = V_IO, R_L = open (no load), C_L = open, R_CM = open	–50		50	mV
V_SYM	Output symmetry (dominant or recessive) ( VO(CANH) + VO(CANL)) / VCC	See Figure 7-1 and Figure 7-4, R_L = 60 Ω, C_L = open, R_CM= open, C1 = 4.7 nF, TXD_INT - 250 kHZ, 1 MHz	0.9		1.1	V/V
V_{SYM_DC}	Output symmetry (dominant or recessive) (VCC – VO(CANH) – VO(CANL)) with a frequency that corresponds to the highest bit rate for which the HS-PMA implementation is intended, however, at most 1 MHz (2 Mbit/s)	See Figure 7-1 and Figure 7-4, R_L = 60 Ω, C_L = open, R_CM= open, C1 = 4.7 nF	–300		300	mV
IOS_DOM	Short-circuit steady-state output current, dominant	See Figure 7-1 and Figure 7-8, -3.0 V ≤ V_CANH ≤ 18.0 V, CANL = open, TXD_INT = 0 V	–100			mA
IOS_DOM	Short-circuit steady-state output current, dominant	See Figure 7-1 and Figure 7-8, -3.0 V ≤ V_CANL ≤+18.0 V, CANH = open, TXD_INT = 0 V			100	mA
IOS_REC	Short-circuit steady-state output current, recessive	See Figure 7-1 and Figure 7-8, – 27 V ≤ V_BUS ≤ 32 V_,V_BUS = CANH = CANL	–5		5	mA
CAN RECEIVER ELECTRICAL CHARACTERISTICS
V_ITdom	Receiver dominant state differential input voltage range, bus biasing active	-12.0 V ≤ V_CANL ≤ +12.0 V -12.0 V ≤ V_CANH ≤ +12.0 V See Figure 7-5, Table 8-3	0.9		8	V
V_ITrec	Receiver recessive state differential input voltage range bus biasing active		–3.0		0.5	V
V_HYS	Hysteresis voltage for input-threshold, normal modes	See Figure 7-5, Table 8-3		120		mV
V_IT(ENdom)	Receiver dominant state differential input voltage range, bus biasing inactive (VDiff)	-12.0 V ≤ V_CANL ≤ +12.0 V -12.0 V ≤ V_CANH ≤ +12.0 V See Figure 7-5, Table 8-3	1.15		8	V
V_IT(ENrec)	Receiver recessive state differential input voltage range, bus biasing inactive (VDiff)	-12.0 V ≤ V_CANL ≤ +12.0 V -12.0 V ≤ V_CANH ≤ +12.0 V See Figure 7-5, Table 8-3	–3		0.4	V
V_CM	Common mode range: normal	See Figure 7-5, Table 8-3	–12		12	V
V_CM(EN)	Common mode range: standby mode	See Figure 7-5, Table 8-3	–12		12	V
I_IOFF(LKG)	Power-off (unpowered) bus input leakage current	V_CANH = V_CANL = 5 V, V_sup to GND via 0 Ω and 47 kΩ resistor			5	µA
C_I	Input capacitance to ground (CANH or CANL)				25	pF
C_ID	Differential input capacitance				14	pF
R_ID	Differential input resistance	TXD_INT = V_CCINT, normal mode: -2.0 V ≤ V_CANH≤+7.0 V; -2.0 V ≤V_CANL ≤ + 7.0 V	60		100	kΩ
R_IN	Single ended Input resistance (CANH or CANL)	-2.0 V ≤ V_CANH ≤+7.0 V; -2.0 V ≤V_CANL ≤ + 7.0 V	30		50	kΩ
R_IN(M)	Input resistance matching: [1 – (R_IN(CANH) / (R_IN(CANL))] × 100%	V_CANH = V_CANL = 5.0 V	–1		1	%
V_CCOUT SUPPLY TERMINAL
V_CCOUT	5 V output supply	I_CCOUT = -70 mA to 0 mA; V_SUP = 5.5 V to 18 V; -40°C < T_A < 85°C	4.75	5	5.25	V
V_DROP	Drop out voltage	V_CCOUT = 5 V, V_SUP = 12 V, I_CCOUT = 70 mA		300	500	mV
ΔV_CC(ΔVSUP)	Line regulation	V_SUP = 5.5 V to 30 V, ΔV_CCOUT, I_CCOUT = 10 mA			50	mV
ΔV_CC(ΔVSUPL)	Load regulation	V_SUP = 14 V, I_CCOUT = 1 mA to 70 mA, ΔV_CCOUT,–40℃ ≤ T_A ≤ 125℃			60	mV
UV_CCOUT	Under voltage threshold on V_CCOUT			4.2	4.55	V
FLTR TERMINAL
V_MEASURE	Voltage measured at FLTR pin			1.5		V
C_(FLTR)	Filter pin capacitor	External filter capacitor	300	330		nF
INH OUTPUT TERMINAL (HIGH VOLTAGE OUTPUT)
ΔV_H	High-level voltage drop INH with respect to V_SUP	I_INH = - 0.5 mA		0.5	1	V
I_LKG(INH)	Leakage current	INH = 0 V, Sleep Mode	–0.5		0.7	µA
WAKE INPUT TERMINAL (HIGH VOLTAGE INPUT)
V_IH	High-level input voltage	Standby mode, WAKE pin enabled	V_SUP–2			V
V_IL	Low-level input voltage	Standby mode, WAKE pin enabled			V_SUP–3	V
I_IH	High-level input current	WAKE = V_SUP–1 V	–25	–15		µA
I_IL	Low-level input current	WAKE = 1 V		15	25	µA
t_WAKE	WAKE filter time	Wake up filter time from a wake edge on WAKE; standby, sleep mode	50			µs
SDI, SCK, GPIO1 INPUT TERMINALS
V_IH	High-level input voltage		0.7			V_IO
V_IL	Low-level input voltage				0.3	V_IO
I_IH	High-level input leakage current	Inputs = V_IO = 5.25 V	–1		1	µA
I_IL	Low-level input leakage current	Inputs = 0 V, V_IO = 5.25 V	–100		–5	µA
C_IN	Input capacitance	18 MHz		10	12	pF
I_LKG(OFF)	Unpowered leakage current (SDI and SCK only)	Inputs = 5.25 V, V_IO = V_SUP = 0 V	–1		1	µA
nCS INPUT TERMINAL
V_IH	High-level input voltage		0.7			V_IO
V_IL	Low-level input voltage				0.3	V_IO
I_IH	High-level input leakage current	nCS = V_IO = 5.25 V	–1		1	µA
I_IL	Low-level input leakage current	nCS = V_IO = 5.25 V	–50		–5	µA
I_LKG(OFF)	Unpowered leakage current	nCS = 5.25 V, V_IO = V_SUP = 0 V	–1		1	µA
RST INPUT TERMINAL
V_IH	High-level input voltage		0.7			V_IO
V_IL	Low-level input voltage				0.3	V_IO
I_IH	High-level input leakage current	RST = V_IO = 5.25 V	1		10	µA
I_IL	Low-level input leakage current	RST = 0 V	–1		1	µA
I_LKG(OFF)	Unpowered leakage current	RST = V_IO, V_SUP = 0 V	–7.5		7.5	µA
t_{PULSE_WIDTH}	Width of the input pulse		30			µs
SDO, GPIO1, GPO2 OUTPUT TERMINAL; nINT (OPEN DRAIIN) and nWKRQ (WHEN PROGRAMMED TO WORK OFF OF VIO AND IS OPEN DRAIN)
V_OH	High-level output voltage		0.8			V_IO
V_OL	Low-level output voltage				0.2	V_IO
nWKRQ OUTPUT TERMINAL (DEFAULT INTERNAL VOLTAGE RAIL)
V_OH	High-level output voltage	Default value when based upon internal voltage rail	2.8		3.6	V
V_OL	Low-level output voltage	Default value when based upon internal voltage rail			0.7	V
OSC1 TERMINAL AND CRYSTAL SPECIFICATION
V_IH	High-level input voltage		0.85		1.10	V_IO
V_IL	Low-level input voltage				0.3	V_IO
F_OSC1	Clock-In frequency tolerance , see section Section 9.1.1	20 MHz	–0.5		0.5	%
F_OSC1	Clock-In frequency tolerance, see section Section 9.1.1	40 MHz	–0.5		0.5	%
t_DC	Input duty cycle		45		55	%
ESR	Crystal ESR for load capacitance ⁽²⁾				60	Ω

(1) All TXD_INT, RXD_INT and EN_INT references are for internal nodes that represent the same functions for a physical layer transceiver.

(2) Specified by design

6.8 Timing Requirements

over operating free-air temperature range for – 40 ℃ ≤ T_A ≤ 125 ℃ (unless otherwise noted)

		MAX	UNIT
MODE CHANGE TIMES (FULL DEVICE)
t_{MODE_STBY_NOM}	Standby to normal mode change time based upon SPI write	70	µs
t_{MODE_NOM_SLP}	SPI write to go to Sleep from Normal: INH and nWKRQ turned off, See Figure 7-15	200	µs
t_{MODE_SLP_STBY}	WUP or LWU event until INH and nWKRQ asserted, See Figure 7-14	200	µs
t_{MODE_SLP_STBY_VCCOUT_ON}	WUP or LWU event until V_CCOUT on, See Figure 7-14	1.5	ms
t_{MODE_NOM_STBY}	SPI write to go to standby from normal mode, See Figure 7-16	200	µs

6.9 Switching Characteristics

over operating free-air temperature range for – 40 ℃ ≤ T_A ≤ 125 ℃ (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SWITCHING CHARACTERISTICS (CAN TRANSCEIVER ONLY)
t_pHR	Propagation delay time, high TXD_INT to Driver Recessive ⁽¹⁾	See Figure 7-4, RST = 0 V. Typical conditions: R_L = 60 Ω, C_L = 100 pF, R_CM = open	50	85	110	ns
t_pLD	Propagation delay time, low TXD_INT to driver dominant ⁽¹⁾		35	75	100	ns
t_sk(p)	Pulse skew (\|t_pHR – t_pLD\|)			30	40	ns
t_R/F	Differential output signal rise time:		8	55	75	ns
t_pRH	Propagation delay time, bus recessive input to high RXD_INT output	See Figure 7-5, typical conditions: CANL = 1.5 V, CANH = 3.5 V.	35	55	90	ns
t_pDL	Propagation delay time, bus dominant input to RXD_INT low output		35	55	90	ns
DEVICE SWITCHING CHARACTERISTICS
t_LOOP	Loop delay⁽³⁾(CAN transceiver only)	See Figure 7-6, RST = 0 V. typical conditions: R_L = 60 Ω, C_L = 100 pF, C_RXD = 15 pF			235	ns
t_{WK_FILTER}	Bus time to meet filtered bus requirements for wake up request	See Figure 8-6, standby mode.	0.5		1.8	µs
t_{WK_TIMEOUT}	Bus wake-up timeout: time that a WUP must take place within to be considered valid	See Figure 8-6	0.5		2.9	ms
t_SILENCE	Timeout for bus inactivity ⁽⁶⁾	Timer is reset and restarted when bus changes from dominant to recessive or vice versa.	0.6		1.2	s
t_INACTIVE	Time required for the processor to clear wake flag or put the device into normal mode upon power up, power on reset or after wake event otherwise the device will enter sleep mode ⁽⁶⁾		2	4	6	min
t_Bias	Time from the start of a dominant-recessive-dominant sequence	Each phase 6 µs until V_sym ≥ 0.1. See Figure 7-10			250	µs
t_{Power_Up}	Power up time on V_SUP ⁽⁶⁾	See Figure 7-13			250	µs
t_{TXD_INT_DTO}	Dominant time out⁽²⁾ (CAN transceiver only)⁽¹⁾	See Figure 8-7, R_L = 60 Ω, C_L = open	1		5	ms
TRANSMITTER AND RECEIVER SWITCHING CHARACTERISTICS
t_Bit(Bus)2M	Transmitted recessive bit width @ 2 Mbps	See Figure 7-5, RST = 0 V typical conditions: R_L = 60 Ω, C_L = 100 pF, C_RXD = 15 pF	435		530	ns
t_Bit(Bus)5M	Transmitted recessive bit width @ 5 Mbps		155		210	ns
t_Bit(Bus)8M ⁽⁵⁾	Transmitted recessive bit width @ 8 Mbps	See Figure 7-5, RST = 0 V typical conditions: R_L = 60 Ω, C_L = 100 pF, C_RXD = 15 pF	80		135	ns
t_Bit(RXD)2M	Received recessive bit width @ 2 Mbps	See Figure 7-5, RST = 0 V typical conditions: R_L = 60 Ω, C_L = 100 pF, C_RXD = 15 pF,	400		550	ns
t_Bit(RXD)5M	Received recessive bit width @ 5 Mbps		120		220	ns
t_Bit(RXD)8M ⁽⁵⁾	Received recessive bit width @ 8 Mbps	See Figure 7-5, RST = 0 V typical conditions: R_L = 60 Ω, C_L = 100 pF, C_RXD = 15 pF	80		135	ns
Δt_Rec ⁽⁴⁾	Receiver Timing symmetry @ 2 Mbps	See Figure 7-5, RST = 0 V typical conditions: R_L = 60 Ω, C_L = 100 pF, C_RXD = 15 pF	–65	30	40	ns
Δt_Rec ⁽⁴⁾	Receiver Timing symmetry @ 5 Mbps		–45	5	15	ns
SPI SWITCHING CHARACTERISTICS
f_SCK	SCK, SPI clock frequency ⁽⁶⁾				18	MHz
t_SCK	SCK, SPI clock period ⁽⁶⁾	See Figure 7-12	56			ns
t_RSCK	SCK rise time ⁽⁶⁾	See Figure 7-11			10	ns
t_FSCK	SCK fall time ⁽⁶⁾	See Figure 7-11			10	ns
t_SCKH	SCK, SPI clock high ⁽⁶⁾	See Figure 7-12	18			ns
t_SCKL	SCK, SPI clock low ⁽⁶⁾	See Figure 7-12	18			ns
t_CSS	Chip select setup time ⁽⁶⁾	See Figure 7-11	28			ns
t_CSH	Chip select hold time ⁽⁶⁾	See Figure 7-11	28			ns
t_CSD	Chip select disable time ⁽⁶⁾	See Figure 7-11	125			ns
t_SISU	Data in setup time ⁽⁶⁾	See Figure 7-11	5			ns
t_SIH	Data in hold time ⁽⁶⁾	See Figure 7-11	10			ns
t_SOV	Data out valid ⁽⁶⁾	V_IO = 3.135 V to 5.25 V, See Figure 7-12			20	ns
t_RSO	SO rise time ⁽⁶⁾	See Figure 7-12			10	ns
t_FSO	SO fall time ⁽⁶⁾	See Figure 7-12			10	ns

(1) All TXD_INT, RXD_INT, EN_INT and CAN transceiver only references are for internal nodes that represent the same functions for a stand-alone transceiver.

(2) The TXD_INT dominant time out (t_{TXD_INT_DTO}) disables the driver of the transceiver once the TXD_INT has been dominant longer than t_{TXD_INT_DTO}, which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant again after TXD_INT has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD_INT) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the t_{TXD_INT_DTO} minimum, limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/ t_{TXD_INT_DTO} = 11 bits / 1.2 ms = 9.2 kbps.

(3) Time span from signal edge on TXD_INT input to next signal edge with same polarity on RXD output, the maximum of delay of both signal edges is to be considered.

(4) Δt_Rec = t_Bit(RXD) – t_Bit(Bus)

(5) Characterized but not 100% tested

(6) Specified by design

6.10 Typical Characteristics

V_CCOUT = 0 V

I_CCOUT = 0 mA

CAN Bus Load = 60 Ω

Figure 6-1 I_SUP vs V_SUP Sleep Mode

V_CCOUT = 5 V

I_CCOUT = 70 mA

CAN Transceiver Off

Figure 6-2 I_SUP Current Across Temperature and V_SUP LDO Output Only.

7 Parameter Measurement Information

Note:

All TXD_INT, RXD_INT and EN_INT references are for internal nodes that represent the same functions for a physical layer transceiver. In test mode these can be brought out to pins to test the transceiver or CAN FD controller.