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  • TCAN4550-Q1 带有集成控制器和收发器的汽车控制器区域网灵活数据速率 (CAN FD) 系统基础芯片

    • ZHCSJK5D January   2018  – June 2022 TCAN4550-Q1

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  • TCAN4550-Q1 带有集成控制器和收发器的汽车控制器区域网灵活数据速率 (CAN FD) 系统基础芯片
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specification
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  ESD Ratings, IEC ESD and ISO Transient Specification
    4. 6.4  Recommended Operating Conditions
    5. 6.5  Thermal Information
    6. 6.6  Supply Characteristics
    7. 6.7  Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VSUP Pin
      2. 8.3.2  VIO Pin
      3. 8.3.3  VCCOUT Pin
      4. 8.3.4  GND
      5. 8.3.5  INH Pin
      6. 8.3.6  WAKE Pin
      7. 8.3.7  FLTR Pin
      8. 8.3.8  RST Pin
      9. 8.3.9  OSC1 and OSC2 Pins
      10. 8.3.10 nWKRQ Pin
      11. 8.3.11 nINT Interrupt Pin
      12. 8.3.12 GPIO1 Pin
      13. 8.3.13 GPO2 Pin
      14. 8.3.14 CANH and CANL Bus Pins
    4. 8.4 Device Functional Modes
      1. 8.4.1 Normal Mode
      2. 8.4.2 Standby Mode
      3. 8.4.3 Sleep Mode
        1. 8.4.3.1 Bus Wake via RXD_INT Request (BWRR) in Sleep Mode
        2. 8.4.3.2 Local Wake-Up (LWU) via WAKE Input Terminal
      4. 8.4.4 Test Mode
      5. 8.4.5 Failsafe Feature
      6. 8.4.6 Protection Features
        1. 8.4.6.1 Watchdog Function
        2. 8.4.6.2 Driver and Receiver Function
        3. 8.4.6.3 Floating Terminals
        4. 8.4.6.4 TXD_INT Dominant Timeout (DTO)
        5. 8.4.6.5 CAN Bus Short Circuit Current Limiting
        6. 8.4.6.6 Thermal Shutdown
        7. 8.4.6.7 Under-Voltage Lockout (UVLO) and Unpowered Device
          1. 8.4.6.7.1 UVSUP and UVCCOUT
          2. 8.4.6.7.2 UVIO
          3. 8.4.6.7.3 Fault and M_CAN Core Behavior:
      7. 8.4.7 CAN FD
    5. 8.5 Programming
      1. 8.5.1 SPI Communication
        1. 8.5.1.1 Chip Select Not (nCS):
        2. 8.5.1.2 SPI Clock Input (SCLK):
        3. 8.5.1.3 SPI Data Input (SDI):
        4. 8.5.1.4 SPI Data Output (SDO):
      2. 8.5.2 Register Descriptions
    6. 8.6 Register Maps
      1. 8.6.1 Device ID and Interrupt/Diagnostic Flag Registers: 16'h0000 to 16'h002F
        1. 8.6.1.1 DEVICE_ID1[31:0] (address = h0000) [reset = h4E414354]
        2. 8.6.1.2 DEVICE_ID2[31:0] (address = h0004) [reset = h30353534]
        3. 8.6.1.3 Revision (address = h0008) [reset = h00110201]
        4. 8.6.1.4 Status (address = h000C) [reset = h0000000U]
        5. 8.6.1.5 SPI Error status mask (address = h0010) [reset = h00000000]
      2. 8.6.2 Device Configuration Registers: 16'h0800 to 16'h08FF
        1. 8.6.2.1 Modes of Operation and Pin Configuration Registers (address = h0800) [reset = hC8000468]
        2. 8.6.2.2 Timestamp Prescaler (address = h0804) [reset = h00000002]
        3. 8.6.2.3 Test Register and Scratch Pad (address = h0808) [reset = h00000000]
        4. 8.6.2.4 Test Register (address = h080C) [reset = h00000000]
      3. 8.6.3 Interrupt/Diagnostic Flag and Enable Flag Registers: 16'h0820/0824 and 16'h0830
        1. 8.6.3.1 Interrupts (address = h0820) [reset = h00100000]
        2. 8.6.3.2 MCAN Interrupts (address = h0824) [reset = h00000000]
        3. 8.6.3.3 Interrupt Enables (address = h0830 ) [reset = hFFFFFFFF]
      4. 8.6.4 CAN FD Register Set: 16'h1000 to 16'h10FF
        1. 8.6.4.1  Core Release Register (address = h1000) [reset = hrrrddddd]
        2. 8.6.4.2  Endian Register (address = h1004) [reset = h87654321]
        3. 8.6.4.3  Customer Register (address = h1008) [reset = h00000000]
        4. 8.6.4.4  Data Bit Timing & Prescaler (address = h100C) [reset = h0000A33]
        5. 8.6.4.5  Test Register (address = h1010 ) [reset = h00000000]
        6. 8.6.4.6  RAM Watchdog (address = h1014) [reset = h00000000]
        7. 8.6.4.7  Control Register (address = h1018) [reset = 0000 0019]
        8. 8.6.4.8  Nominal Bit Timing & Prescaler Register (address = h101C) [reset = h06000A03]
        9. 8.6.4.9  Timestamp Counter Configuration (address = h1020) [reset = h00000000]
        10. 8.6.4.10 Timestamp Counter Value (address = h1024) [reset = h00000000]
        11. 8.6.4.11 Timeout Counter Configuration (address = h1028) [reset = hFFFF0000]
        12. 8.6.4.12 Timeout Counter Value (address = h102C) [reset = h0000FFFF]
        13. 8.6.4.13 Reserved (address = h1030 - h103C) [reset = h00000000]
        14. 8.6.4.14 Error Counter Register (address = h1040) [reset = h00000000]
        15. 8.6.4.15 Protocol Status Register (address = h1044) [reset = h00000707]
        16. 8.6.4.16 Transmitter Delay Compensation Register (address = h1048) [reset = h00000000]
        17. 8.6.4.17 Reserved (address = h104C) [reset = h00000000]
        18. 8.6.4.18 Interrupt Register (address = h1050) [reset = h00000000]
        19. 8.6.4.19 Interrupt Enable (address = h1054) [reset = h00000000]
        20. 8.6.4.20 Interrupt Line Select (address = h1058) [reset = h00000000]
        21. 8.6.4.21 Interrupt Line Enable (address = h105C) [reset = h00000000]
        22. 8.6.4.22 Reserved (address = h1060 - h107C) [reset = h00000000]
        23. 8.6.4.23 Global Filter Configuration (address = h1080) [reset = h00000000]
        24. 8.6.4.24 Standard ID Filter Configuration (address = h1084) [reset = h00000000]
        25. 8.6.4.25 Extended ID Filter Configuration (address = h1088) [reset = h00000000]
        26. 8.6.4.26 Reserved (address = h108C) [reset = h00000000]
        27. 8.6.4.27 Extended ID AND Mask (address = h1090) [reset = h1FFFFFFF]
        28. 8.6.4.28 High Priority Message Status (address = h1094) [reset = h00000000]
        29. 8.6.4.29 New Data 1 (address = h1098) [reset = h00000000]
        30. 8.6.4.30 New Data 2 (address = h109C) [reset = h00000000]
        31. 8.6.4.31 Rx FIFO 0 Configuration (address = h10A0) [reset = h00000000]
        32. 8.6.4.32 Rx FIFO 0 Status (address = h10A4) [reset = h00000000]
        33. 8.6.4.33 Rx FIFO 0 Acknowledge (address = h10A8) [reset = h00000000]
        34. 8.6.4.34 Rx Buffer Configuration (address = h10AC) [reset = h00000000]
        35. 8.6.4.35 Rx FIFO 1 Configuration (address = h10B0) [reset = h00000000]
        36. 8.6.4.36 Rx FIFO 1 Status (address = h10B4) [reset = h00000000]
        37. 8.6.4.37 Rx FIFO 1 Acknowledge (address = h10B8) [reset = h00000000]
        38. 8.6.4.38 Rx Buffer/FIFO Element Size Configuration (address = h10BC) [reset = h00000000]
        39. 8.6.4.39 Tx Buffer Configuration (address = h10C0) [reset = h00000000]
        40. 8.6.4.40 Tx FIFO/Queue Status (address = h10C4) [reset = h00000000]
        41. 8.6.4.41 Tx Buffer Element Size Configuration (address = h10C8) [reset = h00000000]
        42. 8.6.4.42 Tx Buffer Request Pending (address = h10CC) [reset = h00000000]
        43. 8.6.4.43 Tx Buffer Add Request (address = h10D0) [reset = h00000000]
          1. 8.6.4.43.1  Tx Buffer Cancellation Request (address = h10D4 [reset = h00000000]
          2. 8.6.4.43.2  Tx Buffer Add Request Transmission Occurred (address = h10D8) [reset = h00000000]
          3. 8.6.4.43.3  Tx Buffer Cancellation Finished (address = h10DC) [reset = h00000000]
          4. 8.6.4.43.4  Tx Buffer Transmission Interrupt Enable (address = h10E0) [reset = h00000000]
          5. 8.6.4.43.5  Tx Buffer Cancellation Finished Interrupt Enable (address = h10E4) [reset = h00000000]
          6. 8.6.4.43.6  Reserved (address = h10E8) [reset = h00000000]
          7. 8.6.4.43.7  Reserved (address = h10EC) [reset = h00000000]
          8. 8.6.4.43.8  Tx Event FIFO Configuration (address = h10F0) [reset = h00000000]
          9. 8.6.4.43.9  Tx Event FIFO Status (address = h10F4) [reset = h00000000]
          10. 8.6.4.43.10 Tx Event FIFO Acknowledge (address = h10F8) [reset = h00000000]
          11. 8.6.4.43.11 Reserved (address = h10FC) [reset = h00000000]
  9. 9 Application and Implementation
    1. 9.1 Application Design Consideration
      1. 9.1.1 Crystal and Clock Input Requirements
      2. 9.1.2 Bus Loading, Length and Number of Nodes
      3. 9.1.3 CAN Termination
        1.       Termination
        2. 9.1.3.1 CAN Bus Biasing
      4. 9.1.4 INH Brownout Behavior
    2. 9.2 Typical Application
      1. 9.2.1 Detailed Requirements
      2. 9.2.2 Detailed Design Procedures
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 Documentation Support
      1. 12.1.1 Related Documentation
        1. 12.1.1.1 CAN Transceiver Physical Layer Standards:
        2. 12.1.1.2 EMC requirements:
        3. 12.1.1.3 Conformance Test requirements:
        4. 12.1.1.4 Support Documents
    2. 12.2 接收文档更新通知
    3. 12.3 支持资源
    4. 12.4 Trademarks
    5. 12.5 Electrostatic Discharge Caution
    6. 12.6 术语表
  13. 13Mechanical, Packaging, and Orderable Information
  14. 重要声明
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DATA SHEET

TCAN4550-Q1 带有集成控制器和收发器的汽车控制器区域网灵活数据速率 (CAN FD) 系统基础芯片

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 符合面向汽车应用的 AEC-Q100 标准
    • 温度等级 1：–40°C 至 125°C，TA
  • 功能安全质量管理型
    • 有助于进行功能安全系统设计的文档
  • 带有集成 CAN FD 收发器和串行外设接口 (SPI) 的 CAN FD 控制器
  • CAN FD 控制器支持 ISO 11898-1:2015 和 Bosch M_CAN 修订版 3.2.1.1
  • 符合 ISO 11898-2:2016 的要求
  • 支持 CAN FD 数据速率高达 8Mbps，且 SPI 时钟速率高达 18MHz
  • 向后兼容经典 CAN
  • 工作模式：正常、待机、睡眠和失效防护
  • 为微处理器提供 3.3V 至 5V 输入/输出逻辑支持
  • 在 CAN 总线上具有宽工作范围
    • ±58V 总线故障保护
    • ±12V 共模电压
  • 集成的低压降稳压器为 CAN 收发器提供 5V 电压，并为外部器件提供高达 70mA 的电流
  • 优化了未上电时的性能
    • 总线和逻辑终端为高阻抗
      （运行总线或应用上无负载）
    • 上电和断电无干扰运行

2 应用

  • 车身电子装置和照明
  • 信息娱乐系统与仪表组
  • 工业运输

3 说明

TCAN4550-Q1 是带有集成 CAN FD 收发器的 CAN FD 控制器，支持高达 8Mbps 的数据速率。此 CAN FD 控制器符合 ISO11898-1:2015 高速控制器局域网 (CAN) 数据链路层的规范，并满足 ISO11898–2:2016 高速 CAN 规范的物理层要求。

TCAN4550-Q1 通过串行外设接口 (SPI) 在 CAN 总线和系统处理器之间提供了一个接口，同时支持经典 CAN 和 CAN FD，并为不支持 CAN FD 的处理器提供端口扩展或 CAN 支持。TCAN4550-Q1 提供 CAN FD 收发器功能：传输到总线的差分传输能力和从总线接收的差分接收能力。该器件支持通过本地唤醒 (LWU) 进行唤醒以及使用实现 ISO11898-2:2016 唤醒模式 (WUP) 的 CAN 总线进行总线唤醒。

为了保证器件和 CAN 总线的稳健耐用性，此器件包括很多保护特性。这些特性包括失效防护模式、内部显性状态超时、宽总线工作范围和超时看门狗，等等。

器件信息
器件型号封装(1)封装尺寸（标称值）
TCAN4550-Q1VQFN (20)4.50mm x 3.50mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
GUID-20210920-SS0I-5NV6-HXFJ-HDGZK2HKQCGQ-low.gif简化版原理图，CLKIN 来自 MCU
GUID-20210920-SS0I-PFCS-H1GC-2N7HHHCM4M7G-low.gif简化版原理图，晶振

4 Revision History

Changes from Revision C (October 2020) to Revision D (June 2022)

  • 更改了数据表标题Go
  • 通篇将英文的“wake up”（唤醒）更改为“wake-up”（唤醒）Go
  • Changed description of the OSCI (pin 1) and OSC2 (pin 2) in the Pin Functions tableGo
  • Added a second paragraph to the OSC1 and OSC2 Pins sectionGo
  • Changed register Timestamp Prescalar to: Timestamp Prescaler Go
  • Changed bit 23 from: RSVD to: SMS in Table 8-20 Go
  • Changed bit 9 description from: Transmission Completed to: Transmission Cancellation FinishedGo
  • Changed bit 32:24 to: 30:24 in Table 8-56 Go
  • Changed bullet: This is where the termination is split into two resistors, R5 and R6 To: This is where the termination is split into two resistors, R4 and R5 in the Layout Guidelines Go
  • Added bullet for R8 in the Layout Guidelines Go
  • Changed the Layout Example: added resistor R8 to Pin 1.Go

Changes from Revision B (November 2019) to Revision C (October 2020)

  • Changed UVSUP rising max from 5.9 to 5.7  and added min value of 5.2Go
  • Added UVSUP falling max value of 5.0Go
  • Changed bit 2:0 To: 3:0 in Table 8-29 Go

Changes from Revision A (April 2019) to Revision B (November 2019)

  • 添加了“功能安全质量管理型”首页项目符号Go
  • Changed VIO value IIL for SDI, SCK and nCS inputs in test conditions cell value from 0 V to 5.25 VGo
  • Changed Power Up Timing diagram VSUP ramp voltage level for INH turn on and timing.Go
  • Added INH Brownout Behavior section in Application section.Go

Changes from Revision * (October 2017) to Revision A (April 2019)

  • 将文档状态从预告信息 更改为量产 数据Go
  • Changed footnote Gauranteed to Specied throughout the electric table.Go
  • Added VIO values for tSOV.Go
  • Changed Power Up Timing diagram VSUP ramp voltage level for INH turn on and timing. Go
  • Deleted CLKOUT from the GPIO1 circuit in Figure 8-2 Go
  • Deleted CLKOUT: Off from Sleep Mode section in Figure 8-14 Go
  • Deleted CLKOUT: Off From Sleep Mode section in Figure 8-15 Go
  • Deleted bits 15 and 14 from GPO1_CONFIG from in Table 8-16 Go
  • Changed CLKOUT_GPIO1_CONFIG To: GPIO1_CONFIG for GPO1_CONFIG in Table 8-16 Go
  • Changed the name of offset 1048 From: TDCE To: TDCR Go

5 Pin Configuration and Functions

Figure 5-1 RGY Package
20 Pin (VQFN)
(Top View)
Table 5-1 Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
1 OSC1 I/O External crystal oscillator output or single-ended clock input
2 nWKRQ DO Wake request (active low)
3 GPIO1 DI/O Configurable input/output function pin through SPI
4 SCLK DI SPI clock input
5 SDI DI SPI target data input from controller output
6 SDO DO SPI target data output to controller input
7 nCS DI SPI chip select
8 nINT DO Interrupt pin to MCU (active low)
9 GPO2 DO Configurable output function pin through SPI
10 CANL HV Bus I/O Low level CAN bus line
11 CANH HV Bus I/O High level CAN bus line
12 WAKE HVI Wake input, high voltage input
13 GND GND Ground connection
14 VSUP HV Supply In Supply from battery
15 INH HVO Inhibit to control system voltage regulators and supplies (open drain)
16 VCCOUT Supply Out 5 V regulated output
17 VIO Supply In Digital I/O voltage supply
18 FLTR — Internal regulator filter, requires external capacitor to ground
19 RST DI Device reset
20 OSC2 I External crystal oscillator input; when using single-ended input clock to OSC1 this pin should be connected to ground.
(1) Note: DI = Digital Input; DO = Digital Output; HV = High Voltage; Thermal PAD and GND Pins must be soldered to GND

6 Specification

6.1 Absolute Maximum Ratings

over operating free-air temperature range for – 40 ℃ ≤ TA ≤ 125 ℃ (unless otherwise noted)(1)
MIN MAX UNIT
VSUP Supply voltage –0.3 42 V
VIO Supply voltage I/O level shifter –0.3 6 V
VCCOUT 5 V output supply –0.3 6 V
VBUS CAN bus I/O voltage (CANH, CANL) –58 58 V
VWAKE WAKE pin input voltage –0.3 42 V
VINH Inhibit pin output voltage –0.3 42 V
VLogic_Input Logic input terminal voltage –0.3 6 V
VSO Digital output terminal voltage –0.5 6 V
IO(SO) Digital output current 8 mA
IO(INH) Inhibit output current 4 mA
IO(WAKE) Wake current if due to ground shift V(WAKE) ≤ V(GND) – 0.3 V 3 mA
TJ Junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM) classification level 3A per AEC Q100-002 All terminal except for CANH and CANL. (1)  WAKE terminals which are with respect to ground only (2) ±4000 V
V(ESD) Electrostatic discharge Human body model (HBM) classification level H2 for CANH and CANL (2) ±15000 V
V(ESD) Electrostatic discharge Charged device model (CDM) classification level C5, per AEC Q100-011 All terminals ±750 V
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) Terminals stressed with respect to GND

6.3 ESD Ratings, IEC ESD and ISO Transient Specification

VALUE UNIT
V(ESD) Electrostatic discharge according to IBEE CAN EMC (1) Contact discharge ±8000 V
Air discharge ±15 000 V
V(ESD) Electrostatic discharge according to SAEJ2962-2 (2) Contact discharge ±8000 V
Air discharge ±15 000
ISO7637 Transients according to IBEE CAN EMC test spec CAN bus terminals (CANH and CANL), VSUP and WAKE (3) Pulse 1 -100
Pulse 2 75
Pulse 3a -150
Pulse 3b 100
(1) IEC 61000-4-2 is a system-level ESD test. Results given here are specific to the IBEE LIN EMC Test specification conditions per IEC TS 62228. Different system-level configurations may lead to different results
(2) SAEJ2962-2 Testing performed at 3rd party US3 approved EMC test facility, test report available upon request.
(3) ISO7637 is a system-level transient test. Results given here are specific to the IBEE CAN EMC Test specification conditions. Different system-level configurations may lead to different results.

6.4 Recommended Operating Conditions

over operating free-air temperature range for – 40 ℃ ≤ TA ≤ 125 ℃ (unless otherwise noted)
MIN TYP MAX UNIT
VSUP Supply voltage 5.5 30 V
VIO Logic pin supply voltage 3.135 5.25 V
IOH(DO) Digital terminal high-level output current –2 mA
IOL(DO) Digital terminal low-level output current 2 mA
IO (INH) INH output current 1 mA
C(FLTR) Filter pin capacitance See Section 10 300 nF
C(VCCOUT) VCCOUT supply capacitance See Section 10 10 µF
CWAKE External WAKE pin capacitance 10 nF
TSDR Thermal shutdown rising 160 ℃
TSDF Thermal shutdown falling 150 ℃
TSD(HYS) Thermal shutdown hysteresis 10 ℃

6.5 Thermal Information

THERMAL METRIC(1) TCAN4550 UNIT
PKG DES (RGY)
20 PINS
RθJA Junction-to-ambient thermal resistance 35.2 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 28.1 °C/W
RθJB Junction-to-board thermal resistance 12.8 °C/W
ΨJT Junction-to-top characterization parameter 0.3 °C/W
ΨJB Junction-to-board characterization parameter 12.7 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 1.1 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.6 Supply Characteristics

over operating free-air temperature range for – 40 ℃ ≤ TA ≤ 125 ℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ISUP Supply current, normal mode Dominant See Figure 7-3 RL = 60 Ω, CL = open. typical bus load. VCCOUT = no load 80 mA
See Figure 7-3 RL = 50 Ω, CL = open, high bus load. VCCOUT = no load 90 mA
Dominant with bus fault See Figure 7-3 CANH = - 25 V, RL = open, CL = open VCCOUT = no load 180 mA
Recessive See Figure 7-3 RL = 60 Ω, CL = open, RCM = open, VCCOUT = no load 15 mA
Supply current, standby mode See Figure 7-3 RL = 60 Ω, CL = open, -40°C < TA < 85°C, VCCOUT = no load, CANH/L terminated to 2.5 V 3.5 mA
See Figure 7-3 RL = 60 Ω, CL = open, -40°C < TA < 85°C, VCCOUT = no load CANH/L terminated to GND ± 100 mV 3.4 mA
ISUP Supply current, sleep mode SPI bus, OSC/CLKIN disabled: -40°C < TA < 85°C, VIO = 0 25 42 µA
IVIO I/O supply current normal mode dominant I/O supply current CLKIN = 40 MHz, VIO = 5 V 800 µA
Crystal = 40 MHz, VIO = 5 V 3 mA
IVIO I/O supply current, sleep mode I/O supply current Sleep Mode VIO = 5 V; OSC1 = CLKIN = 0 V and OSC2 = GND (2) 9 µA
IVCCOUT VCCOUT supply current Normal Mode: VCCOUT = 5 V; -40°C < TA < 85°C See Section Section 8.3.3 70 mA
UVSUP Under voltage detection on VSUP rising ramp for protected mode See Section Section 8.4.6.7 5.2 5.5 5.7 V
Under voltage detection on VSUP falling ramp for protected mode 4.5 4.7 5.0 V
UVIO Under voltage detection on VIO rising ramp for protected mode See Section Section 8.4.6.7 2.45 2.6 V
Under voltage detection on VIO falling ramp for protected mode 2.1 2.25 V
tUV/TSD Under voltage filter time and thermal shutdown timer (1) Upon a UVIO event this timer starts and provides time for VIO input to return. See section Section 8.4.6.6 for description of thermal shut down. 200 500 ms
(1) Specified by design
(2) When a crystal is used this current will be higher until the crystal's capacitors bleed off their energy. How much current and length of time to bleed of the energy is system dependent and will not be specified. 

6.7 Electrical Characteristics

over operating free-air temperature range for – 40 ℃ ≤ TA ≤ 125 ℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT
CAN DRIVER ELECTRICAL CHARACTERISTICS
VO(D) Bus output voltage (dominant) CANH See Figure 7-3 and Figure 7-4, TXD_INT = 0 V, EN = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open 2.75 4.5 V
Bus output voltage (dominant) CANL 0.5 2.25 V
VO(R) Bus output voltage (recessive) See Figure 7-1 and Figure 7-4, TXD_INT = VIO, RL = open (no load), RCM = open 2 2.5 3 V
V(DIFF) Maximum differential voltage rating See Figure 7-1 and Figure 7-4 –5.0 10 V
VO(STB) Bus output voltage (Standby Mode) CANH See Figure 7-1 and Figure 7-4, TXD_INT = VIO, RL = open (no load), RCM = open –0.1 0.1 V
Bus output voltage (Standby Mode) CANL –0.1 0.1 V
Bus output voltage (Standby Mode) CANH - CANL –0.2 0.2 V
VOD(D) Differential output voltage (dominant) See Figure 7-1 and Figure 7-4, TXD_INT = 0 V, 50 Ω ≤ RL ≤ 65 Ω, CL = open, RCM = open 1.5 3 V
See Figure 7-1 and Figure 7-4, TXD_INT = 0 V, 45 Ω ≤ RL ≤ 70 Ω, CL = open, RCM = open 1.4 3 V
See Figure 7-1 and Figure 7-4, TXD_INT = 0 V, RL = 2.24 kΩ, CL = open, RCM = open 1.5 5 V
VOD(R) Differential output voltage (recessive) See Figure 7-1 and Figure 7-4, TXD_INT = VIO, RL = 60 Ω, CL = open, RCM = open –120 12 mV
See Figure 7-1 and Figure 7-4, TXD_INT = VIO, RL = open (no load), CL = open, RCM = open –50 50 mV
VSYM Output symmetry (dominant or recessive)
( VO(CANH) + VO(CANL)) / VCC		 See Figure 7-1 and Figure 7-4, RL = 60 Ω, CL = open, RCM = open, C1 = 4.7 nF, TXD_INT - 250 kHZ, 1 MHz 0.9 1.1 V/V
VSYM_DC Output symmetry (dominant or recessive) (VCC – VO(CANH) – VO(CANL)) with a frequency that corresponds to the highest bit rate for which the HS-PMA implementation is intended, however, at most 1 MHz (2 Mbit/s) See Figure 7-1 and Figure 7-4, RL = 60 Ω, CL = open, RCM = open, C1 = 4.7 nF –300 300 mV
IOS_DOM Short-circuit steady-state output current, dominant See Figure 7-1 and Figure 7-8, -3.0 V ≤ VCANH ≤ 18.0 V, CANL = open, TXD_INT = 0 V –100 mA
See Figure 7-1 and Figure 7-8, -3.0 V ≤ VCANL ≤+18.0 V, CANH = open, TXD_INT = 0 V 100 mA
IOS_REC Short-circuit steady-state output current, recessive See Figure 7-1 and Figure 7-8, – 27 V ≤ VBUS ≤ 32 V, VBUS = CANH = CANL –5 5 mA
CAN RECEIVER ELECTRICAL CHARACTERISTICS
VITdom Receiver dominant state differential input voltage range, bus biasing active -12.0 V ≤ VCANL ≤ +12.0 V
-12.0 V ≤ VCANH ≤ +12.0 V  See Figure 7-5,  Table 8-3 		0.9 8 V
VITrec Receiver recessive state differential input voltage range bus biasing active –3.0 0.5 V
VHYS Hysteresis voltage for input-threshold, normal modes See Figure 7-5, Table 8-3 120 mV
VIT(ENdom) Receiver dominant state differential input voltage range, bus biasing inactive (VDiff) -12.0 V ≤ VCANL ≤ +12.0 V
-12.0 V ≤ VCANH ≤ +12.0 V See Figure 7-5,  Table 8-3 		1.15 8 V
VIT(ENrec) Receiver recessive state differential input voltage range, bus biasing inactive (VDiff) -12.0 V ≤ VCANL ≤ +12.0 V
-12.0 V ≤ VCANH ≤ +12.0 V See Figure 7-5,  Table 8-3 		–3 0.4 V
VCM Common mode range: normal See Figure 7-5, Table 8-3 –12 12 V
VCM(EN) Common mode range: standby mode See Figure 7-5, Table 8-3 –12 12 V
IIOFF(LKG) Power-off (unpowered) bus input leakage current VCANH = VCANL = 5 V, Vsup to GND via 0 Ω and 47 kΩ resistor 5 µA
CI Input capacitance to ground (CANH or CANL) 25 pF
CID Differential input capacitance 14 pF
RID Differential input resistance TXD_INT = VCCINT, normal mode: -2.0 V ≤ VCANH ≤+7.0 V; -2.0 V ≤VCANL ≤ + 7.0 V 60 100 kΩ
RIN Single ended Input resistance (CANH or CANL) -2.0 V ≤ VCANH ≤+7.0 V; -2.0 V ≤VCANL ≤ + 7.0 V 30 50 kΩ
RIN(M) Input resistance matching: [1 – (RIN(CANH) / (RIN(CANL))] × 100% VCANH = VCANL = 5.0 V –1 1 %
VCCOUT SUPPLY TERMINAL
VCCOUT 5 V output supply ICCOUT = -70 mA to 0 mA; VSUP = 5.5 V to 18 V; -40°C < TA < 85°C 4.75 5 5.25 V
VDROP Drop out voltage VCCOUT = 5 V, VSUP = 12 V, ICCOUT = 70 mA 300 500 mV
ΔVCC(ΔVSUP) Line regulation VSUP = 5.5 V to 30 V, ΔVCCOUT, ICCOUT = 10 mA 50 mV
ΔVCC(ΔVSUPL) Load regulation VSUP = 14 V,   ICCOUT = 1 mA to 70 mA, ΔVCCOUT, –40℃ ≤ TA ≤ 125℃ 60 mV
UVCCOUT Under voltage threshold on VCCOUT 4.2 4.55 V
FLTR TERMINAL
VMEASURE Voltage measured at FLTR pin 1.5 V
C(FLTR) Filter pin capacitor External filter capacitor 300 330 nF
INH OUTPUT TERMINAL (HIGH VOLTAGE OUTPUT)
ΔVH High-level voltage drop INH with respect to VSUP IINH = - 0.5 mA 0.5 1 V
ILKG(INH) Leakage current INH = 0 V, Sleep Mode –0.5 0.7 µA
WAKE INPUT TERMINAL (HIGH VOLTAGE INPUT)
VIH High-level input voltage Standby mode, WAKE pin enabled VSUP–2 V
VIL Low-level input voltage Standby mode, WAKE pin enabled VSUP–3 V
IIH High-level input current WAKE = VSUP–1 V –25 –15 µA
IIL Low-level input current WAKE = 1 V 15 25 µA
tWAKE WAKE filter time Wake up filter time from a wake edge on WAKE; standby, sleep mode 50 µs
SDI, SCK, GPIO1 INPUT TERMINALS
VIH High-level input voltage 0.7 VIO
VIL Low-level input voltage 0.3 VIO
IIH High-level input leakage current Inputs = VIO = 5.25 V –1 1 µA
IIL Low-level input leakage current Inputs = 0 V, VIO = 5.25 V   –100 –5 µA
CIN Input capacitance 18 MHz 10 12 pF
ILKG(OFF) Unpowered leakage current (SDI and SCK only) Inputs = 5.25 V, VIO = VSUP = 0 V –1 1 µA
nCS INPUT TERMINAL
VIH High-level input voltage 0.7  VIO
VIL Low-level input voltage 0.3  VIO
IIH High-level input leakage current nCS = VIO = 5.25 V –1 1 µA
IIL Low-level input leakage current nCS = VIO = 5.25 V –50 –5 µA
ILKG(OFF) Unpowered leakage current nCS = 5.25 V, VIO = VSUP = 0 V –1 1 µA
RST INPUT TERMINAL
VIH High-level input voltage 0.7 VIO
VIL Low-level input voltage 0.3 VIO
IIH High-level input leakage current RST = VIO = 5.25 V 1 10 µA
IIL Low-level input leakage current RST = 0 V –1 1 µA
ILKG(OFF) Unpowered leakage current RST = VIO, VSUP = 0 V –7.5 7.5 µA
tPULSE_WIDTH Width of the input pulse 30 µs
SDO, GPIO1, GPO2 OUTPUT TERMINAL; nINT (OPEN DRAIIN) and nWKRQ (WHEN PROGRAMMED TO WORK OFF OF VIO AND IS OPEN DRAIN)
VOH High-level output voltage 0.8  VIO
VOL Low-level output voltage 0.2  VIO
nWKRQ OUTPUT TERMINAL (DEFAULT INTERNAL VOLTAGE RAIL)
VOH High-level output voltage Default value when based upon internal voltage rail 2.8 3.6 V
VOL Low-level output voltage Default value when based upon internal voltage rail 0.7 V
OSC1 TERMINAL AND CRYSTAL SPECIFICATION
VIH High-level input voltage 0.85 1.10 VIO
VIL Low-level input voltage 0.3 VIO
FOSC1 Clock-In frequency tolerance , see section Section 9.1.1   20 MHz –0.5 0.5 %
FOSC1 Clock-In frequency tolerance, see section Section 9.1.1 40 MHz –0.5 0.5 %
tDC Input duty cycle 45 55 %
ESR Crystal ESR for load capacitance (2) 60 Ω
(1) All TXD_INT, RXD_INT and EN_INT references are for internal nodes that represent the same functions for a physical layer transceiver.
(2) Specified by design

6.8 Timing Requirements

over operating free-air temperature range for – 40 ℃ ≤ TA ≤ 125 ℃ (unless otherwise noted)
MIN TYP MAX UNIT
MODE CHANGE TIMES (FULL DEVICE)
tMODE_STBY_NOM Standby to normal mode change time based upon SPI write 70 µs
tMODE_NOM_SLP SPI write to go to Sleep from Normal: INH and nWKRQ turned off, See Figure 7-15 200 µs
tMODE_SLP_STBY WUP or LWU event until INH and nWKRQ asserted, See Figure 7-14 200 µs
tMODE_SLP_STBY_VCCOUT_ON WUP or LWU event until VCCOUT on, See Figure 7-14 1.5 ms
tMODE_NOM_STBY SPI write to go to standby from normal mode, See Figure 7-16 200 µs

6.9 Switching Characteristics

over operating free-air temperature range for – 40 ℃ ≤ TA ≤ 125 ℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SWITCHING CHARACTERISTICS (CAN TRANSCEIVER ONLY)
tpHR Propagation delay time, high TXD_INT to Driver Recessive (1) See Figure 7-4, RST = 0 V. Typical conditions: RL = 60 Ω, CL = 100 pF, RCM = open 50 85 110 ns
tpLD Propagation delay time, low TXD_INT to driver dominant (1) 35 75 100 ns
tsk(p) Pulse skew (|tpHR – tpLD|) 30 40 ns
tR/F Differential output signal rise time: 8 55 75 ns
tpRH Propagation delay time, bus recessive input to high RXD_INT output See Figure 7-5, typical conditions: CANL = 1.5 V, CANH = 3.5 V. 35 55 90 ns
tpDL Propagation delay time, bus dominant input to RXD_INT low output 35 55 90 ns
DEVICE SWITCHING CHARACTERISTICS
tLOOP Loop delay(3)(CAN transceiver only) See Figure 7-6, RST = 0 V. typical conditions: RL = 60 Ω, CL = 100 pF, CRXD = 15 pF 235 ns
tWK_FILTER Bus time to meet filtered bus requirements for wake up request See Figure 8-6, standby mode. 0.5 1.8 µs
tWK_TIMEOUT Bus wake-up timeout: time that a WUP must take place within to be considered valid See Figure 8-6 0.5 2.9 ms
tSILENCE Timeout for bus inactivity (6) Timer is reset and restarted when bus changes from dominant to recessive or vice versa. 0.6 1.2 s
tINACTIVE Time required for the processor to clear wake flag or put the device into normal mode upon power up, power on reset or after wake event otherwise the device will enter sleep mode (6) 2 4 6 min
tBias Time from the start of a dominant-recessive-dominant sequence Each phase 6 µs until Vsym ≥ 0.1. See Figure 7-10 250 µs
tPower_Up Power up time on VSUP  (6) See Figure 7-13 250 µs
tTXD_INT_DTO Dominant time out(2) (CAN transceiver only)(1) See Figure 8-7, RL = 60 Ω, CL = open 1 5 ms
TRANSMITTER AND RECEIVER SWITCHING CHARACTERISTICS
tBit(Bus)2M Transmitted recessive bit width @ 2 Mbps See Figure 7-5, RST = 0 V typical conditions: RL = 60 Ω, CL = 100 pF, CRXD = 15 pF 435 530 ns
tBit(Bus)5M Transmitted recessive bit width @ 5 Mbps 155 210 ns
tBit(Bus)8M (5) Transmitted recessive bit width @ 8 Mbps See Figure 7-5, RST = 0 V typical conditions: RL = 60 Ω, CL = 100 pF, CRXD = 15 pF 80 135 ns
tBit(RXD)2M Received recessive bit width @ 2 Mbps See Figure 7-5, RST = 0 V typical conditions: RL = 60 Ω, CL = 100 pF, CRXD = 15 pF, 400 550 ns
tBit(RXD)5M Received recessive bit width @ 5 Mbps 120 220 ns
tBit(RXD)8M (5) Received recessive bit width @ 8 Mbps See Figure 7-5, RST = 0 V typical conditions: RL = 60 Ω, CL = 100 pF, CRXD = 15 pF 80 135 ns
ΔtRec (4) Receiver Timing symmetry @ 2 Mbps See Figure 7-5, RST = 0 V typical conditions: RL = 60 Ω, CL = 100 pF, CRXD = 15 pF –65 30 40 ns
Receiver Timing symmetry @ 5 Mbps –45 5 15 ns
SPI SWITCHING CHARACTERISTICS
fSCK SCK, SPI clock frequency (6) 18 MHz
tSCK SCK, SPI clock period (6) See Figure 7-12 56 ns
tRSCK SCK rise time (6) See Figure 7-11 10 ns
tFSCK SCK fall time (6) See Figure 7-11 10 ns
tSCKH SCK, SPI clock high (6) See Figure 7-12 18 ns
tSCKL SCK, SPI clock low (6) See Figure 7-12 18 ns
tCSS Chip select setup time (6) See Figure 7-11 28 ns
tCSH Chip select hold time (6) See Figure 7-11 28 ns
tCSD Chip select disable time (6) See Figure 7-11 125 ns
tSISU Data in setup time (6) See Figure 7-11 5 ns
tSIH Data in hold time (6) See Figure 7-11 10 ns
tSOV Data out valid (6) VIO = 3.135 V to 5.25 V, See Figure 7-12 20 ns
tRSO SO rise time (6) See Figure 7-12 10 ns
tFSO SO fall time (6) See Figure 7-12 10 ns
(1) All TXD_INT, RXD_INT, EN_INT and CAN transceiver only references are for internal nodes that represent the same functions for a stand-alone transceiver.
(2) The TXD_INT dominant time out (tTXD_INT_DTO) disables the driver of the transceiver once the TXD_INT has been dominant longer than tTXD_INT_DTO, which releases the bus lines to recessive, preventing a local failure from locking the bus dominant. The driver may only transmit dominant again after TXD_INT has been returned HIGH (recessive). While this protects the bus from local faults, locking the bus dominant, it limits the minimum data rate possible. The CAN protocol allows a maximum of eleven successive dominant bits (on TXD_INT) for the worst case, where five successive dominant bits are followed immediately by an error frame. This, along with the tTXD_INT_DTO minimum, limits the minimum bit rate. The minimum bit rate may be calculated by: Minimum Bit Rate = 11/ tTXD_INT_DTO = 11 bits / 1.2 ms = 9.2 kbps.
(3) Time span from signal edge on TXD_INT input to next signal edge with same polarity on RXD output, the maximum of delay of both signal edges is to be considered.
(4) ΔtRec = tBit(RXD) – tBit(Bus)
(5) Characterized but not 100% tested
(6) Specified by design

6.10 Typical Characteristics

GUID-781462EA-C576-4E25-B2F7-007B61FAC413-low.gif
VCCOUT = 0 VICCOUT = 0 mACAN Bus Load = 60 Ω
Figure 6-1 ISUP vs VSUP Sleep Mode
GUID-8B7B7B1E-384A-4E86-BF4F-708B67017560-low.gif
VCCOUT = 5 VICCOUT = 70 mACAN Transceiver Off
Figure 6-2 ISUP Current Across Temperature and VSUP LDO Output Only.

 
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