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  • MSP430FR247x 混合信号微控制器

    • ZHCSJG5C March   2019  – September 2021 MSP430FR2475 , MSP430FR2476

      PRODUCTION DATA  

  • CONTENTS
  • SEARCH
  • MSP430FR247x 混合信号微控制器
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 功能模块图
  5. 5 Revision History
  6. 6 Device Comparison
    1. 6.1 Related Products
  7. 7 Terminal Configuration and Functions
    1. 7.1 Pin Diagrams
    2. 7.2 Pin Attributes
    3. 7.3 Signal Descriptions
    4. 7.4 Pin Multiplexing
    5. 7.5 Buffer Types
    6. 7.6 Connection of Unused Pins
  8. 8 Specifications
    1. 8.1  Absolute Maximum Ratings
    2. 8.2  ESD Ratings
    3. 8.3  Recommended Operating Conditions
    4. 8.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 8.5  Active Mode Supply Current Per MHz
    6. 8.6  Low-Power Mode LPM0 Supply Currents Into VCC Excluding External Current
    7. 8.7  Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 8.8  Low-Power Mode LPMx.5 Supply Currents (Into VCC) Excluding External Current
    9. 8.9  Typical Characteristics – Low-Power Mode Supply Currents
    10. 8.10 Current Consumption Per Module
    11. 8.11 Thermal Resistance Characteristics
    12. 8.12 Timing and Switching Characteristics
      1. 8.12.1  Power Supply Sequencing
        1. 8.12.1.1 PMM, SVS and BOR
      2. 8.12.2  Reset Timing
        1. 8.12.2.1 Wake-up Times From Low-Power Modes and Reset
      3. 8.12.3  Clock Specifications
        1. 8.12.3.1 XT1 Crystal Oscillator (Low Frequency)
        2. 8.12.3.2 DCO FLL, Frequency
        3. 8.12.3.3 DCO Frequency
        4. 8.12.3.4 REFO
        5. 8.12.3.5 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        6. 8.12.3.6 Module Oscillator (MODOSC)
      4. 8.12.4  Digital I/Os
        1. 8.12.4.1 Digital Inputs
        2. 8.12.4.2 Digital Outputs
        3. 8.12.4.3 Typical Characteristics – Outputs at 3 V and 2 V
      5. 8.12.5  Internal Shared Reference
        1. 8.12.5.1 Internal Reference Characteristics
      6. 8.12.6  Timer_A and Timer_B
        1. 8.12.6.1 Timer_A
        2. 8.12.6.2 Timer_B
      7. 8.12.7  eUSCI
        1. 8.12.7.1 eUSCI (UART Mode) Clock Frequency
        2. 8.12.7.2 eUSCI (UART Mode) Timing Characteristics
        3. 8.12.7.3 eUSCI (SPI Master Mode) Clock Frequency
        4. 8.12.7.4 eUSCI (SPI Master Mode)
        5. 8.12.7.5 eUSCI (SPI Slave Mode)
        6. 8.12.7.6 eUSCI (I2C Mode)
      8. 8.12.8  ADC
        1. 8.12.8.1 ADC, Power Supply and Input Range Conditions
        2. 8.12.8.2 ADC, Timing Parameters
        3. 8.12.8.3 ADC, Linearity Parameters
      9. 8.12.9  Enhanced Comparator (eCOMP)
        1. 8.12.9.1 eCOMP0 Characteristics
      10. 8.12.10 FRAM
        1. 8.12.10.1 FRAM Characteristics
      11. 8.12.11 Debug and Emulation
        1. 8.12.11.1 JTAG, 4-Wire and Spy-Bi-Wire Interface
  9. 9 Detailed Description
    1. 9.1  Overview
    2. 9.2  CPU
    3. 9.3  Operating Modes
    4. 9.4  Interrupt Vector Addresses
    5. 9.5  Bootloader (BSL)
    6. 9.6  JTAG Standard Interface
    7. 9.7  Spy-Bi-Wire Interface (SBW)
    8. 9.8  FRAM
    9. 9.9  Memory Protection
    10. 9.10 Peripherals
      1. 9.10.1  Power-Management Module (PMM)
      2. 9.10.2  Clock System (CS) and Clock Distribution
      3. 9.10.3  General-Purpose Input/Output Port (I/O)
      4. 9.10.4  Watchdog Timer (WDT)
      5. 9.10.5  System (SYS) Module
      6. 9.10.6  Cyclic Redundancy Check (CRC)
      7. 9.10.7  Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0)
      8. 9.10.8  Timers (TA0, TA1, TA2, TA3 and TB0)
      9. 9.10.9  Hardware Multiplier (MPY)
      10. 9.10.10 Backup Memory (BAKMEM)
      11. 9.10.11 Real-Time Clock (RTC)
      12. 9.10.12 12-Bit Analog-to-Digital Converter (ADC)
      13. 9.10.13 eCOMP0
      14. 9.10.14 Embedded Emulation Module (EEM)
    11. 9.11 Input/Output Diagrams
      1. 9.11.1 Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 9.11.2 Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 9.11.3 Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 9.11.4 Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 9.11.5 Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      6. 9.11.6 Port P6 (P6.0 to P6.2) Input/Output With Schmitt Trigger
    12. 9.12 Device Descriptors
    13. 9.13 Memory
      1. 9.13.1 Memory Organization
      2. 9.13.2 Peripheral File Map
    14. 9.14 Identification
      1. 9.14.1 Revision Identification
      2. 9.14.2 Device Identification
      3. 9.14.3 JTAG Identification
  10. 10Applications, Implementation, and Layout
    1. 10.1 Device Connection and Layout Fundamentals
      1. 10.1.1 Power Supply Decoupling and Bulk Capacitors
      2. 10.1.2 External Oscillator
      3. 10.1.3 JTAG
      4. 10.1.4 Reset
      5. 10.1.5 Unused Pins
      6. 10.1.6 General Layout Recommendations
      7. 10.1.7 Do's and Don'ts
    2. 10.2 Peripheral- and Interface-Specific Design Information
      1. 10.2.1 ADC Peripheral
        1. 10.2.1.1 Partial Schematic
        2. 10.2.1.2 Design Requirements
        3. 10.2.1.3 Layout Guidelines
  11. 11Device and Documentation Support
    1. 11.1 Getting Started and Next Steps
    2. 11.2 Device Nomenclature
    3. 11.3 Tools and Software
    4. 11.4 Documentation Support
    5. 11.5 支持资源
    6. 11.6 Trademarks
    7. 11.7 Electrostatic Discharge Caution
    8. 11.8 Export Control Notice
    9. 11.9 术语表
  12. 12Mechanical, Packaging, and Orderable Information
  13. 重要声明
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DATA SHEET

MSP430FR247x 混合信号微控制器

本资源的原文使用英文撰写。 为方便起见,TI 提供了译文;由于翻译过程中可能使用了自动化工具,TI 不保证译文的准确性。 为确认准确性,请务必访问 ti.com 参考最新的英文版本(控制文档)。

1 特性

  • 嵌入式微控制器
    • 16 位 RISC 架构
    • 支持的时钟频率最高可达 16MHz
    • 1.8 V 至 3.6 V 的宽电源电压范围(最低电源电压受限于 SVS 电平,请参阅 SVS 规格)
  • 优化的超低功耗模式
    • 工作模式:135µA/MHz(典型值)
    • 待机:采用 32768Hz 晶振的 LPM3.5 实时时钟 (RTC) 计数器:660nA(典型值)
    • 关断 (LPM4.5):37nA,未使用 SVS
  • 低功耗铁电 RAM (FRAM)
    • 容量高达 64KB 的非易失性存储器
    • 内置错误修正码 (ECC)
    • 可配置的写保护
    • 对程序、常量和存储的统一存储
    • 耐写次数达 1015 次
    • 抗辐射和非磁性
  • 智能数字外设
    • 四个 16 位计时器,每个计时器有 3 个捕捉/比较寄存器 (Timer_A3)
    • 一个 16 位计时器,具有 7 个捕捉/比较寄存器 (Timer_B7)
    • 一个仅用作计数器的 16 位 RTC
    • 16 位循环冗余校验 (CRC)
  • 增强型串行通信,支持引脚重映射功能
    • 两个 eUSCI_A 接口,支持 UART、IrDA 和 SPI
    • 两个 eUSCI_B 接口,支持 SPI 和 I2C
  • 高性能模拟
    • 高达 12 通道 12 位模数转换器 (ADC)
      • 内部共享基准(1.5、2.0 或 2.5V)
      • 采样与保持 200ksps
    • 一个增强型比较器 (eCOMP)
      • 集成 6 位 DAC 作为基准电压
      • 可编程迟滞
      • 可配置的高功率和低功率模式
  • 时钟系统 (CS)
    • 片上 32kHz RC 振荡器 (REFO),具有 1µA 支持
    • 带有锁频环 (FLL) 的片上 16MHz 数控振荡器 (DCO)
      • 室温下的精度为 ±1%(具有片上基准)
    • 片上超低频 10kHz 振荡器 (VLO)
    • 片上高频调制振荡器 (MODOSC)
    • 外部 32kHz 晶振 (LFXT)
    • 可编程 MCLK 预分频器(1 至 128)
    • 通过可编程预分频器(1、2、4 或 8)从 MCLK 获得的 SMCLK
  • 通用输入/输出和引脚功能
    • LQFP-48 封装上的 43 个 I/O
    • 所有 GPIO 上的 43 个中断引脚可以将 MCU 从低功耗模式下唤醒
  • 开发工具和软件
    • 开发工具
      • 目标开发板 MSP‑TS430PT48A
      • LaunchPad™ 开发套件 LP‑MSP430FR2476
  • 系列成员(另请参阅器件比较)
    • MSP430FR2476:64KB 程序 FRAM、512B 信息 FRAM、8KB RAM
    • MSP430FR2475:32KB 程序 FRAM、512B 信息 FRAM、6KB RAM
  • 封装选项
    • 48 引脚:LQFP (PT)
    • 40 引脚:VQFN (RHA)
    • 32 引脚:VQFN (RHB)

2 应用

  • 小型工业传感器
  • 低功耗医疗、健康和健身器材
  • 电池组
  • EPOS
  • 电器
  • 恒温器
  • 电动牙刷
  • PC 配件

3 说明

MSP430FR247x 微控制器 (MCU) 是 MSP430™ MCU 超值系列超低功耗低成本器件产品系列的一部分,该产品系列用于检测和测量应用。MSP430FR247x MCU 集成了一个 12 位 SAR ADC 和一个比较器。所有 MSP430FR247x MCU 均支持 –40° 至 105°C 的工作温度范围,因此这些器件的 FRAM 数据记录功能对更高温度的工业应用来说意义重大。

MSP430FR247x MCU 由一系列由软、硬件组成的生态系统提供支持,并提供有参考设计和代码示例,可帮助您快速开展设计。开发套件包括 MSP-TS430PT48 48 引脚目标开发板。TI 还提供免费的 MSP430Ware™ 软件,该软件以 Code Composer Studio™ IDE 桌面和云版本组件的形式提供(位于 TI Resource Explorer 中)。我们为 MSP430 MCU 提供广泛的在线配套资料(例如内务处理型示例系列、MSP Academy 培训),也通过 TI E2E™ 支持论坛提供在线支持。

MSP430 超低功耗 (ULP) FRAM 微控制器平台将独特的嵌入式 FRAM 和整体超低功耗系统架构相结合,从而使系统设计人员能够在降低能耗的情况下提升性能。FRAM 技术将 RAM 的低功耗快速写入、灵活性和耐用性与闪存的非易失性相结合。

TI MSP430 系列低功耗微控制器包含多种器件,其中配备了不同的外设集以满足各类应用的需求。此架构与多种低功耗模式配合使用,是延长便携式测量应用电池寿命的最优选择。该 MCU 具有一个强大的 16 位 RISC CPU、16 位寄存器和常数发生器,有助于获得最大编码效率。数控振荡器 (DCO) 可使 MCU 在不到 10μs(典型值)的时间内从低功耗模式唤醒至活动模式。

有关完整的模块说明,请参阅 MSP430FR4xx 和 MSP430FR2xx 系列器件用户指南。

器件信息
器件型号(1) 封装 封装尺寸(2)
MSP430FR2476TPT LQFP (48) 7mm × 7mm
MSP430FR2475TPT LQFP (48) 7mm × 7mm
MSP430FR2476TRHA VQFN (40) 6mm × 6mm
MSP430FR2475TRHA VQFN (40) 6mm × 6mm
MSP430FR2476TRHB VQFN (32) 5mm x 5mm
MSP430FR2475TRHB VQFN (32) 5mm x 5mm
(1) 要获得最新的产品、封装和订购信息,请参阅Section 12中的封装选项附录,或者访问德州仪器 (TI) 网站 www.ti.com.cn。
(2) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸,请参阅机械数据(Section 12中)。
警告:

系统级静电放电 (ESD) 保护必须符合器件级 ESD 规范,以防发生电气过载或对数据或代码存储器造成干扰。如需更多信息,请参阅 MSP430 系统级 ESD 注意事项。

4 功能模块图

图 4-1 给出了功能方框图。

GUID-CD38CD46-F7AD-4255-9F43-8A484A0BB741-low.png图 4-1 功能模块图
  • MCU 的主电源对 DVCC 和 DVSS 分别为数字模块和模拟模块供电。推荐的旁路电容和去耦电容分别为 4.7μF 至 10μF 和 0.1μF,精度为 ±5%。
  • 所有 GPIO 均具备引脚中断功能,可将 MCU 从所有 LPM 模式唤醒。
  • 在 LPM3.5 模式下,RTC 模块可在其他外设停止工作的情况下继续工作。

5 Revision History

Changes from revision B to revision C

Changes from December 11, 2019 to September 14, 2021

  • 更新了整个文档中的表格、图和交叉参考的编号格式Go
  • 通篇更正了 MSP430FR2475 的 RAM 大小(从 4KB 更改为 6KB)Go
  • 在Section 3 说明 中添加了指向在线配套资料的链接Go
  • Corrected the pin numbers for the Veref+ and Veref- signals in Table 7-2, Signal Descriptions Go
  • Corrected the TAxRMP, USCIA0RMP, USCIB0RMP, and USCIB1RMP bit names in the notes for Table 7-2, Signal Descriptions Go
  • Corrected the USCIA0RMP and USCIBxRMP bit names in Section 9.10.7, Enhanced Universal Serial Communication Interface (eUSCI_A0, eUSCI_B0) Go
  • Corrected the TAxRMP bit name in the notes for Table 9-16, TA2 and TA3 Pin Configurations of Remap Functionality Go
  • Added an inverter to the Schmitt-trigger enable in Figure 9-4, Port Input/Output With Schmitt Trigger Go
  • Corrected the value of the P5SEL.x column for P5.3 and P5.4 in Table 9-27, Port P5 (P5.0 to P5.7) Pin Functions Go
  • Added the SYSCFG3 register to Table 9-35, SYS Registers (Base Address: 0140h) Go

Changes from revision A to revision B

Changes from April 26, 2019 to December 10, 2019

  • 更新了 Section 1 特性 Go
  • Changed the note that begins "Supply voltage changes faster than 0.2 V/µs can trigger a BOR reset..." in Section 8.3, Recommended Operating Conditions Go
  • Added the note that begins "TI recommends that power to the DVCC pin must not exceed the limits..." in Section 8.3, Recommended Operating Conditions Go
  • Changed the note that begins "A capacitor tolerance of ±20% or better is required..." in Section 8.3, Recommended Operating Conditions Go
  • Added the note "See MSP430 32-kHz Crystal Oscillators for details on crystal section, layout, and testing" to Section 8.12.3.1, XT1 Crystal Oscillator (Low Frequency) Go
  • Changed the note that begins "Requires external capacitors at both terminals..." in Section 8.12.3.1, XT1 Crystal Oscillator (Low Frequency) Go
  • Added the tTA,cap parameter in Section 8.12.6.1, Timer_A Go
  • Added the tTB,cap parameter in Section 8.12.6.2, Timer_B Go
  • Corrected the test conditions for the RI parameter in Section 8.12.8.1, ADC, Power Supply and Input Range Conditions Go
  • Removed ADCDIV from the equations for tCONVERT because ADCCLK is after division in Section 8.12.8.2, ADC, Timing Parameters Go
  • Added the note that begins "tSample = ln(2n+1) × τ ..." in Section 8.12.8.2, ADC, Timing Parameters Go
  • Changed CRC covered end address to 0x1AF7 in table note (1) in Table 9-30 , Device Descriptors Go

Changes from initial release to revision A

Changes from March 12, 2019 to April 25, 2019

  • 将文档状态更改为“量产数据”Go
  • 在图 4-1、功能方框图 中添加了 MSP430FR2673 和 MSP430FR2672 的存储器大小Go
  • Updated Section 8.7 Low-Power Mode (LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current with production values Go
  • Updated Section 8.12.3.2 DCO FLL, Frequency with production valuesGo

6 Device Comparison

Table 6-1 summarizes the features of the available family members.

Table 6-1 Device Comparison
DEVICE(1)(2) PROGRAM FRAM + INFORMATION FRAM (KB) SRAM (KB) TA0, TA1, TA2, TA3 TB0 eUSCI_A0
eUSCI_A1
eUSCI_B0
eUSCI_B1
12-BIT ADC CHANNELS eCOMP GPIOs PACKAGE
MSP430FR2476TPT 64 + 0.5 8 4, 3 × CCR(3) 1, 7 × CCR(4) 2 2 12 1 43 48 LQFP (PT)
MSP430FR2475TPT 32 + 0.5 6 4, 3 × CCR(3) 1, 7 × CCR(4) 2 2 12 1 43 48 LQFP (PT)
MSP430FR2476TRHA 64 + 0.5 8 4, 3 × CCR(3) 1, 7 × CCR(4) 2 2 10 1 35 40 VQFN (RHA)
MSP430FR2475TRHA 32 + 0.5 6 4, 3 × CCR(3) 1, 7 × CCR(4) 2 2 10 1 35 40 VQFN (RHA)
MSP430FR2476TRHB 64 + 0.5 8 4, 3 × CCR(3) 1, 7 × CCR(5) 2 2 8 1 27 32 VQFN (RHB)
MSP430FR2475TRHB 32 + 0.5 6 4, 3 × CCR (3) 1, 7 × CCR(5) 2 2 8 1 27 32 VQFN (RHB)
(1) For the most current package and ordering information, see the Package Option Addendum in Section 12, or see the TI website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging.
(3) A CCR register is a configurable register that provides internal and external capture or compare inputs, or internal and external PWM outputs. TA0 and TA1 are externally connected on CCR1, CCR2. TA2 and TA3 are externally connected on CCR0 to CCR2.
(4) A CCR register is a configurable register that provides internal and external capture or compare inputs, or internal and external PWM outputs. TB0 is externally connected on CCR0 to CCR6.
(5) A CCR register is a configurable register that provides internal capture only, CCR0 to CCR6 registers can only be used for period timing and interrupt generation, NO PWM outputs functionality.

6.1 Related Products

For information about other devices in this family of products or related products, see the following links.

Products for microcontrollers

Our diverse portfolio of 16- and 32-bit microcontrollers (MCUs) with real-time control capabilities and high-precision analog integration are optimized for industrial and automotive applications. Backed by decades of expertise and innovative hardware and software solutions, our MCUs can meet the needs of any design and budget.

Products for MSP430 microcontrollers

Our 16-bit MSP430™ microcontrollers (MCUs) provide affordable solutions for all applications. Our leadership in integrated precision analog enables designers to enhance system performance and lower system costs. Designers can find a cost-effective MCU within the broad MSP430 portfolio of over 2000 devices for virtually any need. Get started quickly and reduce time to market with our simplified tools, software, and best-in-class support.

Reference designs for MSP430FR2476

Find reference designs leveraging the best in TI technology – from analog and power management to embedded processors

7 Terminal Configuration and Functions

7.1 Pin Diagrams

Figure 7-1 shows the pinout of the 48-pin PT package.

GUID-B3BBE59A-B58A-484F-961B-BFC064B20540-low.gifFigure 7-1 48-Pin PT Package (Top View)

Figure 7-2 shows the pinout of the 40-pin RHA package.

GUID-15AC9E1A-592C-429A-A2EA-B92B7652D06D-low.gifFigure 7-2 40-Pin RHA Package (Top View)

Figure 7-3 shows the pinout of the 32-pin RHB package.

GUID-FE18EB8A-DE06-4A7E-ACAF-90CBC39BA343-low.gifFigure 7-3 32-Pin RHB Package (Top View)

7.2 Pin Attributes

Table 7-1 lists the attributes of all pins.

Table 7-1 Pin Attributes
PIN NUMBER SIGNAL NAME(1)(2) SIGNAL TYPE(3) BUFFER TYPE(4) POWER SOURCE(5) RESET STATE AFTER BOR(6)
PT RHA RHB
1 1 32 DVCC P Power DVCC N/A
2 2 1 RST (RD) I LVCMOS DVCC PU
NMI I LVCMOS DVCC –
SBWTDIO I/O LVCMOS DVCC –
3 3 2 TEST (RD) I LVCMOS DVCC PD
SBWTCK I LVCMOS DVCC –
4 4 3 P1.4 (RD) I/O LVCMOS DVCC OFF
UCA0TXD O LVCMOS DVCC –
UCA0SIMO I/O LVCMOS DVCC –
TA1.2 I/O LVCMOS DVCC –
TCK I LVCMOS DVCC –
A4 I Analog DVCC –
VREF+ O Power DVCC –
5 5 4 P1.5 (RD) I/O LVCMOS DVCC OFF
UCA0RXD I LVCMOS DVCC –
UCA0SOMI I/O LVCMOS DVCC –
TA1.1 I/O LVCMOS DVCC –
TMS I LVCMOS DVCC –
A5 I Analog DVCC –
6 6 5 P1.6 (RD) I/O LVCMOS DVCC OFF
UCA0CLK I/O LVCMOS DVCC –
TA1CLK I LVCMOS DVCC –
TDI I LVCMOS DVCC –
TCLK I LVCMOS DVCC –
A6 I Analog DVCC –
7 7 6 P1.7 (RD) I/O LVCMOS DVCC OFF
UCA0STE I/O LVCMOS DVCC –
SMCLK O LVCMOS DVCC –
TDO O LVCMOS DVCC –
A7 I Analog DVCC –
8 8 – P4.3 (RD) I/O LVCMOS DVCC OFF
UCB1SOMI I/O LVCMOS DVCC –
UCB1SCL I/O LVCMOS DVCC –
TB0.5 I/O LVCMOS DVCC –
A8 I Analog DVCC –
9 9 – P4.4 (RD) I/O LVCMOS DVCC OFF
UCB1SIMO I/O LVCMOS DVCC –
UCB1SDA I/O LVCMOS DVCC –
TB0.6 I/O LVCMOS DVCC –
A9 I Analog DVCC –
10 – – P5.3 (RD) I/O LVCMOS DVCC OFF
UCB1CLK I/O LVCMOS DVCC –
TA3.0 I/O LVCMOS DVCC –
A10 I Analog DVCC –
11 – – P5.4 (RD) I/O LVCMOS DVCC OFF
UCB1STE I/O LVCMOS DVCC –
TA3CLK I/O LVCMOS DVCC –
A11 I Analog DVCC –
12 10 7 P1.0 (RD) I/O LVCMOS DVCC OFF
UCB0STE I/O LVCMOS DVCC –
TA0CLK I LVCMOS DVCC –
A0 I Analog DVCC –
Veref+ I Power DVCC –
13 11 8 P1.1 (RD) I/O LVCMOS DVCC OFF
UCB0CLK I/O LVCMOS DVCC –
TA0.1 I/O LVCMOS DVCC –
A1 I Analog DVCC –
COMP0.0 I Analog DVCC –
14 12 9 P1.2 (RD) I/O LVCMOS DVCC OFF
UCB0SIMO I/O LVCMOS DVCC –
UCB0SDA I/O LVCMOS DVCC –
TA0.2 I/O LVCMOS DVCC –
A2 I Analog DVCC –
Veref- I Power DVCC –
15 13 10 P1.3 (RD) I/O LVCMOS DVCC OFF
UCB0SOMI I/O LVCMOS DVCC –
UCB0SCL I/O LVCMOS DVCC –
MCLK O LVCMOS DVCC –
A3 I Analog DVCC –
16 14 11 P2.2 (RD) I/O LVCMOS DVCC OFF
ACLK O LVCMOS DVCC –
COMP0.1 I Analog DVCC –
17 15 – P4.5 (RD) I/O LVCMOS DVCC OFF
UCB0SOMI I/O LVCMOS DVCC –
UCB0SCL I/O LVCMOS DVCC –
TA3.2 I/O LVCMOS DVCC –
18 16 – P4.6 (RD) I/O LVCMOS DVCC OFF
UCB0SIMO I/O LVCMOS DVCC –
UCB0SDA I/O LVCMOS DVCC –
TA3.1 I/O LVCMOS DVCC –
19 – – P5.5 (RD) I/O LVCMOS DVCC OFF
UCB0CLK I/O LVCMOS DVCC –
TA2CLK I/O LVCMOS DVCC –
20 – – P5.6 (RD) I/O LVCMOS DVCC OFF
UCB0STE I/O LVCMOS DVCC –
TA2.0 I/O LVCMOS DVCC –
21 – – P5.7 (RD) I/O LVCMOS DVCC OFF
TA2.1 I/O LVCMOS DVCC –
COMP0.2 I Analog DVCC –
22 – – P6.0 (RD) I/O LVCMOS DVCC OFF
TA2.2 I/O LVCMOS DVCC –
COMP0.3 I Analog DVCC –
23 17 12 P3.0 (RD) I/O LVCMOS DVCC OFF
TA2.2 I/O LVCMOS DVCC –
24 18 13 P3.3 (RD) I/O LVCMOS DVCC OFF
TA2.1 I/O LVCMOS DVCC –
25 19 14 P2.3 (RD) I/O LVCMOS DVCC OFF
TA2.0 I/O LVCMOS DVCC –
26 20 15 P3.4 (RD) I/O LVCMOS DVCC OFF
TA2CLK I/O LVCMOS DVCC –
COMP0OUT O LVCMOS DVCC –
27 21 16 P3.1 (RD) I/O LVCMOS DVCC OFF
UCA1STE I/O LVCMOS DVCC –
28 22 17 P2.4 (RD) I/O LVCMOS DVCC OFF
UCA1CLK I/O LVCMOS DVCC –
29 23 18 P2.5 (RD) I/O LVCMOS DVCC OFF
UCA1RXD I LVCMOS DVCC –
UCA1SOMI I/O LVCMOS DVCC –
30 24 19 P2.6 (RD) I/O LVCMOS DVCC OFF
UCA1TXD O LVCMOS DVCC –
UCA1SIMO I/O LVCMOS DVCC –
31 25 20 DNC(7) – – – –
32 26 21 P3.7 (RD) I/O LVCMOS DVCC OFF
TA3.2 I/O LVCMOS DVCC –
33 27 22 P4.0 (RD) I/O LVCMOS DVCC OFF
TA3.1 I/O LVCMOS DVCC –
34 28 23 P4.1 (RD) I/O LVCMOS DVCC OFF
TA3.0 I/O LVCMOS DVCC –
35 29 24 P4.2 (RD) I/O LVCMOS DVCC OFF
TA3CLK I/O LVCMOS DVCC –
36 30 25 P2.7 (RD) I/O LVCMOS DVCC OFF
UCB1STE I/O LVCMOS DVCC –
37 31 26 P3.5 (RD) I/O LVCMOS DVCC OFF
UCB1CLK I/O LVCMOS DVCC –
TB0TRG I LVCMOS DVCC –
38 32 27 P3.2 (RD) I/O LVCMOS DVCC OFF
UCB1SIMO I/O LVCMOS DVCC –
UCB1SDA I/O LVCMOS DVCC –
39 33 28 P3.6(RD) I/O LVCMOS DVCC OFF
UCB1SOMI I/O LVCMOS DVCC –
UCB1SCL I/O LVCMOS DVCC –
40 – – P6.1 (RD) I/O LVCMOS DVCC OFF
TB0CLK I/O LVCMOS DVCC –
41 – – P6.2 (RD) I/O LVCMOS DVCC OFF
TB0.0 I/O LVCMOS DVCC –
42 34 – P4.7 (RD) I/O LVCMOS DVCC OFF
UCA0STE I/O LVCMOS DVCC –
TB0.1 I/O LVCMOS DVCC –
43 35 – P5.0 (RD) I/O LVCMOS DVCC OFF
UCA0CLK I/O LVCMOS DVCC –
TB0.2 I LVCMOS DVCC –
44 36 – P5.1 (RD) I/O LVCMOS DVCC OFF
UCA0RXD I LVCMOS DVCC –
UCA0SOMI I/O LVCMOS DVCC –
TB0.3 I/O LVCMOS DVCC –
45 37 – P5.2 (RD) I/O LVCMOS DVCC OFF
UCA0TXD O LVCMOS DVCC –
UCA0SIMO I/O LVCMOS DVCC –
TB0.4 I/O LVCMOS DVCC –
46 38 29 P2.0 (RD) I/O LVCMOS DVCC OFF
XOUT O LVCMOS DVCC –
47 39 30 P2.1 (RD) I/O LVCMOS DVCC OFF
XIN I LVCMOS DVCC –
48 40 31 DVSS P Power DVCC N/A
(1) Signals names with (RD) denote the reset default pin name.
(2) To determine the pin mux encodings for each pin, see Section 9.11.
(3) Signal types: I = input, O = output, I/O = input or output
(4) Buffer types: LVCMOS, Analog, or Power (see Table 7-3)
(5) The power source shown in this table is the I/O power source, which may differ from the module power source.
(6) Reset States:
OFF = High impedance with Schmitt trigger and pullup or pulldown (if available) disabled
PU = Pullup is enabled
PD = Pulldown is enabled
N/A = Not applicable
(7) DNC = do not connect

7.3 Signal Descriptions

Table 7-2 describes the signals for all device variants and package options.

Table 7-2 Signal Descriptions
FUNCTION SIGNAL NAME PIN NUMBER PIN TYPE(1) DESCRIPTION
PT RHA RHB
ADC A0 12 10 7 I Analog input A0
A1 13 11 8 I Analog input A1
A2 14 12 9 I Analog input A2
A3 15 13 10 I Analog input A3
A4 4 4 3 I Analog input A4
A5 5 5 4 I Analog input A5
A6 6 6 5 I Analog input A6
A7 7 7 6 I Analog input A7
A8 8 8 – I Analog input A8
A9 9 9 – I Analog input A9
A10 10 – – I Analog input A10
A11 11 – – I Analog input A11
Veref+ 12 10 7 I ADC positive reference
Veref- 14 12 9 I ADC negative reference
eCOMP0 COMP0.0 13 11 8 I Enhanced comparator input channel C0
COMP0.1 16 14 11 I Enhanced comparator input channel C1
COMP0.2 21 – – I Enhanced comparator input channel C2
COMP0.3 22 – – I Enhanced comparator input channel C3
COMP0OUT 26 20 15 O Enhanced comparator output channel COUT
Clock ACLK 16 14 11 I/O ACLK output
MCLK 15 13 10 O MCLK output
SMCLK 7 7 6 O SMCLK output
XIN 47 39 30 I Input terminal for crystal oscillator
XOUT 46 38 29 O Output terminal for crystal oscillator
Debug SBWTCK 3 3 2 I Spy-Bi-Wire input clock
SBWTDIO 2 2 1 I/O Spy-Bi-Wire data input/output
TCK 4 4 3 I Test clock
TCLK 6 6 5 I Test clock input
TDI 6 6 5 I Test data input
TDO 7 7 6 O Test data output
TEST 3 3 2 I Test Mode pin – selected digital I/O on JTAG pins
TMS 5 5 4 I Test mode select
GPIO, Port 1 P1.0 12 10 7 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P1.1 13 11 8 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P1.2 14 12 9 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P1.3 15 13 10 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P1.4 4 4 3 I/O General-purpose I/O with port interrupt and wake from LPMx.5 (2)
P1.5 5 5 4 I/O General-purpose I/O with port interrupt and wake from LPMx.5(2)
P1.6 6 6 5 I/O General-purpose I/O with port interrupt and wake from LPMx.5(2)
P1.7 7 7 6 I/O General-purpose I/O with port interrupt and wake from LPMx.5(2)
GPIO, Port 2 P2.0 46 38 29 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P2.1 47 39 30 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P2.2 16 14 11 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P2.3 25 19 14 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P2.4 28 22 17 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P2.5 29 23 18 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P2.6 30 24 19 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P2.7 36 30 25 I/O General-purpose I/O with port interrupt and wake from LPMx.5
GPIO, Port 3 P3.0 23 17 12 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P3.1 27 21 16 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P3.2 38 32 27 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P3.3 24 18 13 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P3.4 26 20 15 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P3.5 37 31 26 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P3.6 39 33 28 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P3.7 32 26 21 I/O General-purpose I/O with port interrupt and wake from LPMx.5
GPIO, Port 4 P4.0 33 27 22 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P4.1 34 28 23 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P4.2 35 29 24 I/O General-purpose I/O with port interrupt and wake from LPMx.5
P4.3 8 8 – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P4.4 9 9 – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P4.5 17 15 – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P4.6 18 16 – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P4.7 42 34 – I/O General-purpose I/O with port interrupt and wake from LPMx.5
GPIO, Port 5 P5.0 43 35 – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P5.1 44 36 – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P5.2 45 37 – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P5.3 10 – – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P5.4 11 – – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P5.5 19 – – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P5.6 20 – – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P5.7 21 – – I/O General-purpose I/O with port interrupt and wake from LPMx.5
GPIO, Port 6 P6.0 22 – – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P6.1 40 – – I/O General-purpose I/O with port interrupt and wake from LPMx.5
P6.2 41 – – I/O General-purpose I/O with port interrupt and wake from LPMx.5
I2C UCB0SCL(3) 15 13 10 I/O eUSCI_B0 I2C clock
UCB0SDA(3) 14 12 9 I/O eUSCI_B0 I2C data
UCB0SCL(4) 17 15 – I/O eUSCI_B0 I2C clock
UCB0SDA(4) 18 16 – I/O eUSCI_B0 I2C data
UCB1SCL(3) 39 33 28 I/O eUSCI_B1 I2C clock
UCB1SDA(3) 38 32 27 I/O eUSCI_B1 I2C data
UCB1SCL(4) 8 8 – I/O eUSCI_B1 I2C clock
UCB1SDA(4) 9 9 – I/O eUSCI_B1 I2C data
Power DVCC 1 1 32 P Power supply
DVSS 48 40 31 P Power ground
VREF+ 4 4 3 P Output of positive reference voltage with ground as reference
SPI UCA0STE(3) 7 7 6 I/O eUSCI_A0 SPI slave transmit enable
UCA0CLK(3) 6 6 5 I/O eUSCI_A0 SPI clock input/output
UCA0SOMI(3) 5 5 4 I/O eUSCI_A0 SPI slave out/master in
UCA0SIMO(3) 4 4 3 I/O eUSCI_A0 SPI slave in/master out
UCA0STE(4) 42 34 – I/O eUSCI_A0 SPI slave transmit enable
UCA0CLK(4) 43 35 – I/O eUSCI_A0 SPI clock input/output
UCA0SOMI(4) 44 36 – I/O eUSCI_A0 SPI slave out/master in
UCA0SIMO(4) 45 37 – I/O eUSCI_A0 SPI slave in/master out
UCA1STE 27 21 16 I/O eUSCI_A1 SPI slave transmit enable
UCA1CLK 28 22 17 I/O eUSCI_A1 SPI clock input/output
UCA1SOMI 29 23 18 I/O eUSCI_A1 SPI slave out/master in
UCA1SIMO 30 24 19 I/O eUSCI_A1 SPI slave in/master out
UCB0STE(3) 12 10 7 I/O eUSCI_B0 slave transmit enable
UCB0CLK(3) 13 11 8 I/O eUSCI_B0 clock input/output
UCB0SOMI(3) 15 13 10 I/O eUSCI_B0 SPI slave out/master in
UCB0SIMO(3) 14 12 9 I/O eUSCI_B0 SPI slave in/master out
UCB0STE(4) 20 – – I/O eUSCI_B0 slave transmit enable
UCB0CLK(4) 19 – – I/O eUSCI_B0 clock input/output
UCB0SOMI(4) 17 – – I/O eUSCI_B0 SPI slave out/master in
UCB0SIMO(4) 18 – – I/O eUSCI_B0 SPI slave in/master out
UCB1STE(3) 36 30 25 I/O eUSCI_B1 slave transmit enable
UCB1CLK(3) 37 31 26 I/O eUSCI_B1 clock input/output
UCB1SOMI(3) 39 33 28 I/O eUSCI_B1 SPI slave out/master in
UCB1SIMO(3) 38 32 27 I/O eUSCI_B1 SPI slave in/master out
UCB1STE(4) 11 – – I/O eUSCI_B1 slave transmit enable
UCB1CLK(4) 10 – – I/O eUSCI_B1 clock input/output
UCB1SOMI(4) 8 – – I/O eUSCI_B1 SPI slave out/master in
UCB1SIMO(4) 9 – – I/O eUSCI_B1 SPI slave in/master out
System NMI 2 2 1 I Nonmaskable interrupt input
RST 2 2 1 I Active-low reset input
Timer_A TA0.1 13 11 8 I/O Timer TA0 CCR1 capture: CCI1A input, compare: Out1 outputs
TA0.2 14 12 9 I/O Timer TA0 CCR2 capture: CCI2A input, compare: Out2 outputs
TA0CLK 12 10 7 I Timer clock input TACLK for TA0
TA1.1 5 5 4 I/O Timer TA1 CCR1 capture: CCI1A input, compare: Out1 outputs
TA1.2 4 4 3 I/O Timer TA1 CCR2 capture: CCI2A input, compare: Out2 outputs
TA1CLK 6 6 5 I Timer clock input TACLK for TA1
TA2.0(5) 25 19 14 I/O Timer TA2 CCR0 capture: CCI0A input, compare: Out0 outputs
TA2.1(5) 24 18 13 I/O Timer TA2 CCR1 capture: CCI1A input, compare: Out1 outputs
TA2.2(5) 23 17 12 I/O Timer TA2 CCR2 capture: CCI2A input, compare: Out2 outputs
TA2CLK(5) 26 20 15 I Timer clock input TACLK for TA2
TA2.0(6) 20 – – I/O Timer TA2 CCR0 capture: CCI0A input, compare: Out0 outputs
TA2.1(6) 21 – – I/O Timer TA2 CCR1 capture: CCI1A input, compare: Out1 outputs
TA2.2(6) 22 – – I/O Timer TA2 CCR2 capture: CCI2A input, compare: Out2 outputs
TA2CLK(6) 19 – – I Timer clock input TACLK for TA2
TA3.0(5) 34 28 23 I/O Timer TA3 CCR0 capture: CCI0A input, compare: Out0 outputs
TA3.1(5) 33 27 22 I/O Timer TA3 CCR1 capture: CCI1A input, compare: Out1 outputs
TA3.2(5) 32 26 21 I/O Timer TA3 CCR2 capture: CCI2A input, compare: Out2 outputs
TA3CLK(5) 35 29 24 I Timer clock input TACLK for TA3
TA3.0(6) 10 – – I/O Timer TA3 CCR0 capture: CCI0A input, compare: Out0 outputs
TA3.1(6) 18 16 – I/O Timer TA3 CCR1 capture: CCI1A input, compare: Out1 outputs
TA3.2(6) 17 15 – I/O Timer TA3 CCR2 capture: CCI2A input, compare: Out2 outputs
TA3CLK(6) 11 – – I Timer clock input TACLK for TA3
Timer_B TB0.0 41 – – I/O Timer TB0 CCR0 capture: CCI0A input, compare: Out0 outputs
TB0.1 42 34 – I/O Timer TB0 CCR1 capture: CCI1A input, compare: Out1 outputs
TB0.2 43 35 – I/O Timer TB0 CCR2 capture: CCI2A input, compare: Out2 outputs
TB0.3 44 36 – I/O Timer TB0 CCR3 capture: CCI3A input, compare: Out3 outputs
TB0.4 45 37 – I/O Timer TB0 CCR4 capture: CCI4A input, compare: Out4 outputs
TB0.5 8 8 – I/O Timer TB0 CCR5 capture: CCI5A input, compare: Out5 outputs
TB0.6 9 9 – I/O Timer TB0 CCR6 capture: CCI6A input, compare: Out6 outputs
TB0CLK 40 – – I Timer clock input TBCLK for TB0
TB0TRG 37 31 26 Timer TB0 external trigger input for TB0OUTH
UART UCA0RXD 5 5 4 I eUSCI_A0 UART receive data
UCA0TXD 4 4 3 O eUSCI_A0 UART transmit data
UCA0RXD(3) 44 36 – I eUSCI_A0 UART receive data
UCA0TXD(3) 45 37 – O eUSCI_A0 UART transmit data
UCA1RXD(4) 29 23 18 I eUSCI_A1 UART receive data
UCA1TXD(4) 30 24 19 O eUSCI_A1 UART transmit data
DNC Do not connect 31 25 20 – Do not connect
VQFN pad VQFN thermal pad – PAD PAD – VQFN package exposed thermal pad. TI recommends connecting to VSS
(1) Pin Types: I = Input, O = Output, I/O = Input or Output, P = Power
(2) Because this pin is multiplexed with the JTAG function, TI recommends disabling the pin interrupt function while in JTAG debug to prevent collisions.
(3) This is the default functionality that can be remapped by the USCIBxRMP or USCIA0RMP bit of the SYSCFG2 or SYCFG3 register. Only one selected port is valid at any time.
(4) This is the remapped functionality controlled by the USCIBxRMP or USCIA0RMP bit of the SYSCFG2 or SYCFG3 register. Only one selected port is valid at any time.
(5) This is the default functionality that can be remapped by the TAxRMP bit of the SYSCFG3 register. Only one selected port is valid at any time.
(6) This is the remapped functionality controlled by the TAxRMP bit of the SYSCFG3 register. Only one selected port is valid at any time.

 

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