ZHCSJG5C March 2019 – September 2021 MSP430FR2475 , MSP430FR2476
PRODUCTION DATA
MSP430FR247x 微控制器 (MCU) 是 MSP430™ MCU 超值系列超低功耗低成本器件产品系列的一部分,该产品系列用于检测和测量应用。MSP430FR247x MCU 集成了一个 12 位 SAR ADC 和一个比较器。所有 MSP430FR247x MCU 均支持 –40° 至 105°C 的工作温度范围,因此这些器件的 FRAM 数据记录功能对更高温度的工业应用来说意义重大。
MSP430FR247x MCU 由一系列由软、硬件组成的生态系统提供支持,并提供有参考设计和代码示例,可帮助您快速开展设计。开发套件包括 MSP-TS430PT48 48 引脚目标开发板。TI 还提供免费的 MSP430Ware™ 软件,该软件以 Code Composer Studio™ IDE 桌面和云版本组件的形式提供(位于 TI Resource Explorer 中)。我们为 MSP430 MCU 提供广泛的在线配套资料(例如内务处理型示例系列、MSP Academy 培训),也通过 TI E2E™ 支持论坛提供在线支持。
MSP430 超低功耗 (ULP) FRAM 微控制器平台将独特的嵌入式 FRAM 和整体超低功耗系统架构相结合,从而使系统设计人员能够在降低能耗的情况下提升性能。FRAM 技术将 RAM 的低功耗快速写入、灵活性和耐用性与闪存的非易失性相结合。
TI MSP430 系列低功耗微控制器包含多种器件,其中配备了不同的外设集以满足各类应用的需求。此架构与多种低功耗模式配合使用,是延长便携式测量应用电池寿命的最优选择。该 MCU 具有一个强大的 16 位 RISC CPU、16 位寄存器和常数发生器,有助于获得最大编码效率。数控振荡器 (DCO) 可使 MCU 在不到 10μs(典型值)的时间内从低功耗模式唤醒至活动模式。
有关完整的模块说明,请参阅 MSP430FR4xx 和 MSP430FR2xx 系列器件用户指南。
器件型号(1) | 封装 | 封装尺寸(2) |
---|---|---|
MSP430FR2476TPT | LQFP (48) | 7mm × 7mm |
MSP430FR2475TPT | LQFP (48) | 7mm × 7mm |
MSP430FR2476TRHA | VQFN (40) | 6mm × 6mm |
MSP430FR2475TRHA | VQFN (40) | 6mm × 6mm |
MSP430FR2476TRHB | VQFN (32) | 5mm x 5mm |
MSP430FR2475TRHB | VQFN (32) | 5mm x 5mm |
系统级静电放电 (ESD) 保护必须符合器件级 ESD 规范,以防发生电气过载或对数据或代码存储器造成干扰。如需更多信息,请参阅 MSP430 系统级 ESD 注意事项。
图 4-1 给出了功能方框图。
Changes from revision B to revision C
Changes from December 11, 2019 to September 14, 2021
Changes from revision A to revision B
Changes from April 26, 2019 to December 10, 2019
Changes from initial release to revision A
Changes from March 12, 2019 to April 25, 2019
Table 6-1 summarizes the features of the available family members.
DEVICE(1)(2) | PROGRAM FRAM + INFORMATION FRAM (KB) | SRAM (KB) | TA0, TA1, TA2, TA3 | TB0 | eUSCI_A0 eUSCI_A1 |
eUSCI_B0 eUSCI_B1 |
12-BIT ADC CHANNELS | eCOMP | GPIOs | PACKAGE |
---|---|---|---|---|---|---|---|---|---|---|
MSP430FR2476TPT | 64 + 0.5 | 8 | 4, 3 × CCR(3) | 1, 7 × CCR(4) | 2 | 2 | 12 | 1 | 43 | 48 LQFP (PT) |
MSP430FR2475TPT | 32 + 0.5 | 6 | 4, 3 × CCR(3) | 1, 7 × CCR(4) | 2 | 2 | 12 | 1 | 43 | 48 LQFP (PT) |
MSP430FR2476TRHA | 64 + 0.5 | 8 | 4, 3 × CCR(3) | 1, 7 × CCR(4) | 2 | 2 | 10 | 1 | 35 | 40 VQFN (RHA) |
MSP430FR2475TRHA | 32 + 0.5 | 6 | 4, 3 × CCR(3) | 1, 7 × CCR(4) | 2 | 2 | 10 | 1 | 35 | 40 VQFN (RHA) |
MSP430FR2476TRHB | 64 + 0.5 | 8 | 4, 3 × CCR(3) | 1, 7 × CCR(5) | 2 | 2 | 8 | 1 | 27 | 32 VQFN (RHB) |
MSP430FR2475TRHB | 32 + 0.5 | 6 | 4, 3 × CCR (3) | 1, 7 × CCR(5) | 2 | 2 | 8 | 1 | 27 | 32 VQFN (RHB) |
For information about other devices in this family of products or related products, see the following links.
Our diverse portfolio of 16- and 32-bit microcontrollers (MCUs) with real-time control capabilities and high-precision analog integration are optimized for industrial and automotive applications. Backed by decades of expertise and innovative hardware and software solutions, our MCUs can meet the needs of any design and budget.
Products for MSP430 microcontrollers
Our 16-bit MSP430™ microcontrollers (MCUs) provide affordable solutions for all applications. Our leadership in integrated precision analog enables designers to enhance system performance and lower system costs. Designers can find a cost-effective MCU within the broad MSP430 portfolio of over 2000 devices for virtually any need. Get started quickly and reduce time to market with our simplified tools, software, and best-in-class support.
Reference designs for MSP430FR2476
Find reference designs leveraging the best in TI technology – from analog and power management to embedded processors
Figure 7-1 shows the pinout of the 48-pin PT package.
Figure 7-2 shows the pinout of the 40-pin RHA package.
Figure 7-3 shows the pinout of the 32-pin RHB package.
Table 7-1 lists the attributes of all pins.
PIN NUMBER | SIGNAL NAME(1)(2) | SIGNAL TYPE(3) | BUFFER TYPE(4) | POWER SOURCE(5) | RESET STATE AFTER BOR(6) | ||
---|---|---|---|---|---|---|---|
PT | RHA | RHB | |||||
1 | 1 | 32 | DVCC | P | Power | DVCC | N/A |
2 | 2 | 1 | RST (RD) | I | LVCMOS | DVCC | PU |
NMI | I | LVCMOS | DVCC | – | |||
SBWTDIO | I/O | LVCMOS | DVCC | – | |||
3 | 3 | 2 | TEST (RD) | I | LVCMOS | DVCC | PD |
SBWTCK | I | LVCMOS | DVCC | – | |||
4 | 4 | 3 | P1.4 (RD) | I/O | LVCMOS | DVCC | OFF |
UCA0TXD | O | LVCMOS | DVCC | – | |||
UCA0SIMO | I/O | LVCMOS | DVCC | – | |||
TA1.2 | I/O | LVCMOS | DVCC | – | |||
TCK | I | LVCMOS | DVCC | – | |||
A4 | I | Analog | DVCC | – | |||
VREF+ | O | Power | DVCC | – | |||
5 | 5 | 4 | P1.5 (RD) | I/O | LVCMOS | DVCC | OFF |
UCA0RXD | I | LVCMOS | DVCC | – | |||
UCA0SOMI | I/O | LVCMOS | DVCC | – | |||
TA1.1 | I/O | LVCMOS | DVCC | – | |||
TMS | I | LVCMOS | DVCC | – | |||
A5 | I | Analog | DVCC | – | |||
6 | 6 | 5 | P1.6 (RD) | I/O | LVCMOS | DVCC | OFF |
UCA0CLK | I/O | LVCMOS | DVCC | – | |||
TA1CLK | I | LVCMOS | DVCC | – | |||
TDI | I | LVCMOS | DVCC | – | |||
TCLK | I | LVCMOS | DVCC | – | |||
A6 | I | Analog | DVCC | – | |||
7 | 7 | 6 | P1.7 (RD) | I/O | LVCMOS | DVCC | OFF |
UCA0STE | I/O | LVCMOS | DVCC | – | |||
SMCLK | O | LVCMOS | DVCC | – | |||
TDO | O | LVCMOS | DVCC | – | |||
A7 | I | Analog | DVCC | – | |||
8 | 8 | – | P4.3 (RD) | I/O | LVCMOS | DVCC | OFF |
UCB1SOMI | I/O | LVCMOS | DVCC | – | |||
UCB1SCL | I/O | LVCMOS | DVCC | – | |||
TB0.5 | I/O | LVCMOS | DVCC | – | |||
A8 | I | Analog | DVCC | – | |||
9 | 9 | – | P4.4 (RD) | I/O | LVCMOS | DVCC | OFF |
UCB1SIMO | I/O | LVCMOS | DVCC | – | |||
UCB1SDA | I/O | LVCMOS | DVCC | – | |||
TB0.6 | I/O | LVCMOS | DVCC | – | |||
A9 | I | Analog | DVCC | – | |||
10 | – | – | P5.3 (RD) | I/O | LVCMOS | DVCC | OFF |
UCB1CLK | I/O | LVCMOS | DVCC | – | |||
TA3.0 | I/O | LVCMOS | DVCC | – | |||
A10 | I | Analog | DVCC | – | |||
11 | – | – | P5.4 (RD) | I/O | LVCMOS | DVCC | OFF |
UCB1STE | I/O | LVCMOS | DVCC | – | |||
TA3CLK | I/O | LVCMOS | DVCC | – | |||
A11 | I | Analog | DVCC | – | |||
12 | 10 | 7 | P1.0 (RD) | I/O | LVCMOS | DVCC | OFF |
UCB0STE | I/O | LVCMOS | DVCC | – | |||
TA0CLK | I | LVCMOS | DVCC | – | |||
A0 | I | Analog | DVCC | – | |||
Veref+ | I | Power | DVCC | – | |||
13 | 11 | 8 | P1.1 (RD) | I/O | LVCMOS | DVCC | OFF |
UCB0CLK | I/O | LVCMOS | DVCC | – | |||
TA0.1 | I/O | LVCMOS | DVCC | – | |||
A1 | I | Analog | DVCC | – | |||
COMP0.0 | I | Analog | DVCC | – | |||
14 | 12 | 9 | P1.2 (RD) | I/O | LVCMOS | DVCC | OFF |
UCB0SIMO | I/O | LVCMOS | DVCC | – | |||
UCB0SDA | I/O | LVCMOS | DVCC | – | |||
TA0.2 | I/O | LVCMOS | DVCC | – | |||
A2 | I | Analog | DVCC | – | |||
Veref- | I | Power | DVCC | – | |||
15 | 13 | 10 | P1.3 (RD) | I/O | LVCMOS | DVCC | OFF |
UCB0SOMI | I/O | LVCMOS | DVCC | – | |||
UCB0SCL | I/O | LVCMOS | DVCC | – | |||
MCLK | O | LVCMOS | DVCC | – | |||
A3 | I | Analog | DVCC | – | |||
16 | 14 | 11 | P2.2 (RD) | I/O | LVCMOS | DVCC | OFF |
ACLK | O | LVCMOS | DVCC | – | |||
COMP0.1 | I | Analog | DVCC | – | |||
17 | 15 | – | P4.5 (RD) | I/O | LVCMOS | DVCC | OFF |
UCB0SOMI | I/O | LVCMOS | DVCC | – | |||
UCB0SCL | I/O | LVCMOS | DVCC | – | |||
TA3.2 | I/O | LVCMOS | DVCC | – | |||
18 | 16 | – | P4.6 (RD) | I/O | LVCMOS | DVCC | OFF |
UCB0SIMO | I/O | LVCMOS | DVCC | – | |||
UCB0SDA | I/O | LVCMOS | DVCC | – | |||
TA3.1 | I/O | LVCMOS | DVCC | – | |||
19 | – | – | P5.5 (RD) | I/O | LVCMOS | DVCC | OFF |
UCB0CLK | I/O | LVCMOS | DVCC | – | |||
TA2CLK | I/O | LVCMOS | DVCC | – | |||
20 | – | – | P5.6 (RD) | I/O | LVCMOS | DVCC | OFF |
UCB0STE | I/O | LVCMOS | DVCC | – | |||
TA2.0 | I/O | LVCMOS | DVCC | – | |||
21 | – | – | P5.7 (RD) | I/O | LVCMOS | DVCC | OFF |
TA2.1 | I/O | LVCMOS | DVCC | – | |||
COMP0.2 | I | Analog | DVCC | – | |||
22 | – | – | P6.0 (RD) | I/O | LVCMOS | DVCC | OFF |
TA2.2 | I/O | LVCMOS | DVCC | – | |||
COMP0.3 | I | Analog | DVCC | – | |||
23 | 17 | 12 | P3.0 (RD) | I/O | LVCMOS | DVCC | OFF |
TA2.2 | I/O | LVCMOS | DVCC | – | |||
24 | 18 | 13 | P3.3 (RD) | I/O | LVCMOS | DVCC | OFF |
TA2.1 | I/O | LVCMOS | DVCC | – | |||
25 | 19 | 14 | P2.3 (RD) | I/O | LVCMOS | DVCC | OFF |
TA2.0 | I/O | LVCMOS | DVCC | – | |||
26 | 20 | 15 | P3.4 (RD) | I/O | LVCMOS | DVCC | OFF |
TA2CLK | I/O | LVCMOS | DVCC | – | |||
COMP0OUT | O | LVCMOS | DVCC | – | |||
27 | 21 | 16 | P3.1 (RD) | I/O | LVCMOS | DVCC | OFF |
UCA1STE | I/O | LVCMOS | DVCC | – | |||
28 | 22 | 17 | P2.4 (RD) | I/O | LVCMOS | DVCC | OFF |
UCA1CLK | I/O | LVCMOS | DVCC | – | |||
29 | 23 | 18 | P2.5 (RD) | I/O | LVCMOS | DVCC | OFF |
UCA1RXD | I | LVCMOS | DVCC | – | |||
UCA1SOMI | I/O | LVCMOS | DVCC | – | |||
30 | 24 | 19 | P2.6 (RD) | I/O | LVCMOS | DVCC | OFF |
UCA1TXD | O | LVCMOS | DVCC | – | |||
UCA1SIMO | I/O | LVCMOS | DVCC | – | |||
31 | 25 | 20 | DNC(7) | – | – | – | – |
32 | 26 | 21 | P3.7 (RD) | I/O | LVCMOS | DVCC | OFF |
TA3.2 | I/O | LVCMOS | DVCC | – | |||
33 | 27 | 22 | P4.0 (RD) | I/O | LVCMOS | DVCC | OFF |
TA3.1 | I/O | LVCMOS | DVCC | – | |||
34 | 28 | 23 | P4.1 (RD) | I/O | LVCMOS | DVCC | OFF |
TA3.0 | I/O | LVCMOS | DVCC | – | |||
35 | 29 | 24 | P4.2 (RD) | I/O | LVCMOS | DVCC | OFF |
TA3CLK | I/O | LVCMOS | DVCC | – | |||
36 | 30 | 25 | P2.7 (RD) | I/O | LVCMOS | DVCC | OFF |
UCB1STE | I/O | LVCMOS | DVCC | – | |||
37 | 31 | 26 | P3.5 (RD) | I/O | LVCMOS | DVCC | OFF |
UCB1CLK | I/O | LVCMOS | DVCC | – | |||
TB0TRG | I | LVCMOS | DVCC | – | |||
38 | 32 | 27 | P3.2 (RD) | I/O | LVCMOS | DVCC | OFF |
UCB1SIMO | I/O | LVCMOS | DVCC | – | |||
UCB1SDA | I/O | LVCMOS | DVCC | – | |||
39 | 33 | 28 | P3.6(RD) | I/O | LVCMOS | DVCC | OFF |
UCB1SOMI | I/O | LVCMOS | DVCC | – | |||
UCB1SCL | I/O | LVCMOS | DVCC | – | |||
40 | – | – | P6.1 (RD) | I/O | LVCMOS | DVCC | OFF |
TB0CLK | I/O | LVCMOS | DVCC | – | |||
41 | – | – | P6.2 (RD) | I/O | LVCMOS | DVCC | OFF |
TB0.0 | I/O | LVCMOS | DVCC | – | |||
42 | 34 | – | P4.7 (RD) | I/O | LVCMOS | DVCC | OFF |
UCA0STE | I/O | LVCMOS | DVCC | – | |||
TB0.1 | I/O | LVCMOS | DVCC | – | |||
43 | 35 | – | P5.0 (RD) | I/O | LVCMOS | DVCC | OFF |
UCA0CLK | I/O | LVCMOS | DVCC | – | |||
TB0.2 | I | LVCMOS | DVCC | – | |||
44 | 36 | – | P5.1 (RD) | I/O | LVCMOS | DVCC | OFF |
UCA0RXD | I | LVCMOS | DVCC | – | |||
UCA0SOMI | I/O | LVCMOS | DVCC | – | |||
TB0.3 | I/O | LVCMOS | DVCC | – | |||
45 | 37 | – | P5.2 (RD) | I/O | LVCMOS | DVCC | OFF |
UCA0TXD | O | LVCMOS | DVCC | – | |||
UCA0SIMO | I/O | LVCMOS | DVCC | – | |||
TB0.4 | I/O | LVCMOS | DVCC | – | |||
46 | 38 | 29 | P2.0 (RD) | I/O | LVCMOS | DVCC | OFF |
XOUT | O | LVCMOS | DVCC | – | |||
47 | 39 | 30 | P2.1 (RD) | I/O | LVCMOS | DVCC | OFF |
XIN | I | LVCMOS | DVCC | – | |||
48 | 40 | 31 | DVSS | P | Power | DVCC | N/A |
Table 7-2 describes the signals for all device variants and package options.
FUNCTION | SIGNAL NAME | PIN NUMBER | PIN TYPE(1) | DESCRIPTION | ||
---|---|---|---|---|---|---|
PT | RHA | RHB | ||||
ADC | A0 | 12 | 10 | 7 | I | Analog input A0 |
A1 | 13 | 11 | 8 | I | Analog input A1 | |
A2 | 14 | 12 | 9 | I | Analog input A2 | |
A3 | 15 | 13 | 10 | I | Analog input A3 | |
A4 | 4 | 4 | 3 | I | Analog input A4 | |
A5 | 5 | 5 | 4 | I | Analog input A5 | |
A6 | 6 | 6 | 5 | I | Analog input A6 | |
A7 | 7 | 7 | 6 | I | Analog input A7 | |
A8 | 8 | 8 | – | I | Analog input A8 | |
A9 | 9 | 9 | – | I | Analog input A9 | |
A10 | 10 | – | – | I | Analog input A10 | |
A11 | 11 | – | – | I | Analog input A11 | |
Veref+ | 12 | 10 | 7 | I | ADC positive reference | |
Veref- | 14 | 12 | 9 | I | ADC negative reference | |
eCOMP0 | COMP0.0 | 13 | 11 | 8 | I | Enhanced comparator input channel C0 |
COMP0.1 | 16 | 14 | 11 | I | Enhanced comparator input channel C1 | |
COMP0.2 | 21 | – | – | I | Enhanced comparator input channel C2 | |
COMP0.3 | 22 | – | – | I | Enhanced comparator input channel C3 | |
COMP0OUT | 26 | 20 | 15 | O | Enhanced comparator output channel COUT | |
Clock | ACLK | 16 | 14 | 11 | I/O | ACLK output |
MCLK | 15 | 13 | 10 | O | MCLK output | |
SMCLK | 7 | 7 | 6 | O | SMCLK output | |
XIN | 47 | 39 | 30 | I | Input terminal for crystal oscillator | |
XOUT | 46 | 38 | 29 | O | Output terminal for crystal oscillator | |
Debug | SBWTCK | 3 | 3 | 2 | I | Spy-Bi-Wire input clock |
SBWTDIO | 2 | 2 | 1 | I/O | Spy-Bi-Wire data input/output | |
TCK | 4 | 4 | 3 | I | Test clock | |
TCLK | 6 | 6 | 5 | I | Test clock input | |
TDI | 6 | 6 | 5 | I | Test data input | |
TDO | 7 | 7 | 6 | O | Test data output | |
TEST | 3 | 3 | 2 | I | Test Mode pin – selected digital I/O on JTAG pins | |
TMS | 5 | 5 | 4 | I | Test mode select | |
GPIO, Port 1 | P1.0 | 12 | 10 | 7 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 |
P1.1 | 13 | 11 | 8 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P1.2 | 14 | 12 | 9 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P1.3 | 15 | 13 | 10 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P1.4 | 4 | 4 | 3 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 (2) | |
P1.5 | 5 | 5 | 4 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5(2) | |
P1.6 | 6 | 6 | 5 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5(2) | |
P1.7 | 7 | 7 | 6 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5(2) | |
GPIO, Port 2 | P2.0 | 46 | 38 | 29 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 |
P2.1 | 47 | 39 | 30 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P2.2 | 16 | 14 | 11 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P2.3 | 25 | 19 | 14 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P2.4 | 28 | 22 | 17 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P2.5 | 29 | 23 | 18 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P2.6 | 30 | 24 | 19 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P2.7 | 36 | 30 | 25 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
GPIO, Port 3 | P3.0 | 23 | 17 | 12 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 |
P3.1 | 27 | 21 | 16 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P3.2 | 38 | 32 | 27 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P3.3 | 24 | 18 | 13 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P3.4 | 26 | 20 | 15 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P3.5 | 37 | 31 | 26 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P3.6 | 39 | 33 | 28 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P3.7 | 32 | 26 | 21 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
GPIO, Port 4 | P4.0 | 33 | 27 | 22 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 |
P4.1 | 34 | 28 | 23 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P4.2 | 35 | 29 | 24 | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P4.3 | 8 | 8 | – | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P4.4 | 9 | 9 | – | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P4.5 | 17 | 15 | – | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P4.6 | 18 | 16 | – | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P4.7 | 42 | 34 | – | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
GPIO, Port 5 | P5.0 | 43 | 35 | – | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 |
P5.1 | 44 | 36 | – | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P5.2 | 45 | 37 | – | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P5.3 | 10 | – | – | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P5.4 | 11 | – | – | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P5.5 | 19 | – | – | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P5.6 | 20 | – | – | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P5.7 | 21 | – | – | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
GPIO, Port 6 | P6.0 | 22 | – | – | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 |
P6.1 | 40 | – | – | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
P6.2 | 41 | – | – | I/O | General-purpose I/O with port interrupt and wake from LPMx.5 | |
I2C | UCB0SCL(3) | 15 | 13 | 10 | I/O | eUSCI_B0 I2C clock |
UCB0SDA(3) | 14 | 12 | 9 | I/O | eUSCI_B0 I2C data | |
UCB0SCL(4) | 17 | 15 | – | I/O | eUSCI_B0 I2C clock | |
UCB0SDA(4) | 18 | 16 | – | I/O | eUSCI_B0 I2C data | |
UCB1SCL(3) | 39 | 33 | 28 | I/O | eUSCI_B1 I2C clock | |
UCB1SDA(3) | 38 | 32 | 27 | I/O | eUSCI_B1 I2C data | |
UCB1SCL(4) | 8 | 8 | – | I/O | eUSCI_B1 I2C clock | |
UCB1SDA(4) | 9 | 9 | – | I/O | eUSCI_B1 I2C data | |
Power | DVCC | 1 | 1 | 32 | P | Power supply |
DVSS | 48 | 40 | 31 | P | Power ground | |
VREF+ | 4 | 4 | 3 | P | Output of positive reference voltage with ground as reference | |
SPI | UCA0STE(3) | 7 | 7 | 6 | I/O | eUSCI_A0 SPI slave transmit enable |
UCA0CLK(3) | 6 | 6 | 5 | I/O | eUSCI_A0 SPI clock input/output | |
UCA0SOMI(3) | 5 | 5 | 4 | I/O | eUSCI_A0 SPI slave out/master in | |
UCA0SIMO(3) | 4 | 4 | 3 | I/O | eUSCI_A0 SPI slave in/master out | |
UCA0STE(4) | 42 | 34 | – | I/O | eUSCI_A0 SPI slave transmit enable | |
UCA0CLK(4) | 43 | 35 | – | I/O | eUSCI_A0 SPI clock input/output | |
UCA0SOMI(4) | 44 | 36 | – | I/O | eUSCI_A0 SPI slave out/master in | |
UCA0SIMO(4) | 45 | 37 | – | I/O | eUSCI_A0 SPI slave in/master out | |
UCA1STE | 27 | 21 | 16 | I/O | eUSCI_A1 SPI slave transmit enable | |
UCA1CLK | 28 | 22 | 17 | I/O | eUSCI_A1 SPI clock input/output | |
UCA1SOMI | 29 | 23 | 18 | I/O | eUSCI_A1 SPI slave out/master in | |
UCA1SIMO | 30 | 24 | 19 | I/O | eUSCI_A1 SPI slave in/master out | |
UCB0STE(3) | 12 | 10 | 7 | I/O | eUSCI_B0 slave transmit enable | |
UCB0CLK(3) | 13 | 11 | 8 | I/O | eUSCI_B0 clock input/output | |
UCB0SOMI(3) | 15 | 13 | 10 | I/O | eUSCI_B0 SPI slave out/master in | |
UCB0SIMO(3) | 14 | 12 | 9 | I/O | eUSCI_B0 SPI slave in/master out | |
UCB0STE(4) | 20 | – | – | I/O | eUSCI_B0 slave transmit enable | |
UCB0CLK(4) | 19 | – | – | I/O | eUSCI_B0 clock input/output | |
UCB0SOMI(4) | 17 | – | – | I/O | eUSCI_B0 SPI slave out/master in | |
UCB0SIMO(4) | 18 | – | – | I/O | eUSCI_B0 SPI slave in/master out | |
UCB1STE(3) | 36 | 30 | 25 | I/O | eUSCI_B1 slave transmit enable | |
UCB1CLK(3) | 37 | 31 | 26 | I/O | eUSCI_B1 clock input/output | |
UCB1SOMI(3) | 39 | 33 | 28 | I/O | eUSCI_B1 SPI slave out/master in | |
UCB1SIMO(3) | 38 | 32 | 27 | I/O | eUSCI_B1 SPI slave in/master out | |
UCB1STE(4) | 11 | – | – | I/O | eUSCI_B1 slave transmit enable | |
UCB1CLK(4) | 10 | – | – | I/O | eUSCI_B1 clock input/output | |
UCB1SOMI(4) | 8 | – | – | I/O | eUSCI_B1 SPI slave out/master in | |
UCB1SIMO(4) | 9 | – | – | I/O | eUSCI_B1 SPI slave in/master out | |
System | NMI | 2 | 2 | 1 | I | Nonmaskable interrupt input |
RST | 2 | 2 | 1 | I | Active-low reset input | |
Timer_A | TA0.1 | 13 | 11 | 8 | I/O | Timer TA0 CCR1 capture: CCI1A input, compare: Out1 outputs |
TA0.2 | 14 | 12 | 9 | I/O | Timer TA0 CCR2 capture: CCI2A input, compare: Out2 outputs | |
TA0CLK | 12 | 10 | 7 | I | Timer clock input TACLK for TA0 | |
TA1.1 | 5 | 5 | 4 | I/O | Timer TA1 CCR1 capture: CCI1A input, compare: Out1 outputs | |
TA1.2 | 4 | 4 | 3 | I/O | Timer TA1 CCR2 capture: CCI2A input, compare: Out2 outputs | |
TA1CLK | 6 | 6 | 5 | I | Timer clock input TACLK for TA1 | |
TA2.0(5) | 25 | 19 | 14 | I/O | Timer TA2 CCR0 capture: CCI0A input, compare: Out0 outputs | |
TA2.1(5) | 24 | 18 | 13 | I/O | Timer TA2 CCR1 capture: CCI1A input, compare: Out1 outputs | |
TA2.2(5) | 23 | 17 | 12 | I/O | Timer TA2 CCR2 capture: CCI2A input, compare: Out2 outputs | |
TA2CLK(5) | 26 | 20 | 15 | I | Timer clock input TACLK for TA2 | |
TA2.0(6) | 20 | – | – | I/O | Timer TA2 CCR0 capture: CCI0A input, compare: Out0 outputs | |
TA2.1(6) | 21 | – | – | I/O | Timer TA2 CCR1 capture: CCI1A input, compare: Out1 outputs | |
TA2.2(6) | 22 | – | – | I/O | Timer TA2 CCR2 capture: CCI2A input, compare: Out2 outputs | |
TA2CLK(6) | 19 | – | – | I | Timer clock input TACLK for TA2 | |
TA3.0(5) | 34 | 28 | 23 | I/O | Timer TA3 CCR0 capture: CCI0A input, compare: Out0 outputs | |
TA3.1(5) | 33 | 27 | 22 | I/O | Timer TA3 CCR1 capture: CCI1A input, compare: Out1 outputs | |
TA3.2(5) | 32 | 26 | 21 | I/O | Timer TA3 CCR2 capture: CCI2A input, compare: Out2 outputs | |
TA3CLK(5) | 35 | 29 | 24 | I | Timer clock input TACLK for TA3 | |
TA3.0(6) | 10 | – | – | I/O | Timer TA3 CCR0 capture: CCI0A input, compare: Out0 outputs | |
TA3.1(6) | 18 | 16 | – | I/O | Timer TA3 CCR1 capture: CCI1A input, compare: Out1 outputs | |
TA3.2(6) | 17 | 15 | – | I/O | Timer TA3 CCR2 capture: CCI2A input, compare: Out2 outputs | |
TA3CLK(6) | 11 | – | – | I | Timer clock input TACLK for TA3 | |
Timer_B | TB0.0 | 41 | – | – | I/O | Timer TB0 CCR0 capture: CCI0A input, compare: Out0 outputs |
TB0.1 | 42 | 34 | – | I/O | Timer TB0 CCR1 capture: CCI1A input, compare: Out1 outputs | |
TB0.2 | 43 | 35 | – | I/O | Timer TB0 CCR2 capture: CCI2A input, compare: Out2 outputs | |
TB0.3 | 44 | 36 | – | I/O | Timer TB0 CCR3 capture: CCI3A input, compare: Out3 outputs | |
TB0.4 | 45 | 37 | – | I/O | Timer TB0 CCR4 capture: CCI4A input, compare: Out4 outputs | |
TB0.5 | 8 | 8 | – | I/O | Timer TB0 CCR5 capture: CCI5A input, compare: Out5 outputs | |
TB0.6 | 9 | 9 | – | I/O | Timer TB0 CCR6 capture: CCI6A input, compare: Out6 outputs | |
TB0CLK | 40 | – | – | I | Timer clock input TBCLK for TB0 | |
TB0TRG | 37 | 31 | 26 | Timer TB0 external trigger input for TB0OUTH | ||
UART | UCA0RXD | 5 | 5 | 4 | I | eUSCI_A0 UART receive data |
UCA0TXD | 4 | 4 | 3 | O | eUSCI_A0 UART transmit data | |
UCA0RXD(3) | 44 | 36 | – | I | eUSCI_A0 UART receive data | |
UCA0TXD(3) | 45 | 37 | – | O | eUSCI_A0 UART transmit data | |
UCA1RXD(4) | 29 | 23 | 18 | I | eUSCI_A1 UART receive data | |
UCA1TXD(4) | 30 | 24 | 19 | O | eUSCI_A1 UART transmit data | |
DNC | Do not connect | 31 | 25 | 20 | – | Do not connect |
VQFN pad | VQFN thermal pad | – | PAD | PAD | – | VQFN package exposed thermal pad. TI recommends connecting to VSS |