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  • 具有功率限制功能的 LM5069 正高电压热插拔和浪涌电流控制器

    • ZHCSJC9G September   2006  – Jaunuary 2020 LM5069

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  • 具有功率限制功能的 LM5069 正高电压热插拔和浪涌电流控制器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      典型应用图
  4. 4 修订历史记录
    1.     Device Comparison
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Current Limit
      2. 7.3.2 Circuit Breaker
      3. 7.3.3 Power Limit
      4. 7.3.4 Undervoltage Lockout (UVLO)
      5. 7.3.5 Overvoltage Lockout (OVLO)
      6. 7.3.6 Power Good Pin
    4. 7.4 Device Functional Modes
      1. 7.4.1 Power Up Sequence
      2. 7.4.2 Gate Control
      3. 7.4.3 Fault Timer and Restart
      4. 7.4.4 Shutdown Control
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 48-V, 10-A Hot Swap Design
        1. 8.2.1.1 Design Requirements
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Select RSNS and CL setting
          2. 8.2.1.2.2 Selecting the Hot Swap FET(s)
          3. 8.2.1.2.3 Select Power Limit
          4. 8.2.1.2.4 Set Fault Timer
          5. 8.2.1.2.5 Check MOSFET SOA
          6. 8.2.1.2.6 Set Undervoltage and Overvoltage Threshold
            1. 8.2.1.2.6.1 Option A
            2. 8.2.1.2.6.2 Option B
            3. 8.2.1.2.6.3 Option C
            4. 8.2.1.2.6.4 Option D
          7. 8.2.1.2.7 Input and Output Protection
          8. 8.2.1.2.8 Final Schematic and Component Values
        3. 8.2.1.3 Application Curves
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 PC Board Guidelines
      2. 10.1.2 System Considerations
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 开发支持
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息
  13. 重要声明
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DATA SHEET

具有功率限制功能的 LM5069 正高电压热插拔和浪涌电流控制器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 宽工作电压范围：9V 至 80V
  • 浪涌电流限制，用于将电路板安全插入带电电源
  • 外部导通器件中的可编程最大功耗
  • 可调节电流限制
  • 针对严重过流事件的断路器功能
  • 适用于外部 N 沟道 MOSFET 的内部高侧电荷泵和栅极驱动器
  • 可调节欠压锁定 (UVLO) 和迟滞
  • 可调节过压锁定 (OVLO) 和迟滞
  • 初始插入计时器可使振铃和瞬变在系统连接之后消除
  • 可编程故障计时器可避免干扰性跳变
  • 高电平有效、开漏电源正常状态输出
  • 提供故障锁存和自动重启版本
  • 10 引脚 VSSOP 封装

2 应用

  • 服务器背板系统
  • 基站配电系统
  • 固态断路器
  • 24V 和 48V 工业系统

3 说明

LM5069 正电压热插拔控制器可在从带电系统背板或其他热插拔电源插入和移除电路板期间，为电源连接提供智能控制。LM5069 可提供浪涌电流控制以限制系统电压下降和瞬变。外部串行导通 N 沟道 MOSFET 中的电流限制和功率耗散可进行编程，从而确保其在安全工作区 (SOA) 内工作。当输出电压低于 1.25V 输入电压时，会显示电源正常输出。输入欠压和过压锁定电平和迟滞，以及初始插入延迟时间和故障监测时间均可进行编程。在故障监测之后 LM5069-1 闭锁，同时 LM5069-2 以固定占空比自动重启。LM5069 采用 10 引脚 VSSOP 封装。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
LM5069 VSSOP (10) 3.00mm × 3.00mm
  1. 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

Device Images

典型应用图

LM5069 Typical_Application_Schematic_LM5069.gif

4 修订历史记录

Changes from F Revision (February 2019) to G Revision

  • Added Device Comparison tableGo

Changes from E Revision (November 2016) to F Revision

  • Updated the Absolute Maximum Ratings sectionGo

Changes from D Revision (May 2013) to E Revision

  • Added ESD 额定值表，特性 说明 部分，器件功能模式，应用和实施部分，电源建议部分，布局部分，器件和文档支持部分以及机械、封装和可订购信息部分Go
  • Added Thermal Information tableGo

Device Comparison

DEVICE NUMBER RETRY BEHAVIOR AFTER FAULT PACKAGE
LM5069-1 Latch Off on Fault VSSOP (10)
LM5069-2 Auto Retry on Fault

5 Pin Configuration and Functions

DGS Package
10-Pin VSSOP
Top View

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 SENSE I Current sense input: The voltage across the current sense resistor (RS) is measured from VIN to this pin. If the voltage across RS reaches 55 mV the load current is limited and the fault timer activates.
2 VIN I Positive supply input: A small ceramic bypass capacitor close to this pin is recommended to suppress transients which occur when the load current is switched off.
3 UVLO I Undervoltage lockout: An external resistor divider from the system input voltage sets the undervoltage turnon threshold. An internal 21-µA current source provides hysteresis. The enable threshold at the pin is 2.5 V. This pin can also be used for remote shutdown control.
4 OVLO I Overvoltage lockout: An external resistor divider from the system input voltage sets the overvoltage turnoff threshold. An internal 21-µA current source provides hysteresis. The disable threshold at the pin is 2.5 V.
5 GND — Circuit ground
6 TIMER I/O Timing capacitor: An external capacitor connected to this pin sets the insertion time delay and the fault timeout period. The capacitor also sets the restart timing of the LM5069-2.
7 PWR I Power limit set: An external resistor connected to this pin, in conjunction with the current sense resistor (RS), sets the maximum power dissipation allowed in the external series pass MOSFET.
8 PGD O Power Good indicator: An open drain output. When the external MOSFET VDS decreases below 1.25 V, the PGD indicator is active (high). When the external MOSFET VDS increases above 2.5 V the PGD indicator switches low.
9 OUT I Output feedback: Connect to the output rail (external MOSFET source). Internally used to determine the MOSFET VDS voltage for power limiting, and to control the PGD indicator.
10 GATE O Gate drive output: Connect to the external MOSFET’s gate. This pin's voltage is typically 12 V above the OUT pin when enabled.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)(2)
MIN MAX UNIT
VIN to GND(3) –0.3 100 V
SENSE, OUT, and PGD to GND –0.3 100 V
GATE to GND(3) –0.3 100 V
OUT to GND (1 -ms transient) (4) –1 100 V
UVLO to GND –0.3 100 V
OVLO to GND –0.3 7 V
VIN to SENSE –0.3 0.3 V
Maximum junction temperature, TJMAX 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.
(3) The GATE pin voltage is typically 12 V above VIN when the LM5069 is enabled. Therefore, the Absolute Maximum Ratings for VIN
(100 V) applies only when the LM5069 is disabled, or for a momentary surge to that voltage because the Absolute Maximum Rating for the GATE pin is also 100 V.
(4) Select external MOSFET with VGS(th) voltage higher than VOUT during -ve transient. This avoids MOSFET getting turned-ON during -ve transient.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge(1) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(2) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(3) ±500
(1) The Human-body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VIN Supply voltage 9 80 V
PGD off voltage 0 80 V
TJ Junction temperature –40 125 °C
(1) For detailed information on soldering plastic VSSOP packages, see Absolute Maximum Ratings for Soldering (SNOA549) available from Texas Instruments.

6.4 Thermal Information

THERMAL METRIC(1) LM5069 UNIT
DGS (VSSOP)
10 PINS
RθJA Junction-to-ambient thermal resistance 156 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 50.6 °C/W
RθJB Junction-to-board thermal resistance 75.8 °C/W
ψJT Junction-to-top characterization parameter 4.8 °C/W
ψJB Junction-to-board characterization parameter 74.5 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

 
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