具有功率限制功能的 LM5069 正高电压热插拔和浪涌电流控制器
- ZHCSJC9G September 2006 – Jaunuary 2020 LM5069
  
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具有功率限制功能的 LM5069 正高电压热插拔和浪涌电流控制器

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

宽工作电压范围：9V 至 80V
浪涌电流限制，用于将电路板安全插入带电电源
外部导通器件中的可编程最大功耗
可调节电流限制
针对严重过流事件的断路器功能
适用于外部 N 沟道 MOSFET 的内部高侧电荷泵和栅极驱动器
可调节欠压锁定 (UVLO) 和迟滞
可调节过压锁定 (OVLO) 和迟滞
初始插入计时器可使振铃和瞬变在系统连接之后消除
可编程故障计时器可避免干扰性跳变
高电平有效、开漏电源正常状态输出
提供故障锁存和自动重启版本
10 引脚 VSSOP 封装

2 应用

服务器背板系统
基站配电系统
固态断路器
24V 和 48V 工业系统

3 说明

LM5069 正电压热插拔控制器可在从带电系统背板或其他热插拔电源插入和移除电路板期间，为电源连接提供智能控制。LM5069 可提供浪涌电流控制以限制系统电压下降和瞬变。外部串行导通 N 沟道 MOSFET 中的电流限制和功率耗散可进行编程，从而确保其在安全工作区 (SOA) 内工作。当输出电压低于 1.25V 输入电压时，会显示电源正常输出。输入欠压和过压锁定电平和迟滞，以及初始插入延迟时间和故障监测时间均可进行编程。在故障监测之后 LM5069-1 闭锁，同时 LM5069-2 以固定占空比自动重启。LM5069 采用 10 引脚 VSSOP 封装。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
LM5069	VSSOP (10)	3.00mm × 3.00mm

如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

Device Images

典型应用图

LM5069 Typical_Application_Schematic_LM5069.gif

4 修订历史记录

Changes from F Revision (February 2019) to G Revision

Added Device Comparison tableGo

Changes from E Revision (November 2016) to F Revision

Updated the Absolute Maximum Ratings sectionGo

Changes from D Revision (May 2013) to E Revision

Added ESD 额定值表，特性说明 部分，器件功能模式，应用和实施部分，电源建议部分，布局部分，器件和文档支持部分以及机械、封装和可订购信息部分Go
Added Thermal Information tableGo

Device Comparison

DEVICE NUMBER	RETRY BEHAVIOR AFTER FAULT	PACKAGE
LM5069-1	Latch Off on Fault	VSSOP (10)
LM5069-2	Auto Retry on Fault	VSSOP (10)

5 Pin Configuration and Functions

DGS Package

10-Pin VSSOP

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NO.	NAME	I/O	DESCRIPTION
1	SENSE	I	Current sense input: The voltage across the current sense resistor (R_S) is measured from VIN to this pin. If the voltage across R_S reaches 55 mV the load current is limited and the fault timer activates.
2	VIN	I	Positive supply input: A small ceramic bypass capacitor close to this pin is recommended to suppress transients which occur when the load current is switched off.
3	UVLO	I	Undervoltage lockout: An external resistor divider from the system input voltage sets the undervoltage turnon threshold. An internal 21-µA current source provides hysteresis. The enable threshold at the pin is 2.5 V. This pin can also be used for remote shutdown control.
4	OVLO	I	Overvoltage lockout: An external resistor divider from the system input voltage sets the overvoltage turnoff threshold. An internal 21-µA current source provides hysteresis. The disable threshold at the pin is 2.5 V.
5	GND	—	Circuit ground
6	TIMER	I/O	Timing capacitor: An external capacitor connected to this pin sets the insertion time delay and the fault timeout period. The capacitor also sets the restart timing of the LM5069-2.
7	PWR	I	Power limit set: An external resistor connected to this pin, in conjunction with the current sense resistor (R_S), sets the maximum power dissipation allowed in the external series pass MOSFET.
8	PGD	O	Power Good indicator: An open drain output. When the external MOSFET V_DS decreases below 1.25 V, the PGD indicator is active (high). When the external MOSFET V_DS increases above 2.5 V the PGD indicator switches low.
9	OUT	I	Output feedback: Connect to the output rail (external MOSFET source). Internally used to determine the MOSFET V_DS voltage for power limiting, and to control the PGD indicator.
10	GATE	O	Gate drive output: Connect to the external MOSFET’s gate. This pin's voltage is typically 12 V above the OUT pin when enabled.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

	MIN	MAX	UNIT
VIN to GND⁽³⁾	–0.3	100	V
SENSE, OUT, and PGD to GND	–0.3	100	V
GATE to GND⁽³⁾	–0.3	100	V
OUT to GND (1 -ms transient) ⁽⁴⁾	–1	100	V
UVLO to GND	–0.3	100	V
OVLO to GND	–0.3	7	V
VIN to SENSE	–0.3	0.3	V
Maximum junction temperature, T_JMAX		150	°C
Storage temperature, T_stg	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and specifications.

(3) The GATE pin voltage is typically 12 V above VIN when the LM5069 is enabled. Therefore, the Absolute Maximum Ratings for VIN
(100 V) applies only when the LM5069 is disabled, or for a momentary surge to that voltage because the Absolute Maximum Rating for the GATE pin is also 100 V.

(4) Select external MOSFET with VGS(th) voltage higher than V_OUT during -ve transient. This avoids MOSFET getting turned-ON during -ve transient.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge⁽¹⁾	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽²⁾	±2000	V
V_(ESD)	Electrostatic discharge⁽¹⁾	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽³⁾	±500	V

(1) The Human-body model is a 100-pF capacitor discharged through a 1.5-kΩ resistor into each pin.

(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(3) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
VIN	Supply voltage	9	80	V
	PGD off voltage	0	80	V
T_J	Junction temperature	–40	125	°C

(1) For detailed information on soldering plastic VSSOP packages, see Absolute Maximum Ratings for Soldering (SNOA549) available from Texas Instruments.

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		LM5069	UNIT
		DGS (VSSOP)
		10 PINS
R_θJA	Junction-to-ambient thermal resistance	156	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	50.6	°C/W
R_θJB	Junction-to-board thermal resistance	75.8	°C/W
ψ_JT	Junction-to-top characterization parameter	4.8	°C/W
ψ_JB	Junction-to-board characterization parameter	74.5	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	—	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Minimum and maximum limits are specified through test, design, or statistical correlation at T_J= –40°C to 125°C. Typical values represent the most likely parametric norm at T_J = 25°C and are provided for reference purposes only. VIN = 48 V (unless otherwise noted).

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT (VIN PIN)
I_IN-EN	Input current, enabled	UVLO > 2.5 V and OVLO < 2.5 V		1.3	1.6	mA
I_IN-DIS	Input current, disabled	UVLO < 2.5 V or OVLO > 2.5 V		480	650	µA
POR_IT	Power-On reset threshold at VIN to trigger insertion timer	VIN increasing		7.6	8	V
POR_EN	Power-On reset threshold at VIN to enable all functions	VIN increasing		8.4	9	V
POR_EN-HYS	POR_EN hysteresis	VIN decreasing		90		mV
OUT PIN
I_OUT-EN	OUT bias current, enabled	OUT = VIN, Normal operation		11		µA
I_OUT-DIS	OUT bias current, disabled⁽¹⁾	Disabled, OUT = 0 V, SENSE = VIN		50		µA
UVLO, OVLO PINS
UVLO_TH	UVLO threshold		2.45	2.5	2.55	V
UVLO_HYS	UVLO hysteresis current	UVLO = 1 V	12	21	30	µA
UVLO_DEL	UVLO delay	Delay to GATE high		55		µs
UVLO_DEL	UVLO delay	Delay to GATE low		11		µs
UVLO_BIAS	UVLO bias current	UVLO = 48 V			1	µA
OVLO_TH	OVLO threshold		2.4	2.5	2.6	V
OVLO_HYS	OVLO hysteresis current	OVLO = 2.6 V	12	21	30	µA
OVLO_DEL	OVLO delay	Delay to GATE high		55		µs
OVLO_DEL	OVLO delay	Delay to GATE low		11		µs
OVLO_BIAS	OVLO bias current	OVLO = 2.4 V			1	µA
POWER LIMIT (PWR PIN)
PWR_LIM-1	Power limit sense voltage (VIN-SENSE)	SENSE-OUT = 48 V, R_PWR = 150 kΩ	19	25	31	mV
PWR_LIM-2	Power limit sense voltage (VIN-SENSE)	SENSE-OUT = 24 V, R_PWR = 75 kΩ		25		mV
I_PWR	PWR pin current	V_PWR = 2.5 V		20		µA
GATE CONTROL (GATE PIN)
I_GATE	Source current	Normal operation, GATE-OUT = 5 V	10	16	22	µA
	Sink current	UVLO < 2.5 V	1.75	2	2.6	mA
	Sink current	VIN to SENSE = 150 mV or VIN < POR_IT, V_GATE = 5 V	45	110	175	mA
V_GATE	Gate output voltage in normal operation	GATE-OUT voltage	11.4	12	12.6	V
CURRENT LIMIT
V_CL	Threshold voltage	VIN-SENSE voltage	48.5	55	61.5	mV
t_CL	Response time	VIN-SENSE stepped from 0 mV to 80 mV		45		µs
I_SENSE	SENSE input current	Enabled, SENSE = OUT		23		µA
I_SENSE	SENSE input current	Disabled, OUT = 0 V		60		µA
CIRCUIT BREAKER
V_CB	Threshold voltage	VIN to SENSE	80	105	130	mV
t_CB	Response time	VIN to SENSE stepped from 0 mV to 150 mV, time to GATE low, no load		0.44	1.2	µs
TIMER (TIMER PIN)
V_TMRH	Upper threshold		3.76	4	4.16	V
V_TMRL	Lower threshold	Restart cycles (LM5069-2)	1.187	1.25	1.313	V
		End of 8th cycle (LM5069-2)		0.3		V
		Re-enable Threshold (LM5069-1)		0.3		V
I_TIMER	Insertion time current		3	5.5	8	µA
	Sink current, end of insertion time	TIMER pin = 2 V	1	1.5	2	mA
	Fault detection current		51	85	120	µA
	Fault sink current		1.25	2.5	3.75	µA
DC_FAULT	Fault restart duty cycle	LM5069-2 only		0.5%
t_FAULT	Fault to GATE low delay	TIMER pin reaches 4 V		12		µs
POWER GOOD (PGD PIN)
PGD_TH	Threshold measured at SENSE-OUT	Decreasing	0.67	1.25	1.85	V
PGD_TH	Threshold measured at SENSE-OUT	Increasing, relative to decreasing threshold	0.95	1.25	1.55	V
PGD_VOL	Output low voltage	I_SINK = 2 mA		60	150	mV
PGD_IOH	Off leakage current	V_PGD= 80 V			5	µA

(1) OUT bias current (disabled) due to leakage current through an internal 1-MΩ resistance from SENSE to VOUT.

6.6 Typical Characteristics

T_J = 25°C and V_IN = 48 V (unless otherwise noted)

Figure 1. VIN Pin Input Current vs VIN

Figure 3. OUT Pin Current

Figure 5. GATE Pin Source Current vs V_IN

Figure 7. MOSFET Power Dissipation Limit vs R_PWR and R_S

Figure 9. UVLO Hysteresis Current vs Temperature

Figure 11. UVLO, OVLO Threshold vs Temperature

Figure 13. Current Limit Threshold vs Temperature

Figure 15. Power Limit Threshold vs Temperature

Figure 17. GATE Source Current vs Temperature

Figure 19. PGD Low Voltage vs Temperature

Figure 2. SENSE Pin Input Current

Figure 4. GATE Pin Voltage vs V_IN

Figure 6. PGD Pin Low Voltage vs Sink Current

Figure 8. GATE Pulldown Current, Circuit Breaker
vs GATE Voltage

Figure 10. OVLO Hysteresis Current vs Temperature

Figure 12. Input Current, Enabled vs Temperature

Figure 14. Circuit Breaker Threshold vs Temperature

Figure 16. GATE Output Voltage vs Temperature

Figure 18. GATE Pulldown Current, Circuit Breaker
vs Temperature

7 Detailed Description

7.1 Overview

The inline protection functionality of the LM5069 is designed to control the in-rush current to the load upon insertion of a circuit card into a live backplane or other hot power source, thereby limiting the voltage sag on the backplane's supply voltage and the dV/dt of the voltage applied to the load. Effects on other circuits in the system are minimized, preventing possible unintended resets. A controlled shutdown when the circuit card is removed can also be implemented using the LM5069.

In addition to a programmable current limit, the LM5069 monitors and limits the maximum power dissipation in the series pass device to maintain operation within the device Safe Operating Area (SOA). Either current limiting or power limiting for an extended period of time results in the shutdown of the series pass device. In this event, the LM5069-1 latches off while the LM5069-2 retries an infinite number of times to recover after the fault is removed. The circuit breaker function quickly switches off the series pass device upon detection of a severe overcurrent condition. Programmable undervoltage lockout (UVLO) and overvoltage lockout (OVLO) circuits shut down the LM5069 when the system input voltage is outside the desired operating range.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Current Limit

The current limit threshold is reached when the voltage across the sense resistor R_S (VIN to SENSE) reaches
55 mV. In the current limiting condition, the GATE voltage is controlled to limit the current in MOSFET Q1. While the current limit circuit is active, the fault timer is active as described in Fault Timer and Restart. If the load current falls below the current limit threshold before the end of the fault timeout period, the LM5069 resumes normal operation. For proper operation, the R_S resistor value must be no larger than 100 mΩ.

7.3.2 Circuit Breaker

If the load current increases rapidly (for example, the load is short-circuited) the current in the sense resistor (R_S) may exceed the current limit threshold before the current limit control loop is able to respond. If the current exceeds twice the current limit threshold (105 mV/R_S), Q1 is quickly switched off by the 230-mA pulldown current at the GATE pin, and a fault timeout period begins. When the voltage across R_S falls below 105 mV the 230-mA pulldown current at the GATE pin is switched off, and the gate voltage of Q1 is then determined by the current limit or the power limit functions. If the TIMER pin reaches 4 V before the current limiting or power limiting condition ceases, Q1 is switched off by the 2-mA pulldown current at the GATE pin as described in Fault Timer and Restart.

7.3.3 Power Limit

An important feature of the LM5069 is the MOSFET power limiting. The Power Limit function can be used to maintain the maximum power dissipation of MOSFET Q1 within the device SOA rating. The LM5069 determines the power dissipation in Q1 by monitoring its drain-source voltage (SENSE to OUT), and the drain current through the sense resistor (VIN to SENSE). The product of the current and voltage is compared to the power limit threshold programmed by the resistor at the PWR pin. If the power dissipation reaches the limiting threshold, the GATE voltage is modulated to reduce the current in Q1. While the power limiting circuit is active, the fault timer is active as described in Fault Timer and Restart.

7.3.4 Undervoltage Lockout (UVLO)

The series pass MOSFET (Q1) is enabled when the input supply voltage (V_SYS) is within the operating range defined by the programmable undervoltage lockout (UVLO) and overvoltage lockout (OVLO) levels. Typically the UVLO level at V_SYS is set with a resistor divider (R1-R3) as shown in Figure 30. When V_SYS is below the UVLO level, the internal 21-µA current source at UVLO is enabled, the current source at OVLO is off, and Q1 is held off by the
2-mA pulldown current at the GATE pin. As V_SYS is increased, raising the voltage at UVLO above 2.5 V, the
21-µA current source at UVLO is switched off, increasing the voltage at UVLO, providing hysteresis for this threshold. With the UVLO pin above 2.5 V, Q1 is switched on by the 16-µA current source at the GATE pin if the insertion time delay has expired (Figure 22). See Application and Implementation for a procedure to calculate the values of the threshold setting resistors (R1-R3). The minimum possible UVLO level at V_SYS can be set by connecting the UVLO pin to VIN. In this case Q1 is enabled when the VIN voltage reaches the POR_EN threshold.

7.3.5 Overvoltage Lockout (OVLO)

The series pass MOSFET (Q1) is enabled when the input supply voltage (V_SYS) is within the operating range defined by the programmable undervoltage lockout (UVLO) and overvoltage lockout (OVLO) levels. If V_SYS raises the OVLO pin voltage above 2.5 V, Q1 is switched off by the 2-mA pulldown current at the GATE pin, denying power to the load. When the OVLO pin is above 2.5 V, the internal 21-µA current source at OVLO is switched on, raising the voltage at OVLO to provide threshold hysteresis. When V_SYS is reduced below the OVLO level Q1 is enabled. See Application and Implementation for a procedure to calculate the threshold setting resistor values.

7.3.6 Power Good Pin

During turnon, the Power Good pin (PGD) is high until the voltage at VIN increases above ≊ 5 V. PGD then switches low, remaining low as the VIN voltage increases. When the voltage at OUT increases to within 1.25 V of the SENSE pin (V_DS <1.25 V), PGD switches high. PGD switches low if the V_DS of Q1 increases above 2.5 V. A pullup resistor is required at PGD as shown in Figure 20. The pullup voltage (V_PGD) can be as high as 80 V, with transient capability to 100 V, and can be higher or lower than the voltages at VIN and OUT.

Figure 20. Power Good Output

If a delay is required at PGD, suggested circuits are shown in Figure 21. In Figure 21a, capacitor C_PG adds delay to the rising edge, but not to the falling edge. In Figure 21b, the rising edge is delayed by R_PG1 + R_PG2 and C_PG, while the falling edge is delayed a lesser amount by R_PG2 and C_PG. Adding a diode across R_PG2 (Figure 21c) allows for equal delays at the two edges, or a short delay at the rising edge and a long delay at the falling edge.

Figure 21. Adding Delay to the Power Good Output Pin

7.4 Device Functional Modes

The LM5069 hot swap controller has a power up sequence which can be broken down into 3x distinct sections: Insertion Time, In-Rush Limiting, and Normal Operation. Once the device reaches normal operation, the GATE and TIMER behavior depends on whether a fault condition is present or not on the output.

7.4.1 Power Up Sequence

The VIN operating range of the LM5069 is 9 V to 80 V, with a transient capability to 100 V. See Functional Block Diagram and Figure 22, as the voltage at VIN initially increases, the external N-channel MOSFET (Q1) is held off by an internal 230-mA pulldown current at the GATE pin. The strong pulldown current at the GATE pin prevents an inadvertent turnon as the MOSFET’s gate-to-drain (Miller) capacitance is charged. Additionally, the TIMER pin is initially held at ground. When the VIN voltage reaches the POR_IT threshold (7.6 V) the insertion time begins. During the insertion time, the capacitor at the TIMER pin (C_T) is charged by a 5.5-µA current source, and Q1 is held off by a 2-mA pulldown current at the GATE pin regardless of the VIN voltage. The insertion time delay allows ringing and transients at VIN to settle before Q1 can be enabled. The insertion time ends when the TIMER pin voltage reaches 4 V. C_T is then quickly discharged by an internal 1.5-mA pulldown current. After the insertion time, the LM5069 control circuitry is enabled when VIN reaches the POR_EN threshold (8.4 V). The GATE pin then switches on Q1 when V_SYS exceeds the UVLO threshold (UVLO pin >2.5 V). If V_SYS is above the UVLO threshold at the end of the insertion time, Q1 switches on at that time. The GATE pin charge pump sources 16 µA to charge Q1’s gate capacitance. The maximum gate-to-source voltage of Q1 is limited by an internal 12-V Zener diode.

As the voltage at the OUT pin increases, the LM5069 monitors the drain current and power dissipation of MOSFET Q1. In-rush current limiting and/or power limiting circuits actively control the current delivered to the load. During the in-rush limiting interval (t2 in Figure 22) an internal 85-µA fault timer current source charges C_T. If Q1’s power dissipation and the input current reduce below their respective limiting thresholds before the TIMER pin reaches 4 V, the 85-µA current source is switched off, and C_T is discharged by the internal 2.5-µA current sink (t3 in Figure 22). The in-rush limiting interval is complete when the voltage at the OUT pin increases to within 1.25 V of the input voltage (V_SYS), and the PGD pin switches high.

If the TIMER pin voltage reaches 4 V before in-rush current limiting or power limiting ceases (during t2), a fault is declared and Q1 is turned off. See Fault Timer and Restart for a complete description of the fault mode.

Figure 22. Power-Up Sequence (Current Limit Only)

7.4.2 Gate Control

A charge pump provides internal bias voltage above the output voltage (OUT pin) to enhance the N-Channel MOSFET’s gate. The gate-to-source voltage is limited by an internal 12-V Zener diode. During normal operating conditions (t3 in Figure 22) the gate of Q1 is held charged by an internal 16-µA current source to approximately 12 V above OUT. If the maximum V_GS rating of Q1 is less than 12 V, an external Zener diode of lower voltage must be added between the GATE and OUT pins. The external Zener diode must have a forward current rating of at least 250 mA.

When the system voltage is initially applied, the GATE pin is held low by a 230-mA pulldown current. This helps prevent an inadvertent turnon of the MOSFET through its drain-gate capacitance as the applied system voltage increases.

During the insertion time (t1 in Figure 22) the GATE pin is held low by a 2-mA pulldown current. This maintains Q1 in the off-state until the end of t1, regardless of the voltage at VIN or UVLO.

Following the insertion time, during t2 in Figure 22, the gate voltage of Q1 is modulated to keep the current or power dissipation level from exceeding the programmed levels. While in the current or power limiting mode the TIMER pin capacitor is charging. If the current and power limiting cease before the TIMER pin reaches 4 V the TIMER pin capacitor then discharges, and the circuit enters normal operation.

If the in-rush limiting condition persists such that the TIMER pin reached 4 V during t2, the GATE pin is then pulled low by the 2-mA pulldown current. The GATE pin is then held low until either a power-up sequence is initiated (LM5069-1), or until the end of the restart sequence (LM5069-2). See Fault Timer and Restart.

If the system input voltage falls below the UVLO threshold, or rises above the OVLO threshold, the GATE pin is pulled low by the 2-mA pulldown current to switch off Q1.

Figure 23. Gate Control

7.4.3 Fault Timer and Restart

When the current limit or power limit threshold is reached during turnon or as a result of a fault condition, the gate-to-source voltage of Q1 is modulated to regulate the load current and power dissipation. When either limiting function is activated, an 85-µA fault timer current source charges the external capacitor (C_T) at the TIMER pin as shown in Figure 25 (fault timeout period). If the fault condition subsides during the fault timeout period before the TIMER pin reaches 4 V, the LM5069 returns to the normal operating mode and C_T is discharged by the 2.5-µA current sink. If the TIMER pin reaches 4 V during the fault timeout period, Q1 is switched off by a 2-mA pulldown current at the GATE pin. The subsequent restart procedure then depends on which version of the LM5069 is in use.

The LM5069-1 latches the GATE pin low at the end of the fault timeout period. C_T is then discharged to ground by the 2.5-µA fault current sink. The GATE pin is held low by the 2-mA pulldown current until a power-up sequence is externally initiated by cycling the input voltage (V_SYS), or momentarily pulling the UVLO pin below 2.5 V with an open-collector or open-drain device as shown in Figure 24. The voltage at the TIMER pin must be <0.3 V for the restart procedure to be effective.

Figure 24. Latched Fault Restart Control

The LM5069-2 provides an automatic restart sequence which consists of the TIMER pin cycling between 4 V and 1.25 V seven times after the fault timeout period, as shown in Figure 25. The period of each cycle is determined by the 85-µA charging current, and the 2.5-µA discharge current, and the value of the capacitor C_T. When the TIMER pin reaches 0.3 V during the eighth high-to-low ramp, the 16-µA current source at the GATE pin turns on Q1. If the fault condition is still present, the fault timeout period and the restart cycle repeat.

Figure 25. Restart Sequence (LM5069-2)

7.4.4 Shutdown Control

The load current can be remotely switched off by taking the UVLO pin below its 2.5-V threshold with an open collector or open-drain device, as shown in Figure 26. Upon releasing the UVLO pin the LM5069 switches on the load current with in-rush current and power limiting.

Figure 26. Shutdown Control

8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LM5069 is a hot swap controller which is used to manage inrush current and protect in case of faults. When designing a hot swap, three key scenarios must be considered:

Start-up
Output of a hot swap is shorted to ground when the hot swap is on. This is often referred to as a hot-short.
Powering up a board when the output and ground are shorted. This is usually called a start-into-short.

All of these scenarios place a lot of stress on the hot swap MOSFET and thus special care is required when designing the hot swap circuit to keep the MOSFET within its SOA (Safe Operating Area). Detailed design examples are provided in the following sections. Solving all of the equations by hand is cumbersome and can result in errors. Instead, TI recommends using the LM5069 Design Calculator provided on the product page.