DATA SHEET
MSP430FR604x、MSP430FR504x 16MHz MCU 高达 64KB FRAM，12 位高速 8-MSPS Σ-Δ ADC 和集成传感器 AFE
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1 特性
- 功耗超低的一流超声波水流和气流测量
- 水
- 在低流速到高流速的情况下以及工作温度范围内的差分飞行时间 (dToF) 精度为 ±12.5ps
- 可在 500:1 的宽动态范围内实现 ±1% 精度
- 在直径为 25mm 的管道上，能够测量的最大流速为 8800 升/小时（40 加仑/分钟）
- 能够检测的最小流速小于 1 升/小时（0.005 加仑/分钟）
- 高精度时间测量分辨率小于 5ps
- 在每秒获取一组结果的条件下总体电流消耗大约为 3µA
- 能够支持直径为 15mm 至 1000mm 的宽管道尺寸
- 气体
- 在低流速到高流速的情况下以及工作温度范围内的差分飞行时间 (dToF) 精度为 ±250ps
- 可在流速高达 12000 升/小时的条件下实现 ±1% 的精度，具有 200:1 的宽动态范围
- 能够测量的流速大于 25000 升/小时
- 能够检测的最小流速小于 3 升/小时
- 高精度时间测量分辨率小于 100ps
- 在每秒获取一组结果的条件下总体电流消耗大约为 20µA
- 水
- 符合并超出 ISO4064、OIML R49、EN 14236 和 EN 1434 精度标准
- 能够直接与标准超声波传感器（高达 2.5MHz）连接
- 集成模拟前端 – 超声波传感解决方案 (USS_A)，包括
- 用于在各种频率下生成多音调脉冲的可编程脉冲发生器 (PPG)
- 用于控制输入和输出通道且具有低阻抗输出驱动器 (4Ω) 的集成 PHY
- 具有高达 8Msps 输出数据速率的高性能高速 12 位模数转换器 (SDHS)
- 具有 –6.5dB 至 30.8dB 增益的可编程增益放大器 (PGA)
- 输出范围为 68MHz 至 80MHz 的高性能 PLL
- 计量测试接口 (MTIF)
- 脉冲发生器和脉冲计数器
- 脉冲率高达 1024 次脉冲/秒 (p/s)
- 计数容量高达 65535（16 位）
- 在 LPM3.5 下以 200nA（典型值）运行
- 低功耗加速器 (LEA)
- 独立于 CPU 运行
- 与 CPU 共享 8KB RAM
- 高效的 256 点复数 FFT：比 Arm®Cortex®-M0+ 内核最多快 40 倍
- 嵌入式微控制器
- 时钟频率高达 16MHz 的 16 位精简指令集计算机 (RISC) 架构
- 宽电源电压范围：1.8V 至 3.6V (1)
- 优化的超低功耗模式
- 激活模式：大约 120 µA/MHz
- 具有实时时钟 (RTC) 的待机模式 (LPM3.5)：450nA (2)
- 关断 (LPM4.5)：30nA
- 铁电随机存取存储器 (FRAM)
- 容量高达 64KB 的非易失性存储器
- 超低功耗写入
- 以 125ns/字（4ms 内写入 64KB）的速度快速写入
- 统一的存储器 = 程序 + 数据 + 存储都处于同一存储空间
- 耐写次数达 1015 次
- 抗辐射和非磁性
- 智能数字外设
- 32 位硬件乘法器 (MPY)
- 6 通道内部 DMA
- 带有日历和报警功能的 RTC
- 6 个 16 位计时器，每个计时器具有多达 7 个捕捉/比较寄存器
- 32 位和 16 位循环冗余校验 (CRC)
- 高性能模拟
- 12 通道模拟比较器
- 12 位 ADC，具有窗口比较器、内部基准和采样保持功能以及多达 8 条外部输入通道
- 具有高达 248 段对比度控制的集成 LCD 驱动器
- 多功能输入/输出端口
- 所有引脚均支持电容式触控功能，无需外部组件
- 可按位、字节和字进行访问（成对访问）
- 所有端口均可从 LPM 进行边沿可选唤醒
- 所有端口均具有可设定的上拉电阻或下拉电阻
- 代码安全性和加密
- 128 位或 256 位 AES 安全加密和解密协处理器
- 用于随机数生成算法的随机数种子
- IP 封装可保护存储器免遭外部访问
- FRAM 可提供固有安全性优势
- 增强型串行通信
- 多达 4 个 eUSCI_A 串行通信端口
- 支持自动波特率检测的 UART
- IrDA 编码和解码
- 多达 2 个 eUSCI_B 串行通信端口
- 支持多从器件寻址的 I2C
- 硬件 UART 或 I2C 引导加载程序 (BSL)
- 多达 4 个 eUSCI_A 串行通信端口
- 灵活的时钟系统
- 具有 10 个可选厂家调整频率的固定频率数控振荡器 (DCO)
- 低功耗低频内部时钟源 (VLO)
- 32kHz 晶振 (LFXT)
- 高频晶振 (HFXT)
- 开发工具和软件
- 器件比较汇总了可用的器件型号和封装选项
1. 最低电源电压受限于 SVS 电平（请参阅 SVS 规格）
2. RTC 由 3.7pF 晶振计时。
3 说明
德州仪器 (TI) MSP430FR604x 和 MSP430FR504x SoC 属于 MSP430 超声波传感微控制器 (MCU) 系列，且功能强大、集成度高，专为各种工业应用而设计：
这些 MCU 提供集成的超声波传感解决方案 (USS_A) 模块，该模块可针对多种流速提供高精度测量。USS 模块高度集成，需要的外部组件极少，因而有助于实现超低功耗计量并降低系统成本。
MSP430FR604x 和 MSP430FR504x 器件采用低功耗加速器 (LEA)，可实现基于 ADC 的高速信号采集以及后续优化数字信号处理，为电池供电型计量应用提供了一款理想的超低功耗、高精度计量解决方案。
USS_A 模块包括可编程脉冲发生器 (PPG) 和具有低阻抗输出驱动器的物理接口 (PHY)，以实现最佳传感器激励和准确的阻抗匹配，从而在零流量漂移 (ZFD) 方面达到最佳效果。USS_A 模块还包含可编程增益放大器 (PGA) 和高速 12 位 8Msps Σ-Δ ADC (SDHS)，便于通过行业标准超声波传感器实现精确的信号采集。
此外，MSP430FR604x 和 MSP430FR504x 还集成了其他外设，可提高系统在计量方面的集成度。它具有计量测试接口 (MTIF) 模块，能够通过脉冲生成来指示仪表测量的流量。它还具有片上 8 通道多路复用器 LCD 驱动器（仅限 MSP430FR604x）、实时时钟 (RTC)、12 位 SAR ADC、模拟比较器、高级加密 (AES256) 模块和循环冗余校验 (CRC) 模块。
MSP430FR604x 和 MSP430FR504x MCU 由广泛的硬件和软件生态系统提供支持，随附参考设计和代码示例，便于您快速开始设计。开发套件包括 MSP-TS430PN80C 80 引脚目标开发板和 EVM430-FR6043 超声波气流计 EVM。TI 还提供免费软件，包括超声波感应设计中心、超声波感应软件库和 MSP430Ware™ 软件。
MSP430FR604x 和 MSP430FR504x MCU 系列集成了 TI 的 FRAM（铁电 RAM）和功耗整体超低 MSP 系统架构，从而使系统设计人员能够在降低能耗的同时提升性能。FRAM 技术兼有 RAM 的低功耗快速写入、灵活性、耐用性和闪存非易失性等特性。
有关完整的模块说明，请参阅《MSP430FR58xx、MSP430FR59xx 和 MSP430FR6xx 系列用户指南》。
器件信息
| 器件型号(1) | 封装(2) | 封装尺寸(3) |
|---|---|---|
| MSP430FR6043IPN | LQFP (80) | 12mm x 12mm |
| MSP430FR60431IPN | LQFP (80) | 12mm x 12mm |
| MSP430FR6041IPN | LQFP (80) | 12mm x 12mm |
| MSP430FR5043IPM | LQFP (64) | 10mm x 10mm |
| MSP430FR50431IPM | LQFP (64) | 10mm x 10mm |
| MSP430FR5041IPM | LQFP (64) | 10mm x 10mm |
| MSP430FR5043IRGC | VQFN (64) | 9mm x 9mm |
| MSP430FR50431IRGC | VQFN (64) | 9mm x 9mm |
| MSP430FR5041IRGC | VQFN (64) | 9mm x 9mm |
(2) 有关提供的所有器件变型的对比，请参见Section 6。
(3) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参阅机械数据（Section 12中）。
4 功能方框图
图 4-1 给出了功能方框图。
注意：该器件具备 12KB RAM，其中 8KB RAM 与 LEA 子系统共享。
图 4-1 功能方框图5 Revision History
Changed from revision A to revision B
Changes from December 2, 2020 to December 1, 2021
- 更改了文档标题Go
- 在说明 中添加了指向应用资源的链接Go
- Updated Section 11.5, Support Resources Go
Changed from initial release to revision A
Changes from January 19, 2019 to December 1, 2020
- 更新了整个文档中的表格、图和交叉参考的编号格式。Go
- Added notes to Section 8.12, Thermal Resistance Characteristics Go
- Added the note that begins "XT1CLK and VLOCLK can be active during LPM4..." in Section 9.5, Operating Modes Go
- Added the INTERRUPT VECTOR REGISTER column, moved register names from the INTERRUPT FLAG column, and corrected interrupt flag names as necessary in Table 9-4, Interrupt Sources, Flags, Vectors, and Signatures Go
- Corrected the interrupt flag bit numbers for ports P4 to P7 (changed PxIFG.2 to PxIFG.7) in Table 9-4, Interrupt Sources, Flags, and Vectors Go
- Corrected a typo in the PySEL0.x column header in Table 9-24, I/O Function Selection Go
- Corrected the address range for "Main: interrupt vectors" in Table 9-52, Memory Organization Go
6 Device Comparison
Table 6-1 summarizes the available family members.
Table 6-1 Device Comparison
| DEVICE(1) | FRAM (KB)(2) |
SRAM (KB) |
CLOCK SYSTEM | LEA | LCD | MTIF | ADC12_B (Channels) | Comp_E (Channels) | Timer_A(3) | Timer_B(4) | eUSCI_A(5) | eUSCI_B(6) | AES | BSL | I/O | PACKAGE |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| MSP430FR6043 | 64 | 12 | DCO HFXT LFXT |
Yes | Yes | Yes | 8 external, 2 internal | 12 | 3, 3(7) 2, 2,2(8) |
7 | 4 | 2 | Yes | UART | 57 | 80 PN (LQFP) |
| MSP430FR60431 | 64 | 12 | DCO HFXT LFXT |
Yes | Yes | Yes | 8 external, 2 internal | 12 | 3, 3(7) 2, 2,2(8) |
7 | 4 | 2 | Yes | I2C | 57 | 80 PN (LQFP) |
| MSP430FR6041 | 32 | 12 | DCO HFXT LFXT |
Yes | Yes | Yes | 8 external, 2 internal | 12 | 3, 3(7) 2, 2,2(8) |
7 | 4 | 2 | Yes | UART | 57 | 80 PN (LQFP) |
| MSP430FR5043 | 64 | 12 | DCO HFXT LFXT |
Yes | No | Yes | 7 external, 2 internal | 11 | 3, 3(7) 2, 2,2(8) |
7 | 4 | 2 | Yes | UART | 44 | 64 PM (LQFP) 64 RGC (VQFN) |
| MSP430FR50431 | 64 | 12 | DCO HFXT LFXT |
Yes | No | Yes | 7 external, 2 internal | 11 | 3, 3(7) 2, 2,2(8) |
7 | 4 | 2 | Yes | I2C | 44 | 64 PM (LQFP) 64 RGC (VQFN) |
| MSP430FR5041 | 32 | 12 | DCO HFXT LFXT |
Yes | No | Yes | 7 external, 2 internal | 11 | 3, 3(7) 2, 2,2(8) |
7 | 4 | 2 | Yes | UART | 44 | 64 PM (LQFP) 64 RGC (VQFN) |
(1) For the most current package and ordering information, see the Package Option Addendum in Section 12, or see the TI website at www.ti.com.
(2) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare
registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the
first instantiation having 3 capture/compare registers and PWM output generators and the second instantiation having 5 capture/compare
registers and PWM output generators, respectively.
(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare
registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the
first instantiation having 3 capture/compare registers and PWM output generators and the second instantiation having 5 capture/compare
registers and PWM output generators, respectively.
(5) eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.
(6) eUSCI_B supports I2C with multiple slave addresses and SPI.
(7) Timers TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.
(8) Timers TA2 and TA3 provide only internal capture/compare inputs and only internal PWM outputs (if any) whereas Timer
TA4 provides internal, external capture/compare inputs and internal, external PWM outputs (Note: TA4 in the RGZ package provide only
internal capture/compare inputs and only internal PWM outputs.).
6.1 Related Products
For information about other devices in this family of products or related products, see the following links.
TI 16-bit and 32-bit microcontrollers
High-performance, low-power solutions to enable the autonomous future
Products for MSP430 ultra-low-power sensing & measurement MCUs
One platform. One ecosystem. Endless possibilities.
Find reference designs leveraging the best in TI technology to solve your system-level challenges
7 Terminal Configuration and Functions
7.1 Pin Diagrams
Figure 7-1 shows the pinout of the 80-pin PM package.
On devices with UART BSL: P2.0 is BSLTX, P2.1 is BSLRX
On devices with I2C BSL: P1.6 is BSLSDA, P1.7 is BSLSCL
Figure 7-1 80-Pin PN Package (Top View) Figure 7-2 shows the pinout of the 64-pin PM and 64-pin RGC package.
On devices with UART BSL: P2.0 is BSLTX, P2.1 is BSLRX
On devices with I2C BSL: P1.6 is BSLSDA, P1.7 is BSLSCL
Figure 7-2 64-Pin PM or RGC Package (Top View) 7.2 Pin Attributes
Table 7-1 Pin Attributes
| PIN NUMBER(1) | SIGNAL NAME(1)(4) | SIGNAL TYPE(2) | BUFFER TYPE(3) | POWER SOURCE(5) | RESET STATE AFTER BOR(7) | |
|---|---|---|---|---|---|---|
| FR6043, FR6041 | FR5043, FR5041 | |||||
| 1 | 1 | AVCC1 | P | Power | – | N/A |
| 2 | 2 | P2.2 | I/O | LVCMOS | DVCC | OFF |
| COUT | O | LVCMOS | DVCC | – | ||
| UCA0CLK | I/O | LVCMOS | DVCC | – | ||
| A14 | I | Analog | DVCC | – | ||
| C14 | I | Analog | DVCC | – | ||
| 3 | – | P2.3 | I/O | LVCMOS | DVCC | OFF |
| TA0.0 | I/O | LVCMOS | DVCC | – | ||
| UCA0STE | I/O | LVCMOS | DVCC | – | ||
| A15 | I | Analog | DVCC | – | ||
| C15 | I | Analog | DVCC | – | ||
| 4 | 3 | P1.0 | I/O | LVCMOS | DVCC | OFF |
| UCA1CLK | I/O | LVCMOS | DVCC | – | ||
| TA1.0 | I/O | LVCMOS | DVCC | – | ||
| A0 | I | Analog | DVCC | – | ||
| C0 | I | Analog | DVCC | – | ||
| VREF- | O | Analog | DVCC | – | ||
| VeREF- | I | Analog | DVCC | – | ||
| 5 | 4 | P1.1 | I/O | LVCMOS | DVCC | OFF |
| UCA1STE | I/O | LVCMOS | DVCC | – | ||
| TA4.0 | I/O | LVCMOS | DVCC | – | ||
| A1 | I | Analog | DVCC | – | ||
| C1 | I | Analog | DVCC | – | ||
| VREF+ | O | Analog | DVCC | – | ||
| VeREF+ | I | Analog | DVCC | – | ||
| 6 | 5 | AVSS2 | P | Power | – | N/A |
| 7 | 6 | PJ.4 | I/O | LVCMOS | DVCC | OFF |
| LFXIN | I | Analog | DVCC | – | ||
| 8 | 7 | PJ.5 | I/O | LVCMOS | DVCC | OFF |
| LFXOUT | O | Analog | DVCC | – | ||
| 9 | 8 | AVSS3 | P | Power | – | N/A |
| 10 | 9 | PJ.6 | I/O | LVCMOS | DVCC | – |
| HFXIN | I | Analog | DVCC | – | ||
| USSXT_BOUT | O | Analog | DVCC | – | ||
| 11 | 10 | PJ.7 | I/O | LVCMOS | DVCC | OFF |
| HFXOUT | O | Analog | DVCC | – | ||
| 12 | – | P2.4 | I/O | LVCMOS | DVCC | OFF |
| TA0CLK | I | LVCMOS | DVCC | – | ||
| TB0CLK | I | LVCMOS | DVCC | – | ||
| TA1CLK | I | LVCMOS | DVCC | – | ||
| S24 | O | Analog | DVCC | – | ||
| 13 | – | P2.6 | I/O | LVCMOS | DVCC | OFF |
| UCA0TXD | O | LVCMOS | DVCC | – | ||
| UCA0SIMO | I/O | LVCMOS | DVCC | – | ||
| TA1.2 | I/O | LVCMOS | DVCC | – | ||
| TA1.2C | I/O | LVCMOS | DVCC | – | ||
| S23 | O | Analog | DVCC | – | ||
| 14 | – | P2.7 | I/O | LVCMOS | DVCC | OFF |
| UCA0RXD | I | LVCMOS | DVCC | – | ||
| UCA0SOMI | I/O | LVCMOS | DVCC | – | ||
| TA4.1 | I/O | LVCMOS | DVCC | – | ||
| TA4.1C | I/O | LVCMOS | DVCC | – | ||
| S22 | O | Analog | DVCC | – | ||
| 15 | 11 | TEST | I | LVCMOS | DVCC | PD |
| SBWTCK | I | LVCMOS | DVCC | – | ||
| 16 | 12 | RST | I/O | LVCMOS | DVCC | PU |
| NMI | I | LVCMOS | DVCC | – | ||
| SBWTDIO | I/O | LVCMOS | DVCC | – | ||
| 17 | 13 | PJ.0 | I/O | LVCMOS | DVCC | OFF |
| TDO | O | LVCMOS | DVCC | – | ||
| UCA2CLK | I/O | LVCMOS | DVCC | – | ||
| SRSCG1 | O | LVCMOS | DVCC | – | ||
| DMAE0 | I | LVCMOS | DVCC | – | ||
| C10 | I | Analog | DVCC | – | ||
| 18 | 14 | PJ.1 | I/O | LVCMOS | DVCC | OFF |
| TDI | I | LVCMOS | DVCC | – | ||
| TCLK | I | LVCMOS | DVCC | – | ||
| UCA2STE | I/O | LVCMOS | DVCC | – | ||
| SRSCG0 | O | LVCMOS | DVCC | – | ||
| TA4CLK | I | LVCMOS | DVCC | – | ||
| C11 | I | Analog | DVCC | – | ||
| 19 | 15 | PJ.2 | I/O | LVCMOS | DVCC | OFF |
| TMS | I | LVCMOS | DVCC | – | ||
| UCA2TXD | O | LVCMOS | DVCC | – | ||
| UCA2SIMO | I/O | LVCMOS | DVCC | – | ||
| SROSCOFF | O | LVCMOS | DVCC | – | ||
| TB0OUTH | I | LVCMOS | DVCC | – | ||
| C12 | I | Analog | DVCC | – | ||
| 20 | 16 | PJ.3 | I/O | LVCMOS | DVCC | OFF |
| TCK | I | LVCMOS | DVCC | – | ||
| UCA2RXD | I | LVCMOS | DVCC | – | ||
| UCA2SOMI | I/O | LVCMOS | DVCC | – | ||
| SRCPUOFF | O | LVCMOS | DVCC | – | ||
| TB0.6 | I/O | LVCMOS | DVCC | – | ||
| C13 | I | Analog | DVCC | – | ||
| 21 | 17 | DVSS1 | P | Power | – | N/A |
| 22 | 18 | DVCC1 | P | Power | – | N/A |
| 23 | – | P2.5 | I/O | LVCMOS | DVCC | OFF |
| TA0.2 | I/O | LVCMOS | DVCC | – | ||
| TA4.0 | I/O | LVCMOS | DVCC | – | ||
| S21 | O | Analog | DVCC | – | ||
| 24 | – | P3.0 | I/O | LVCMOS | DVCC | OFF |
| TB0.0 | I/O | LVCMOS | DVCC | – | ||
| S20 | O | Analog | DVCC | – | ||
| 25 | 19 | P1.2 | I/O | LVCMOS | DVCC | OFF |
| UCA1TXD | O | LVCMOS | DVCC | – | ||
| UCA1SIMO | I/O | LVCMOS | DVCC | – | ||
| TA1.0 | I/O | LVCMOS | DVCC | – | ||
| A8 | I | Analog | DVCC | – | ||
| C8 | I | Analog | DVCC | – | ||
| 26 | 20 | P1.3 | I/O | LVCMOS | DVCC | OFF |
| UCA1RXD | I | LVCMOS | DVCC | – | ||
| UCA1SOMI | I/O | LVCMOS | DVCC | – | ||
| TA1.1 | I/O | LVCMOS | DVCC | – | ||
| A9 | I | Analog | DVCC | – | ||
| C9 | I | Analog | DVCC | – | ||
| 27 | 21 | P2.0 | I/O | LVCMOS | DVCC | OFF |
| UCA1CLK | I/O | LVCMOS | DVCC | – | ||
| UCA3TXD | O | LVCMOS | DVCC | – | ||
| UCA3SIMO | I/O | LVCMOS | DVCC | – | ||
| S19 | O | Analog | DVCC | – | ||
| 28 | 22 | P2.1 | I/O | LVCMOS | DVCC | OFF |
| UCA1STE | I/O | LVCMOS | DVCC | – | ||
| UCA3RXD | I | LVCMOS | DVCC | – | ||
| UCA3SOMI | I/O | LVCMOS | DVCC | – | ||
| S18 | O | Analog | DVCC | – | ||
| 29 | 23 | P1.6 | I/O | LVCMOS | DVCC | OFF |
| UCA3STE | I/O | LVCMOS | DVCC | – | ||
| UCB0SIMO | I/O | LVCMOS | DVCC | – | ||
| UCB0SDA | I/O | LVCMOS | DVCC | – | ||
| S17 | O | Analog | DVCC | – | ||
| 30 | 24 | P1.7 | I/O | LVCMOS | DVCC | OFF |
| USSTRG | I | LVCMOS | DVCC | – | ||
| UCA3CLK | I/O | LVCMOS | DVCC | – | ||
| UCB0SOMI | I/O | LVCMOS | DVCC | – | ||
| UCB0SCL | I/O | LVCMOS | DVCC | – | ||
| S16 | O | Analog | DVCC | – | ||
| 31 | 25 | P1.4 | I/O | LVCMOS | DVCC | OFF |
| TB0.4 | I/O | LVCMOS | DVCC | – | ||
| UCA0STE | I/O | LVCMOS | DVCC | – | ||
| A2 | I | Analog | DVCC | – | ||
| C2 | I | Analog | DVCC | – | ||
| 32 | 26 | P1.5 | I/O | LVCMOS | DVCC | OFF |
| TB0.5 | I/O | LVCMOS | DVCC | – | ||
| UCB0CLK | I/O | LVCMOS | DVCC | – | ||
| A3 | I | Analog | DVCC | – | ||
| C3 | I | Analog | DVCC | – | ||
| 33 | 27 | P3.1 | I/O | LVCMOS | DVCC | OFF |
| TA1CLK | I | LVCMOS | DVCC | – | ||
| TB0.1 | I/O | LVCMOS | DVCC | – | ||
| MTIF_OUT_IN | I/O | LVCMOS | DVCC | – | ||
| 34 | 28 | P4.0 | I/O | LVCMOS | DVCC | OFF |
| RTCCLK | O | LVCMOS | DVCC | – | ||
| TA4.1 | O | LVCMOS | DVCC | – | ||
| MTIF_PIN_EN | I | LVCMOS | DVCC | – | ||
| 35 | 29 | P4.1 | I/O | LVCMOS | DVCC | OFF |
| UCA0CLK | I/O | LVCMOS | DVCC | – | ||
| TB0.4 | I/O | LVCMOS | DVCC | – | ||
| UCA3RXD | I | LVCMOS | DVCC | – | ||
| UCA3SOMI | I/O | LVCMOS | DVCC | – | ||
| S15 | O | Analog | DVCC | – | ||
| 36 | 30 | P4.2 | I/O | LVCMOS | DVCC | OFF |
| UCA0STE | I/O | LVCMOS | DVCC | – | ||
| TB0.5 | I/O | LVCMOS | DVCC | – | ||
| UCA3SIMO | I/O | LVCMOS | DVCC | – | ||
| UCA3TXD | O | LVCMOS | DVCC | – | ||
| S14 | O | Analog | DVCC | – | ||
| 37 | 31 | P4.3 | I/O | LVCMOS | DVCC | OFF |
| UCA0TXD | O | LVCMOS | DVCC | – | ||
| UCA0SIMO | I/O | LVCMOS | DVCC | – | ||
| S13 | O | Analog | DVCC | – | ||
| 38 | 32 | P4.4 | I/O | LVCMOS | DVCC | OFF |
| UCA0RXD | I | LVCMOS | DVCC | – | ||
| UCA0SOMI | I/O | LVCMOS | DVCC | – | ||
| S12 | O | Analog | DVCC | – | ||
| 39 | – | P4.5 | I/O | LVCMOS | DVCC | OFF |
| TA0CLK | I | LVCMOS | DVCC | – | ||
| TA1CLK | I | LVCMOS | DVCC | – | ||
| S11 | O | Analog | DVCC | – | ||
| 40 | – | P4.6 | I/O | LVCMOS | DVCC | OFF |
| TB0CLK | I | LVCMOS | DVCC | – | ||
| TA4CLK | I | LVCMOS | DVCC | – | ||
| S10 | O | Analog | DVCC | – | ||
| 41 | 33 | DVSS2 | P | Power | – | N/A |
| 42 | – | P4.7 | I/O | LVCMOS | DVCC | OFF |
| DMAE0 | I | LVCMOS | DVCC | – | ||
| S9 | O | Analog | DVCC | – | ||
| 43 | 34 | P5.0 | I/O | LVCMOS | DVCC | OFF |
| TB0.0 | I/O | LVCMOS | DVCC | – | ||
| UCA2TXD | O | LVCMOS | DVCC | – | ||
| UCA2SIMO | I/O | LVCMOS | DVCC | – | ||
| S8 | O | Analog | DVCC | – | ||
| 44 | 35 | P5.1 | I/O | LVCMOS | DVCC | OFF |
| TB0.1 | O | LVCMOS | DVCC | – | ||
| UCA2RXD | I | LVCMOS | DVCC | – | ||
| UCA2SOMI | I/O | LVCMOS | DVCC | – | ||
| S7 | O | Analog | DVCC | – | ||
| 45 | 36 | P5.2 | I/O | LVCMOS | DVCC | OFF |
| TB0.2 | O | LVCMOS | DVCC | – | ||
| UCA2CLK | I/O | LVCMOS | DVCC | – | ||
| S6 | O | Analog | DVCC | – | ||
| 46 | 37 | P5.3 | I/O | LVCMOS | DVCC | OFF |
| TB0.3 | O | LVCMOS | DVCC | – | ||
| UCA2STE | I/O | LVCMOS | DVCC | – | ||
| S5 | O | Analog | DVCC | – | ||
| 47 | 38 | P5.4 | I/O | LVCMOS | DVCC | OFF |
| TA0.0 | I/O | LVCMOS | DVCC | – | ||
| UCB1CLK | I/O | LVCMOS | DVCC | – | ||
| TA4.0 | O | LVCMOS | DVCC | – | ||
| S4 | O | Analog | DVCC | – | ||
| 48 | 39 | P5.5 | I/O | LVCMOS | DVCC | OFF |
| TA4.1 | I/O | LVCMOS | DVCC | – | ||
| UCB1SIMO | I/O | LVCMOS | DVCC | – | ||
| UCB1SDA | I/O | LVCMOS | DVCC | – | ||
| S3 | O | Analog | DVCC | – | ||
| 49 | 40 | P5.6 | I/O | LVCMOS | DVCC | OFF |
| TB0OUTH | I | LVCMOS | DVCC | – | ||
| UCB1SOMI | I/O | LVCMOS | DVCC | – | ||
| UCB1SCL | I/O | LVCMOS | DVCC | – | ||
| S2 | O | Analog | DVCC | – | ||
| 50 | 41 | P5.7 | I/O | LVCMOS | DVCC | OFF |
| TA0.2 | I/O | LVCMOS | DVCC | – | ||
| UCB1STE | I/O | LVCMOS | DVCC | – | ||
| S1 | O | Analog | DVCC | – | ||
| 51 | 42 | P6.0 | I/O | LVCMOS | DVCC | OFF |
| TA0CLK | I | LVCMOS | DVCC | – | ||
| COUT | I | LVCMOS | DVCC | – | ||
| S0 | O | Analog | DVCC | – | ||
| 52 | 43 | P6.4 | I/O | LVCMOS | DVCC | OFF |
| MCLK | O | LVCMOS | DVCC | – | ||
| COM0 | O | Analog | DVCC | – | ||
| 53 | 44 | P6.5 | I/O | LVCMOS | DVCC | OFF |
| SMCLK | O | LVCMOS | DVCC | – | ||
| COM1 | O | Analog | DVCC | – | ||
| S34 | O | Analog | DVCC | – | ||
| 54 | 45 | P6.6 | I/O | LVCMOS | DVCC | OFF |
| ACLK | O | LVCMOS | DVCC | – | ||
| COM2 | O | Analog | DVCC | – | ||
| S31 | O | Analog | DVCC | – | ||
| 55 | 46 | P7.0 | I/O | LVCMOS | DVCC | OFF |
| TA1.0 | I/O | LVCMOS | DVCC | – | ||
| TA1.2 | I/O | LVCMOS | DVCC | – | ||
| XPB0 | O | Analog | 1.5 V | – | ||
| S30 | O | Analog | DVCC | – | ||
| 56 | – | P6.1 | I/O | LVCMOS | DVCC | OFF |
| RTCCLK | O | LVCMOS | DVCC | – | ||
| R03 | I/O | Analog | DVCC | – | ||
| S33 | O | Analog | DVCC | – | ||
| 57 | 47 | P6.2 | I/O | LVCMOS | DVCC | OFF |
| TB0CLK | I | LVCMOS | DVCC | – | ||
| R13 | I/O | Analog | DVCC | – | ||
| LCDREF | I | Analog | - | – | ||
| S32 | O | Analog | DVCC | – | ||
| 58 | 48 | DVSS3 | P | Power | – | N/A |
| 59 | 49 | DVCC3 | P | Power | – | N/A |
| 60 | – | P6.3 | I/O | LVCMOS | DVCC | OFF |
| COM7 | O | Analog | DVCC | – | ||
| R23 | I/O | Analog | DVCC | – | ||
| 61 | – | R33 | I/O | Analog | DVCC | - |
| LCDCAP | I/O | Analog | DVCC | – | ||
| 62 | – | P6.7 | I/O | LVCMOS | DVCC | OFF |
| TA0.1 | I/O | LVCMOS | DVCC | – | ||
| COM4 | O | Analog | DVCC | – | ||
| S29 | O | Analog | DVCC | – | ||
| 63 | – | P3.2 | I/O | LVCMOS | DVCC | OFF |
| TA1.1 | I/O | LVCMOS | DVCC | – | ||
| COM5 | O | Analog | DVCC | – | ||
| S28 | O | Analog | DVCC | – | ||
| 64 | 50 | P3.3 | I/O | LVCMOS | DVCC | OFF |
| MCLK | O | LVCMOS | DVCC | – | ||
| TB0.3 | I/O | LVCMOS | DVCC | – | ||
| XPB1 | O | Analog | 1.5 V | – | ||
| S25 | O | Analog | DVCC | – | ||
| 65 | 51 | P3.4 | I/O | LVCMOS | DVCC | OFF |
| SMCLK | O | LVCMOS | DVCC | – | ||
| COM6 | O | Analog | DVCC | – | ||
| DMAE0 | I | LVCMOS | DVCC | – | ||
| S27 | O | Analog | DVCC | – | ||
| 66 | 52 | P3.5 | I/O | LVCMOS | DVCC | OFF |
| ACLK | O | LVCMOS | DVCC | – | ||
| COM3 | O | Analog | DVCC | – | ||
| COUT | O | LVCMOS | DVCC | – | ||
| S26 | O | Analog | DVCC | – | ||
| 67 | 53 | CH1_IN | I | Analog | PVCC | – |
| 68 | 54 | CH1_OUT | O | Analog | PVCC | – |
| 69 | 55 | PVSS | P | Power | – | N/A |
| 70 | 56 | PVCC | P | Power | – | N/A |
| 71 | 57 | PVCC | P | Power | – | N/A |
| 72 | 58 | PVSS | P | Power | – | N/A |
| 73 | 59 | CH0_OUT | O | Analog | PVCC | – |
| 74 | 60 | CH0_IN | I | Analog | PVCC | – |
| 75 | – | P3.6 | I/O | LVCMOS | DVCC | OFF |
| UCB1SIMO | I/O | LVCMOS | DVCC | – | ||
| UCB1SDA | I/O | LVCMOS | DVCC | – | ||
| TB0.6 | I/O | LVCMOS | DVCC | – | ||
| USSXT_BOUT | I/O | LVCMOS | DVCC | – | ||
| S35 | O | Analog | DVCC | – | ||
| 76 | – | P3.7 | I/O | LVCMOS | DVCC | OFF |
| UCB1SOMI | I/O | LVCMOS | DVCC | – | ||
| UCB1SCL | I/O | LVCMOS | DVCC | – | ||
| TB0.2 | I/O | LVCMOS | DVCC | – | ||
| TB0OUTH | I | LVCMOS | DVCC | – | ||
| S36 | O | Analog | DVCC | – | ||
| 77 | 61 | AVSS4 | P | Power | – | N/A |
| 78 | 62 | USSXTIN(6) | I | Analog | 1.5 V | – |
| 79 | 63 | USSXTOUT(6) | O | Analog | 1.5 V | – |
| 80 | 64 | AVSS1 | P | Power | – | N/A |
(1) The signal that is listed first for each pin is the reset default pin name.
(2) Signal Types: I = Input, O = Output, I/O = Input or Output.
(3) Buffer Types: LVCMOS, Analog, or Power (see Table 7-3 for details)
(4) To determine the pin mux encodings for each pin, see Section 9.14.
(5) The power source shown in this table is the I/O power source, which may differ from the module power source.
(6) Do not connect the USSXTIN and USSXTOUT pins to AVCC or DVCC. USSXTIN does not support bypass mode, so do not drive an external clock to USSXTIN pin.
(7) Reset States:
OFF = High impedance with Schmitt-trigger input and pullup or pulldown (if available) disabled
PU = Pullup is enabled
PD = Pulldown is enabled
N/A = Not applicable
OFF = High impedance with Schmitt-trigger input and pullup or pulldown (if available) disabled
PU = Pullup is enabled
PD = Pulldown is enabled
N/A = Not applicable
7.3 Signal Descriptions
Section 7.3 describes the signals for all device variants and package options.
Table 7-2 Signal Descriptions
| FUNCTION | SIGNAL NAME | PIN NO.(1) | PIN TYPE(2) | DESCRIPTION | |
|---|---|---|---|---|---|
| 80-PIN PN | 64-PIN PM OR RGC | ||||
| ADC | A0 | 4 | 3 | I | ADC analog input A0 |
| A1 | 5 | 4 | I | ADC analog input A1 | |
| A2 | 31 | 25 | I | ADC analog input A2 | |
| A3 | 32 | 26 | I | ADC analog input A3 | |
| – | AVSS | AVSS | I | ADC analog input A4 | |
| – | AVSS | AVSS | I | ADC analog input A5 | |
| – | AVSS | AVSS | I | ADC analog input A6 | |
| – | AVSS | AVSS | I | ADC analog input A7 | |
| A8 | 25 | 19 | I | ADC analog input A8 | |
| A9 | 26 | 20 | I | ADC analog input A9 | |
| – | AVSS | AVSS | I | ADC analog input A10 | |
| – | AVSS | AVSS | I | ADC analog input A11 | |
| – | AVSS | AVSS | I | ADC analog input A12 | |
| – | AVSS | AVSS | I | ADC analog input A13 | |
| A14 | 2 | 2 | I | ADC analog input A14 | |
| A15 | 3 | – | I | ADC analog input A15 | |
| VREF+ | 5 | 4 | O | Output of positive reference voltage | |
| VREF- | 4 | 3 | O | Output of negative reference voltage | |
| VeREF+ | 5 | 4 | I | Input for an external positive reference voltage to the ADC | |
| VeREF- | 4 | 3 | I | Input for an external negative reference voltage to the ADC | |
| Clock | ACLK | 54, 66 | 45, 52 | O | ACLK output |
| HFXIN | 10 | 9 | I | Input for high-frequency crystal oscillator HFXT | |
| HFXOUT | 11 | 10 | O | Output for high-frequency crystal oscillator HFXT | |
| LFXIN | 7 | 6 | I | Input for low-frequency crystal oscillator LFXT | |
| LFXOUT | 8 | 7 | O | Output of low-frequency crystal oscillator LFXT | |
| MCLK | 52, 64 | 43, 50 | O | MCLK output | |
| SMCLK | 53, 65 | 44, 51 | O | SMCLK output | |
| Comparator | C0 | 4 | 3 | I | Comparator input C0 |
| C1 | 5 | 4 | I | Comparator input C1 | |
| C2 | 31 | 25 | I | Comparator input C2 | |
| C3 | 32 | 26 | I | Comparator input C3 | |
| Not connected | 4 | 3 | I | Comparator input C4 | |
| Not connected | 4 | 3 | I | Comparator input C5 | |
| Not connected | 4 | 3 | I | Comparator input C6 | |
| Not connected | 4 | 3 | I | Comparator input C7 | |
| C8 | 25 | 19 | I | Comparator input C8 | |
| C9 | 26 | 20 | I | Comparator input C9 | |
| C10 | 17 | 13 | I | Comparator input C10 | |
| C11 | 18 | 14 | I | Comparator input C11 | |
| C12 | 19 | 15 | I | Comparator input C12 | |
| C13 | 20 | 16 | I | Comparator input C13 | |
| C14 | 2 | 2 | I | Comparator input C14 | |
| C15 | 3 | – | I | Comparator input C15 | |
| COUT | 2, 51, 66 | 2, 42, 52 | O | Comparator output | |
| DMA | DMAE0 | 17, 42, 65 | 13, 51 | I | External DMA trigger |
| Debug | SBWTCK | 15 | 11 | I | Spy-Bi-Wire input clock |
| SBWTDIO | 16 | 12 | I/O | Spy-Bi-Wire data input/output | |
| SRCPUOFF | 20 | 16 | O | Low-power debug: CPU Status register bit CPUOFF | |
| SROSCOFF | 19 | 15 | O | Low-power debug: CPU Status register bit OSCOFF | |
| SRSCG0 | 18 | 14 | O | Low-power debug: CPU Status register bit SCG0 | |
| SRSCG1 | 17 | 13 | O | Low-power debug: CPU Status register bit SCG1 | |
| TCK | 20 | 16 | I | Test clock | |
| TCLK | 18 | 14 | I | Test clock input | |
| TDI | 18 | 14 | I | Test data input | |
| TDO | 17 | 13 | O | Test data output port | |
| TEST | 15 | 11 | I | Test mode pin – select digital I/O on JTAG pins | |
| TMS | 19 | 15 | I | Test mode select | |
| GPIO, P1 | P1.0 | 4 | 3 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 |
| P1.1 | 5 | 4 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P1.2 | 25 | 19 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P1.3 | 26 | 20 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P1.4 | 31 | 25 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P1.5 | 32 | 26 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P1.6 | 29 | 23 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P1.7 | 30 | 24 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| GPIO, P2 | P2.0 | 27 | 21 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 |
| P2.1 | 28 | 22 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P2.2 | 2 | 2 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P2.3 | 3 | – | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P2.4 | 12 | – | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P2.5 | 23 | – | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P2.6 | 13 | – | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P2.7 | 14 | – | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| GPIO, P3 | P3.0 | 24 | – | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 |
| P3.1 | 33 | 27 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P3.2 | 63 | – | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P3.3 | 64 | 50 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P3.4 | 65 | 51 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P3.5 | 66 | 52 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P3.6 | 75 | – | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P3.7 | 76 | – | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| GPIO, P4 | P4.0 | 34 | 28 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 |
| P4.1 | 35 | 29 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P4.2 | 36 | 30 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P4.3 | 37 | 31 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P4.4 | 38 | 32 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P4.5 | 39 | – | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P4.6 | 40 | – | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P4.7 | 42 | – | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| GPIO, P5 | P5.0 | 43 | 34 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 |
| P5.1 | 44 | 35 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P5.2 | 45 | 36 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P5.3 | 46 | 37 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P5.4 | 47 | 38 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P5.5 | 48 | 39 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P5.6 | 49 | 40 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P5.7 | 50 | 41 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| GPIO, P6 | P6.0 | 51 | 42 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 |
| P6.1 | 56 | – | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P6.2 | 57 | 47 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P6.3 | 60 | – | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P6.4 | 52 | 43 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P6.5 | 53 | 44 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P6.6 | 54 | 45 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| P6.7 | 62 | – | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 | |
| GPIO, P7 | P7.0 | 55 | 46 | I/O | General-purpose digital I/O with port interrupt and wakeup from LPMx.5 |
| GPIO, PJ | PJ.0 | 17 | 13 | I/O | General-purpose digital I/O |
| PJ.1 | 18 | 14 | I/O | General-purpose digital I/O | |
| PJ.2 | 19 | 15 | I/O | General-purpose digital I/O | |
| PJ.3 | 20 | 16 | I/O | General-purpose digital I/O | |
| PJ.4 | 7 | 6 | I/O | General-purpose digital I/O | |
| PJ.5 | 8 | 7 | I/O | General-purpose digital I/O | |
| PJ.6 | 10 | 9 | I/O | General-purpose digital I/O | |
| PJ.7 | 11 | 10 | I/O | General-purpose digital I/O | |
| I2C | UCB0SCL | 30 | 24 | I/O | I2C clock – eUSCI_B0 I2C mode |
| UCB0SDA | 29 | 23 | I/O | I2C data – eUSCI_B0 I2C mode | |
| UCB1SCL | 49, 76 | 40 | I/O | I2C clock – eUSCI_B1 I2C mode | |
| UCB1SDA | 48, 75 | 39 | I/O | I2C data – eUSCI_B1 I2C mode | |
| LCD | COM0 | 52 | – | O | LCD common output COM0 for LCD backplane |
| COM1 | 53 | – | O | LCD common output COM1 for LCD backplane | |
| COM2 | 54 | – | O | LCD common output COM2 for LCD backplane | |
| COM3 | 66 | – | O | LCD common output COM3 for LCD backplane | |
| COM4 | 62 | – | O | LCD common output COM4 for LCD backplane | |
| COM5 | 63 | – | O | LCD common output COM5 for LCD backplane | |
| COM6 | 65 | – | O | LCD common output COM6 for LCD backplane | |
| COM7 | 60 | – | O | LCD common output COM7 for LCD backplane | |
| LCDCAP | 61 | – | I/O | LCD capacitor connection CAUTION: LCDCAP/R33 must be connected to DVSS if not used. |
|
| LCDREF | 57 | – | I | External reference voltage input for regulated LCD voltage | |
| R03 | 56 | – | I/O | Input/output port of lowest analog LCD voltage (V5) | |
| R13 | 57 | – | I/O | Input/output port of third most positive analog LCD voltage (V3 or V4) | |
| R23 | 60 | – | I/O | Input/output port of second most positive analog LCD voltage (V2) | |
| R33 | 61 | – | I/O | Input/output port of most positive analog LCD voltage (V1) CAUTION: LCDCAP/R33 must be connected to DVSS if not used. |
|
| LCD | S0 | 51 | – | O | LCD segment output 0 |
| S1 | 50 | – | O | LCD segment output 1 | |
| S2 | 49 | – | O | LCD segment output 2 | |
| S3 | 48 | – | O | LCD segment output 3 | |
| S4 | 47 | – | O | LCD segment output 4 | |
| S5 | 46 | – | O | LCD segment output 5 | |
| S6 | 45 | – | O | LCD segment output 6 | |
| S7 | 44 | – | O | LCD segment output 7 | |
| S8 | 43 | – | O | LCD segment output 8 | |
| S9 | 42 | – | O | LCD segment output 9 | |
| S10 | 40 | – | O | LCD segment output 10 | |
| S11 | 39 | – | O | LCD segment output 11 | |
| S12 | 38 | – | O | LCD segment output 12 | |
| S13 | 37 | – | O | LCD segment output 13 | |
| S14 | 36 | – | O | LCD segment output 14 | |
| S15 | 35 | – | O | LCD segment output 15 | |
| S16 | 30 | – | O | LCD segment output 16 | |
| S17 | 29 | – | O | LCD segment output 17 | |
| S18 | 28 | – | O | LCD segment output 18 | |
| S19 | 27 | – | O | LCD segment output 19 | |
| S20 | 24 | – | O | LCD segment output 20 | |
| S21 | 23 | – | O | LCD segment output 21 | |
| S22 | 14 | – | O | LCD segment output 22 | |
| S23 | 13 | – | O | LCD segment output 23 | |
| S24 | 12 | – | O | LCD segment output 24 | |
| S25 | 64 | – | O | LCD segment output 25 | |
| S26 | 66 | – | O | LCD segment output 26 | |
| S27 | 65 | – | O | LCD segment output 27 | |
| S28 | 63 | – | O | LCD segment output 28 | |
| S29 | 62 | – | O | LCD segment output 29 | |
| S30 | 55 | – | O | LCD segment output 30 | |
| S31 | 54 | – | O | LCD segment output 31 | |
| S32 | 57 | – | O | LCD segment output 32 | |
| S33 | 56 | – | O | LCD segment output 33 | |
| S34 | 53 | – | O | LCD segment output 34 | |
| S35 | 75 | – | O | LCD segment output 35 | |
| S36 | 76 | – | O | LCD segment output 36 | |
| MTIF | MTIF_PIN_EN | 34 | 28 | I | Meter test Interface pin enable |
| MTIF_OUT_IN | 33 | 27 | I/O | Meter test Interface In/Out | |
| Power | AVCC1 | 1 | 1 | P | Analog power supply |
| AVSS1 | 80 | 64 | P | Analog ground supply | |
| AVSS2 | 6 | 5 | P | Analog ground supply | |
| AVSS3 | 9 | 8 | P | Analog ground supply | |
| AVSS4 | 77 | 61 | P | Analog ground supply | |
| DVCC1 | 22 | 18 | P | Digital power supply | |
| DVCC3 | 59 | 49 | P | Digital power supply | |
| DVSS1 | 21 | 17 | P | Digital ground supply | |
| DVSS2 | 41 | 33 | P | Digital ground supply | |
| DVSS3 | 58 | 48 | P | Digital ground supply | |
| PVCC | 70, 71 | 56, 57 | P | USS power supply | |
| PVSS | 69, 72 | 55, 58 | P | USS ground supply | |
| RTC | RTCCLK | 34, 56 | 28 | O | RTC clock calibration output |
| SPI | UCA0CLK | 2, 35 | 2, 29 | I/O | Clock signal input – eUSCI_A0 SPI slave mode Clock signal output – eUSCI_A0 SPI master mode |
| UCA0SIMO | 13, 37 | 31 | I/O | Slave in/master out – eUSCI_A0 SPI mode | |
| UCA0SOMI | 14, 38 | 32 | I/O | Slave out/master in – eUSCI_A0 SPI mode | |
| UCA0STE | 3, 36 | 30 | I/O | Slave transmit enable – eUSCI_A0 SPI mode | |
| UCA1CLK | 4, 27 | 3, 21 | I/O | Clock signal input – eUSCI_A1 SPI slave mode Clock signal output – eUSCI_A1 SPI master mode |
|
| UCA1SIMO | 25 | 19 | I/O | Slave in/master out – eUSCI_A1 SPI mode | |
| UCA1SOMI | 26 | 20 | I/O | Slave out/master in – eUSCI_A1 SPI mode | |
| UCA1STE | 5, 28 | 4, 22 | I/O | Slave transmit enable – eUSCI_A1 SPI mode | |
| UCA2CLK | 45 | 36 | I/O | Clock signal input – eUSCI_A2 SPI slave mode Clock signal output – eUSCI_A2 SPI master mode |
|
| UCA2SIMO | 19, 43 | 34 | I/O | Slave in/master out – eUSCI_A2 SPI mode | |
| UCA2SOMI | 20, 44 | 35 | I/O | Slave out/master in – eUSCI_A2 SPI mode | |
| UCA2STE | 46 | 37 | I/O | Slave transmit enable – eUSCI_A2 SPI mode | |
| UCA3CLK | 30 | 24 | I/O | Clock signal input – eUSCI_A3 SPI slave mode Clock signal output – eUSCI_A3 SPI master mode |
|
| UCA3SIMO | 27, 36 | 21, 30 | I/O | Slave in/master out – eUSCI_A3 SPI mode | |
| UCA3SOMI | 28, 35 | 22, 29 | I/O | Slave out/master in – eUSCI_A3 SPI mode | |
| UCA3STE | 29 | 23 | I/O | Slave transmit enable – eUSCI_A3 SPI mode | |
| UCB0CLK | 32 | 26 | I/O | Clock signal input – eUSCI_B0 SPI slave mode Clock signal output – eUSCI_B0 SPI master mode |
|
| UCB0SIMO | 29 | 23 | I/O | Slave in/master out – eUSCI_B0 SPI mode | |
| UCB0SOMI | 30 | 24 | I/O | Slave out/master in – eUSCI_B0 SPI mode | |
| UCB0STE | 31 | 25 | I/O | Slave transmit enable – eUSCI_B0 SPI mode | |
| UCB1CLK | 47 | 38 | I/O | Clock signal input – eUSCI_B1 SPI slave mode Clock signal output – eUSCI_B1 SPI master mode |
|
| UCB1SIMO | 48, 75 | 39 | I/O | Slave in/master out – eUSCI_B1 SPI mode | |
| UCB1SOMI | 49, 76 | 40 | I/O | Slave out/master in – eUSCI_B1 SPI mode | |
| UCB1STE | 50 | 41 | I/O | Slave transmit enable – eUSCI_B1 SPI mode | |
| System | NMI | 16 | 12 | I | Nonmaskable interrupt input |
| RST | 16 | 12 | I/O | Reset input active low | |
| Timer_A0 | TA0.0 | 3 | – | I/O | TA0 CCR0 capture: CCI0A input, compare: Out0 |
| TA0.0 | 47 | 38 | I/O | TA0 CCR0 capture: CCI0B input, compare: Out0 | |
| TA0.1 | 62 | – | I/O | TA0 CCR1 capture: CCI1A input, compare: Out1 | |
| TA0.2 | 50 | 41 | I/O | TA0 CCR2 capture: CCI2A input, compare: Out2 | |
| TA0.2 | 23 | – | O | TA0 compare: Out2 enabled by COUT | |
| TA0CLK | 12, 39, 51 | 42 | I | TA0 input clock | |
| Timer_A1 | TA1.0 | 4 | 3 | I/O | TA1 CCR0 capture: CCI0A input, compare: Out0 |
| TA1.0 | 55 | 46 | I/O | TA1 CCR0 capture: CCI0B input, compare: Out0 | |
| TA1.0 | 25 | 19 | O | TA1 CCR0 compare: Out0 | |
| TA1.1 | 63 | – | I/O | TA1 CCR1 capture: CCI1A input, compare: Out1 | |
| TA1.1 | 26 | 20 | O | TA1 CCR1 compare: Out1 | |
| TA1.2 | 13 | – | I/O | TA1 CCR2 capture: CCI2A input, compare: Out2 | |
| TA1.2 | 55 | 46 | O | TA1 CCR2 compare: Out2 | |
| TA1.2C | 13 | – | O | TA1 CCR2 compare: Out2 enabled by COUT | |
| TA1CLK | 12, 33, 39 | 27 | I | TA1 input clock | |
| Timer_A4 | TA4.0 | 5 | 4 | I/O | TA4 CCR0 capture: CCI0A input, compare: Out0 |
| TA4.0 | 23 | – | I/O | TA4 CCR0 capture: CCI0B input, compare: Out0 | |
| TA4.0 | 47 | 38 | O | TA4 CCR0 compare: Out0 | |
| TA4.1 | 14 | – | I/O | TA4CCR1 capture: CCI1B input, compare: Out1 | |
| TA4.1 | 48 | 39 | I/O | TA4 CCR1 capture: CCI1A input, compare: Out1 | |
| TA4.1 | 34 | 28 | O | TA4 CCR1 compare: Out1 | |
| TA4.1C | 14 | – | O | TA4 CCR1 compare: Out1 enabled by COUT | |
| TA4CLK | 18, 40 | 14 | I | TA4 input clock | |
| Timer_B0 | TB0.0 | 43 | 34 | I/O | TB0 CCR0 capture: CCI0B input, compare: Out0 |
| TB0.0 | 24 | – | I/O | TB0 CCR0 capture: CCI0A input, compare: Out0 | |
| TB0.1 | 33 | 27 | I/O | TB0 CCR1 capture: CCI1A input, compare: Out1 | |
| TB0.1 | 44 | 35 | O | TB0 CCR1 compare: Out1 | |
| TB0.2 | 76 | – | I/O | TB0 CCR2 capture: CCI2A input, compare: Out2 | |
| TB0.2 | 45 | 36 | O | TB0 CCR2 compare: Out2 | |
| TB0.3 | 46 | 37 | I/O | TB0 CCR3 capture: CCI3A input, compare: Out3 | |
| TB0.3 | 64 | 50 | I/O | TB0 CCR3 capture: CCI3B input, compare: Out3 | |
| TB0.4 | 31 | 25 | I/O | TB0 CCR4 capture: CCI4A input, compare: Out4 | |
| TB0.4 | 35 | 29 | I/O | TB0 CCR4 capture: CCI4B input, compare: Out4 | |
| TB0.5 | 32 | 26 | I/O | TB0 CCR5 capture: CCI5A input, compare: Out5 | |
| TB0.5 | 36 | 30 | I/O | TB0CCR5 capture: CCI5B input, compare: Out5 | |
| TB0.6 | 75 | – | I/O | TB0 CCR6 capture: CCI6B input, compare: Out6 | |
| TB0.6 | 20 | 16 | I/O | TB0 CCR6 capture: CCI6A input, compare: Out6 | |
| TB0CLK | 12, 40,57 | 47 | I | TB0 clock input | |
| TB0OUTH | 19, 49, 76 | 15 | I | Switch all PWM outputs high impedance input – TB0 | |
| UART | UCA0RXD | 14, 38 | 32 | I | Receive data – eUSCI_A0 UART mode |
| UCA0TXD | 13, 37 | 31 | O | Transmit data – eUSCI_A0 UART mode | |
| UCA1RXD | 26 | 20 | I | Receive data – eUSCI_A1 UART mode | |
| UCA1TXD | 25 | 19 | O | Transmit data – eUSCI_A1 UART mode | |
| UCA2RXD | 20, 44 | 16, 35 | I | Receive data – eUSCI_A2 UART mode | |
| UCA2TXD | 19, 43 | 15, 34 | O | Transmit data – eUSCI_A2 UART mode | |
| UCA3RXD | 28, 35 | 22, 29 | I | Receive data – eUSCI_A3 UART mode | |
| UCA3TXD | 27, 36 | 21, 30 | O | Transmit data – eUSCI_A3 UART mode | |
| USS_A | USSTRG | 30 | 24 | I | USS UUPS trigger |
| USSXTIN | 78 | 62 | I | Input for an oscillator USSXT | |
| USSXTOUT | 79 | 63 | O | Output for an oscillator USSXT | |
| USSXT_BOUT | 75, 10 | 9 | O | Buffered output clock of USSXT | |
| CH0_IN | 74 | 60 | I | USS Channel 0 RX | |
| CH0_OUT | 73 | 59 | I/O | USS Channel 0 TX | |
| CH1_IN | 67 | 53 | I | USS Channel 1 RX | |
| CH1_OUT | 68 | 54 | I/O | USS Channel 1 TX | |
| XPB0 | 55 | 46 | O | External bias output | |
| XPB1 | 64 | 50 | O | External bias output | |
(1) N/A = not available
(2) I = input, O = output, P = power
7.4 Pin Multiplexing
Pin multiplexing for these devices is controlled by both register settings and operating modes (for example, if the device is in test mode). For details of the settings for each pin and diagrams of the multiplexed ports, see Section 9.14.
7.5 Buffer Type
Table 7-3 describes the buffer types that are referenced in Table 7-1.
Table 7-3 Buffer Type
| BUFFER TYPE (STANDARD) | NOMINAL VOLTAGE | HYSTERESIS | PULLUP (PU) OR PULLDOWN (PD) | NOMINAL PU OR PD STRENGTH (µA) | OUTPUT DRIVE STRENGTH (mA) | OTHER CHARACTERISTICS |
|---|---|---|---|---|---|---|
| Analog(2) | 3.0 V | N | N/A | N/A | N/A | See analog modules in Specifications for details |
| LVCMOS | 3.0 V | Y(1) | Programmable | See General-Purpose I/Os | See Typical Characteristics – Outputs | |
| Power (DVCC)(3) | 3.0 V | N | N/A | N/A | N/A | SVS enables hysteresis on DVCC |
| Power (AVCC)(3) | 3.0 V | N | N/A | N/A | N/A | |
| Power (PVCC)(3) | 3.0 V | N | N/A | N/A | N/A | |
| Power (DVSS and AVSS)(3) | 0 V | N | N/A | N/A | N/A |
(1) Only for input pins
(2) This is a switch, not a buffer.
(3) This is supply input, not a buffer.
7.6 Connection of Unused Pins
Table 7-4 lists the correct termination of all unused pins.
Table 7-4 Connection of Unused Pins
| PIN(1) | POTENTIAL | COMMENT |
|---|---|---|
| AVCC | DVCC | |
| PVCC | DVCC | |
| AVSS | DVSS | |
| PVSS | DVSS | |
| USS_CHx_IN, USS_CHx_OUT | DVSS | |
| USSXTIN | DVSS | |
| USSXTOUT | DVSS | |
| Px.0 to Px.7 | Open | Switched to port function, output direction (PxDIR.n = 1) |
| RST/NMI | DVCC or VCC | 47-kΩ pullup or internal pullup selected with 10-nF (2.2 nF(2)) pulldown |
| PJ.0/TDO PJ.1/TDI PJ.2/TMS PJ.3/TCK |
Open | The JTAG pins are shared with general-purpose I/O function (PJ.x). If not being used, these should be switched to port function, output direction. When used as JTAG pins, these pins should remain open. |
| TEST | Open | This pin always has an internal pulldown enabled. |
(1) For any unused pin with a secondary function that is shared with general-purpose I/O, follow the guidelines for the Px.0 to Px.7 pins.
(2) The pulldown capacitor should not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers.
