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  • 适用于汽车 48V 系统、采用 LGA 封装且具有单输入的 UCC20225-Q1、UCC20225A-Q1 隔离式双通道栅极驱动器

    • ZHCSJ23C November   2018  – September 2019 UCC20225-Q1 , UCC20225A-Q1

      PRODUCTION DATA.  

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  • 适用于汽车 48V 系统、采用 LGA 封装且具有单输入的 UCC20225-Q1、UCC20225A-Q1 隔离式双通道栅极驱动器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      功能方框图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Thermal Derating Curves
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay and Pulse Width Distortion
    2. 7.2 Rising and Falling Time
    3. 7.3 PWM Input and Disable Response Time
    4. 7.4 Programable Dead Time
    5. 7.5 Power-up UVLO Delay to OUTPUT
    6. 7.6 CMTI Testing
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in UCC20225-Q1 family
    4. 8.4 Device Functional Modes
      1. 8.4.1 Disable Pin
      2. 8.4.2 Programmable Dead Time (DT) Pin
        1. 8.4.2.1 Tying the DT Pin to VCC
        2. 8.4.2.2 DT Pin Left Open or Connected to a Programming Resistor between DT and GND Pins
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing PWM Input Filter
        2. 9.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 9.2.2.3 Gate Driver Output Resistor
        4. 9.2.2.4 Estimate Gate Driver Power Loss
        5. 9.2.2.5 Estimating Junction Temperature
        6. 9.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.6.1 Selecting a VCCI Capacitor
          2. 9.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 9.2.2.6.3 Select a VDDB Capacitor
        7. 9.2.2.7 Dead Time Setting Guidelines
        8. 9.2.2.8 Application Circuits with Output Stage Negative Bias
      3. 9.2.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 相关链接
    2. 12.2 文档支持
      1. 12.2.1 相关文档
    3. 12.3 认证
    4. 12.4 接收文档更新通知
    5. 12.5 社区资源
    6. 12.6 商标
    7. 12.7 静电放电警告
    8. 12.8 Glossary
  13. 13机械、封装和可订购信息
  14. 重要声明
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DATA SHEET

适用于汽车 48V 系统、采用 LGA 封装且具有单输入的 UCC20225-Q1、UCC20225A-Q1 隔离式双通道栅极驱动器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 具有符合 AEC-Q100 标准的下列特性：
    • 器件温度 1 级
    • 器件 HBM ESD 分类等级 H2
    • 器件 CDM ESD 分类等级 C6
  • 单 PWM 输入，双输出
  • 可通过电阻器编程的死区时间
  • 4A 峰值拉电流、6A 峰值灌电流输出
  • CMTI 大于 100V/ns
  • 开关参数：
    • 19ns 典型传播延迟
    • 5ns 最大延迟匹配
    • 6ns 最大脉宽失真
  • 3V 至 18V 输入 VCCI 范围
  • VDD 高达 25V，带 5V 和 8V UVLO 选项
  • 抑制短于 5ns 的输入瞬变
  • TTL 和 CMOS 兼容输入
  • 节省空间的 5mm x 5mm LGA-13 封装
  • 安全相关认证：
    • 符合 VDE V 0884-11:2017 标准的 3535VPK隔离
    • 符合 UL 1577 标准且持续时长为 1 分钟的 2500VRMS 隔离
    • 符合 GB4943.1-2011 的 CQC 认证

2 应用

  • 汽车外部音频放大器
  • 汽车 48V 系统

3 说明

是UCC20225-Q1 系列是一款单输入、双输出隔离式栅极驱动器，具有 4A 峰值拉电流和 6A 峰值灌电流，并且采用 5mm x 5mm LGA-13 封装。该器件旨在以一流的传播延迟和脉宽失真度驱动功率晶体管，频率最高可达 5MHz。

输入侧通过一个 2.5kVRMS 隔离栅与两个输出驱动器隔离，共模瞬态抗扰度 (CMTI) 的最小值为 100V/ns。两个输出侧驱动器之间的内部功能隔离支持高达 700VDC 的工作电压。

UCC20225-Q1 系列通过 DT 引脚上的电阻器支持可编程死区时间。DIS 引脚在设为高电平时可同时关断两个输出，在接地时允许器件正常运行。

该器件接受的 VDD 电源电压高达 25V。凭借 3V 至 18V 的宽 VCCI 范围，该驱动器非常适合连接模拟和数字控制器。所有电源电压引脚都具有欠压锁定 (UVLO) 保护功能。

凭借上述所有高级 功能，UCC20225-Q1 系列可在各种汽车 应用中实现高功率密度、高效率和稳健性。

器件信息(1)

器件型号 封装 UVLO
UCC20225A-Q1 LGA (13) 5 × 5 mm 5V
UCC20225-Q1 LGA (13) 5 × 5 mm 8V
  1. 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品附录。

Device Images

功能方框图

UCC20225-Q1 UCC20225A-Q1 fig35-slucv8-Typ-App.png

4 修订历史记录

Changes from B Revision (June 2019) to C Revision

  • Changed 将 UCC20225A-Q1 的销售状态从“预告信息”更改为“初始发行版”Go

Changes from A Revision (April 2019) to B Revision

  • Added 向数据表添加了 UCC20225A-Q1 器件Go

Changes from * Revision (November 2018) to A Revision

  • Changed 将销售状态从“预告信息”更改为“初始发行版”。Go

5 Pin Configuration and Functions

NPL Package
13-Pin LGA
Top View
UCC20225-Q1 UCC20225A-Q1 pin_sluscv8.gif

Pin Functions

PIN I/O(1) DESCRIPTION
NAME NO.
DISABLE 5 I Disables both driver outputs if asserted high, enables if set low or left open. This pin is pulled low internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise immunity. Bypass using a ≈1nF low ESR/ESL capacitor close to DIS pin when connecting to a micro controller with distance.
DT 6 I Programmable dead time function.

Tying DT to VCCI disables the DT function with dead time ≈ 0ns. Placing a resistor (RDT) between DT and GND adjusts dead time according to: DT (in ns) = 10 x RDT (in kΩ). It is recommended to parallel a ceramic capacitor, 2.2nF or above, close to DT pin to achieve better noise immunity when using RDT.
GND 1 G Primary-side ground reference. All signals in the primary side are referenced to this ground.
NC 3 – No internal connection.
OUTA 12 O Output of driver A. Connect to the gate of the A channel FET or IGBT. Output A is in phase with PWM input with a propagation delay
OUTB 9 O Output of driver B. Connect to the gate of the B channel FET or IGBT. Output B is always complementary to output A with a programmed dead time.
PWM 2 I PWM input has a TTL/CMOS compatible input threshold. This pin is pulled low internally if left open.
VCCI 4 P Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor located as close to the device as possible.
VCCI 7 P This pin is internally shorted to pin 4. Preference should be given to bypassing pin-4 to pin-1 instead of pin-7 to pin-1.
VDDA 13 P Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL capacitor located as close to the device as possible.
VDDB 10 P Secondary-side power for driver B. Locally decoupled to VSSB using a low ESR/ESL capacitor located as close to the device as possible.
VSSA 11 G Ground for secondary-side driver A. Ground reference for secondary side A channel.
VSSB 8 G Ground for secondary-side driver B. Ground reference for secondary side B channel.
(1) P =Power, G= Ground, I= Input, O= Output

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Input bias pin supply voltage VCCI to GND –0.3 20 V
Driver bias supply VDDA-VSSA, VDDB-VSSB –0.3 30 V
Output signal voltage OUTA to VSSA, OUTB to VSSB –0.3 VVDDA+0.3, VVDDB+0.3 V
OUTA to VSSA, OUTB to VSSB, Transient for 200 ns –2 VVDDA+0.3, VVDDB+0.3 V
Input signal voltage PWM, DIS, DT to GND –0.3 VVCCI+0.3 V
PWM Transient for 50ns –5 VVCCI+0.3 V
Channel to channel voltage VSSA-VSSB, VSSB-VSSA 700 V
Junction temperature, TJ(2) –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) To maintain the recommended operating conditions for TJ, see the Thermal Information.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) ±4000 V
Charged-device model (CDM), per AEC Q100-011 ±1500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCCI VCCI Input supply voltage 3 18 V
VDDA, VDDB Driver output bias supply UCC20225A-Q1 6.5 25 V
UCC20225-Q1 9.2 25
TA Ambient Temperature –40 125 °C
TJ Junction Temperature –40 130 °C

6.4 Thermal Information

THERMAL METRIC(1) UCC20225A-Q1, UCC20225-Q1 UNIT
LGA (13)(2)
RθJA Junction-to-ambient thermal resistance 98.0 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 48.8
RθJB Junction-to-board thermal resistance 78.9
ψJT Junction-to-top characterization parameter 26.2
ψJB Junction-to-board characterization parameter 76.8
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.
(2) Standard JESD51-9 Area Array SMT Test Board (2s2p) in still air, with 12-mil dia. 1-oz copper vias connecting VSSA and VSSB to the plane immediately below (three vias for VSSA, three vias for VSSB).

6.5 Power Ratings

VALUE UNIT
PD Power dissipation by UCC20225A-Q1, UCC20225-Q1 VCCI = 18 V, VDDA/B = 12 V, PWM = 3.3 V, 2.7 MHz 50% duty cycle square wave 1-nF load 0.95 W
PDI Power dissipation by primary side of UCC20225A-Q1, UCC20225-Q1 0.05
PDA, PDB Power dissipation by each driver side of UCC20225A-Q1, UCC20225-Q1 0.45

6.6 Insulation Specifications

PARAMETER TEST CONDITIONS VALUE UNIT
CLR External clearance(1)(2) Shortest pin-to-pin distance through air 3.5 mm
CPG External creepage(1) Shortest pin-to-pin distance across the package surface 3.5 mm
DTI Distance through the insulation Minimum internal gap (internal clearance) >21 µm
CTI Comparative tracking index DIN EN 60112 (VDE 0303-11); IEC 60112 > 600 V
Material group I
Overvoltage category per IEC 60664-1 Rated mains voltage ≤ 150 VRMS I-III
Rated mains voltage ≤ 300 VRMS I-II
DIN V VDE V 0884-11 (VDE V 0884-11): 2017-01(3)
VIORM Maximum repetitive peak isolation voltage AC voltage (bipolar) 792 VPK
VIOWM Maximum working isolation voltage AC voltage (sine wave); time dependent dielectric breakdown (TDDB) test; (See Figure 1) 560 VRMS
DC Voltage 792 VDC
VIOTM Maximum transient isolation voltage VTEST = VIOTM, t = 60 s (qualification); VTEST = 1.2 × VIOTM, t = 1 s (100% production) 3535 VPK
VIOSM Maximum surge isolation voltage(4) Test method per IEC 62368-1, 1.2/50 μs waveform, VTEST = 1.3 × VIOSM (qualification) 3500 VPK
qpd Apparent charge(5) Method a, After Input/Output safety test subgroup 2/3,
Vini = VIOTM, tini = 60s;
Vpd(m) = 1.2 × VIORM, tm = 10s 		<5 pC
Method a, After environmental tests subgroup 1,
Vini = VIOTM, tini = 60s;
Vpd(m) = 1.2 × VIORM, tm = 10s		 <5
Method b1; At routine test (100% production) and preconditioning (type test)
Vini = 1.2 × VIOTM; tini = 1 s;
Vpd(m) = 1.5 × VIORM , tm = 1s 		<5
CIO Barrier capacitance, input to output(6) VIO = 0.4 sin (2πft), f =1 MHz 1.2 pF
RIO Isolation resistance, input to output VIO = 500 V at TA = 25°C > 1012 Ω
VIO = 500 V at 100°C ≤ TA ≤ 125°C > 1011
VIO = 500 V at TS =150°C > 109
Pollution degree 2
Climatic category 40/125/21
UL 1577
VISO Withstand isolation voltage VTEST = VISO = 3000 VRMS, t = 60 sec. (qualification),
VTEST = 1.2 × VISO = 3000VRMS, t = 1 sec (100% production)		 2500 VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves, ribs, or both on a printed circuit board are used to help increase these specifications.
(2) Package dimension tolerance ± 0.05mm.
(3) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(4) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(5) Apparent charge is electrical discharge caused by a partial discharge (pd).
(6) All pins on each side of the barrier tied together creating a two-pin device.

6.7 Safety-Related Certifications

VDE UL CQC
Certified according to DIN V VDE V 0884-11:2017-01 Recognized under UL 1577 Component Recognition Program Certified according to GB 4943.1-2011
Basic Insulation Maximum Transient Overvoltage, 3535 VPK;
Maximum Repetitive Peak Voltage, 792 VPK;
Maximum Surge Isolation Voltage, 2719 VPK 		Single protection, 2500 VRMS Basic Insulation,
Altitude ≤ 5000 m,
Tropical Climate 320-VRMS maximum working voltage
Certification Number: 40016131 Certification Number: E181974 Certification Number: CQC18001186974

 
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