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  • MSP430F552x、MSP430F551x 混合信号微控制器

    • ZHCSIR7N March   2009  – September 2018 MSP430F5513 , MSP430F5514 , MSP430F5515 , MSP430F5517 , MSP430F5519 , MSP430F5521 , MSP430F5522 , MSP430F5524 , MSP430F5525 , MSP430F5526 , MSP430F5527 , MSP430F5528 , MSP430F5529

      PRODUCTION DATA.  

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  • MSP430F552x、MSP430F551x 混合信号微控制器
  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用范围
    3. 1.3 说明
    4. 1.4 功能方框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagrams
    2. 4.2 Signal Descriptions
      1. Table 4-1 Terminal Functions
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Low-Power Mode Supply Currents (Into VCC) Excluding External Current
    6. 5.6  Thermal Resistance Characteristics
    7. 5.7  Schmitt-Trigger Inputs – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7, P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
    8. 5.8  Inputs – Ports P1 and P2 (P1.0 to P1.7, P2.0 to P2.7)
    9. 5.9  Leakage Current – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7) (P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)
    10. 5.10 Outputs – General-Purpose I/O (Full Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7, P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
    11. 5.11 Outputs – General-Purpose I/O (Reduced Drive Strength) (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7, P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
    12. 5.12 Output Frequency – General-Purpose I/O (P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7, P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)
    13. 5.13 Typical Characteristics – Outputs, Reduced Drive Strength (PxDS.y = 0)
    14. 5.14 Typical Characteristics – Outputs, Full Drive Strength (PxDS.y = 1)
    15. 5.15 Crystal Oscillator, XT1, Low-Frequency Mode
    16. 5.16 Crystal Oscillator, XT2
    17. 5.17 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
    18. 5.18 Internal Reference, Low-Frequency Oscillator (REFO)
    19. 5.19 DCO Frequency
    20. 5.20 PMM, Brownout Reset (BOR)
    21. 5.21 PMM, Core Voltage
    22. 5.22 PMM, SVS High Side
    23. 5.23 PMM, SVM High Side
    24. 5.24 PMM, SVS Low Side
    25. 5.25 PMM, SVM Low Side
    26. 5.26 Wake-up Times From Low-Power Modes and Reset
    27. 5.27 Timer_A
    28. 5.28 Timer_B
    29. 5.29 USCI (UART Mode) Clock Frequency
    30. 5.30 USCI (UART Mode)
    31. 5.31 USCI (SPI Master Mode) Clock Frequency
    32. 5.32 USCI (SPI Master Mode)
    33. 5.33 USCI (SPI Slave Mode)
    34. 5.34 USCI (I2C Mode)
    35. 5.35 12-Bit ADC, Power Supply and Input Range Conditions
    36. 5.36 12-Bit ADC, Timing Parameters
    37. 5.37 12-Bit ADC, Linearity Parameters Using an External Reference Voltage or AVCC as Reference Voltage
    38. 5.38 12-Bit ADC, Linearity Parameters Using the Internal Reference Voltage
    39. 5.39 12-Bit ADC, Temperature Sensor and Built-In VMID
    40. 5.40 REF, External Reference
    41. 5.41 REF, Built-In Reference
    42. 5.42 Comparator_B
    43. 5.43 Ports PU.0 and PU.1
    44. 5.44 USB Output Ports DP and DM
    45. 5.45 USB Input Ports DP and DM
    46. 5.46 USB-PWR (USB Power System)
    47. 5.47 USB-PLL (USB Phase-Locked Loop)
    48. 5.48 Flash Memory
    49. 5.49 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  CPU (Link to User's Guide)
    2. 6.2  Operating Modes
    3. 6.3  Interrupt Vector Addresses
    4. 6.4  Memory Organization
    5. 6.5  Bootloader (BSL)
      1. 6.5.1 USB BSL
      2. 6.5.2 UART BSL
    6. 6.6  JTAG Operation
      1. 6.6.1 JTAG Standard Interface
      2. 6.6.2 Spy-Bi-Wire Interface
    7. 6.7  Flash Memory (Link to User's Guide)
    8. 6.8  RAM (Link to User's Guide)
    9. 6.9  Peripherals
      1. 6.9.1  Digital I/O (Link to User's Guide)
      2. 6.9.2  Port Mapping Controller (Link to User's Guide)
      3. 6.9.3  Oscillator and System Clock (Link to User's Guide)
      4. 6.9.4  Power-Management Module (PMM) (Link to User's Guide)
      5. 6.9.5  Hardware Multiplier (Link to User's Guide)
      6. 6.9.6  Real-Time Clock (RTC_A) (Link to User's Guide)
      7. 6.9.7  Watchdog Timer (WDT_A) (Link to User's Guide)
      8. 6.9.8  System Module (SYS) (Link to User's Guide)
      9. 6.9.9  DMA Controller (Link to User's Guide)
      10. 6.9.10 Universal Serial Communication Interface (USCI) (Links to User's Guide: UART Mode, SPI Mode, I2C Mode)
      11. 6.9.11 TA0 (Link to User's Guide)
      12. 6.9.12 TA1 (Link to User's Guide)
      13. 6.9.13 TA2 (Link to User's Guide)
      14. 6.9.14 TB0 (Link to User's Guide)
      15. 6.9.15 Comparator_B (Link to User's Guide)
      16. 6.9.16 ADC12_A (Link to User's Guide)
      17. 6.9.17 CRC16 (Link to User's Guide)
      18. 6.9.18 Voltage Reference (REF) Module (Link to User's Guide)
      19. 6.9.19 Universal Serial Bus (USB) (Link to User's Guide)
      20. 6.9.20 Embedded Emulation Module (EEM) (Link to User's Guide)
      21. 6.9.21 Peripheral File Map
    10. 6.10 Input/Output Diagrams
      1. 6.10.1  Port P1 (P1.0 to P1.7) Input/Output With Schmitt Trigger
      2. 6.10.2  Port P2 (P2.0 to P2.7) Input/Output With Schmitt Trigger
      3. 6.10.3  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      4. 6.10.4  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      5. 6.10.5  Port P5 (P5.0 and P5.1) Input/Output With Schmitt Trigger
      6. 6.10.6  Port P5 (P5.2 and P5.3) Input/Output With Schmitt Trigger
      7. 6.10.7  Port P5 (P5.4 and P5.5) Input/Output With Schmitt Trigger
      8. 6.10.8  Port P5 (P5.6 and P5.7) Input/Output With Schmitt Trigger
      9. 6.10.9  Port P6 (P6.0 to P6.7) Input/Output With Schmitt Trigger
      10. 6.10.10 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      11. 6.10.11 Port P7 (P7.4 to P7.7) Input/Output With Schmitt Trigger
      12. 6.10.12 Port P8 (P8.0 to P8.2) Input/Output With Schmitt Trigger
      13. 6.10.13 Port PU (PU.0/DP, PU.1/DM, PUR) USB Ports
      14. 6.10.14 Port PJ (PJ.0) JTAG Pin TDO, Input/Output With Schmitt Trigger or Output
      15. 6.10.15 Port PJ (PJ.1 to PJ.3) JTAG Pins TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger or Output
    11. 6.11 Device Descriptors (TLV)
  7. 7器件和文档支持
    1. 7.1  入门和后续步骤
    2. 7.2  Device Nomenclature
    3. 7.3  工具与软件
    4. 7.4  文档支持
    5. 7.5  相关链接
    6. 7.6  社区资源
    7. 7.7  商标
    8. 7.8  静电放电警告
    9. 7.9  Export Control Notice
    10. 7.10 Glossary
  8. 8机械、封装和可订购信息
  9. 重要声明
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DATA SHEET

MSP430F552x、MSP430F551x 混合信号微控制器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 器件概述

1.1 特性

  • 低电源电压范围：
    从 3.6V 低至 1.8V
  • 超低功耗
    • 激活模式 (AM)：
      • 所有系统时钟激活：
        • 8MHz 时为 290µA/MHz、3.0V、闪存程序执行（典型值）
        • 8MHz 时为 150µA/MHz、3.0V、RAM 程序执行（典型值）
    • 待机模式 (LPM3)：
      • 含晶体的实时时钟 (RTC)、看门狗、电源监控器可用、完全 RAM 保持、快速唤醒：
        • 2.2V 时为 1.9µA，3.0V 时为 2.1µA（典型值）
      • 低功耗振荡器 (VLO)、通用计数器、看门狗、电源监控器可用、完全 RAM 保持、快速唤醒：
        • 3.0V 时为 1.4µA（典型值）
    • 关闭模式 (LPM4)：
      • 完全 RAM 保持、电源监视器可用、快速唤醒：
        • 3.0V 时为 1.1µA（典型值）
    • 关断模式 (LPM4.5)：
      • 3.0V 时为 0.18µA（典型值）
  • 在 3.5µs（典型值）内从待机模式唤醒
  • 16 位精简指令集计算机 (RISC) 架构，扩展内存，高达 25MHz 的系统时钟
  • 灵活的电源管理系统
    • 内置可编程的低压降稳压器 (LDO)
    • 电源电压监控、监视和临时限电
  • 统一时钟系统
    • 针对频率稳定的锁相环 (FLL) 控制环路
    • 低功耗低频内部时钟源 (VLO)
    • 低频修整内部基准源 (REFO)
    • 32kHz 手表晶振 (XT1)
    • 高达 32MHz 的高频晶振 (XT2)
  • 具有 5 个捕捉/比较寄存器的 16 位定时器 TA0，Timer_A
  • 具有 3 个捕捉/比较寄存器的 16 位定时器 TA1，Timer_A
  • 具有 3 个捕捉/比较寄存器的 16 位定时器 TA2，Timer_A
  • 具有 7 个捕捉/比较影子寄存器的 16 位定时器 TB0，Timer_B
  • 2 个通用串行通信接口
    • USCI_A0 和 USCI_A1 均支持：
      • 增强型通用异步收发器 (UART) 支持自动波特率检测
      • IrDA 编码和解码
      • 同步串行外设接口 (SPI)
    • USCI_B0 和 USCI_B1 每个都支持：
      • I2C
      • 同步串行外设接口 (SPI)
  • 全速通用串行总线 (USB)
    • 集成的 USB - 物理层 (PHY)
    • 集成 3.3V 和 1.8V USB 电源系统
    • 集成 USB- 锁相环 (PLL)
    • 8 输入和 8 输出端点
  • 具有内部基准、采样保持和自动扫描功能的 12 位模数转换器 (ADC)（仅限 MSP430F552x）
  • 比较器
  • 硬件乘法器支持 32 位运算
  • 串行板上编程，无需外部编程电压
  • 3 通道内部 DMA
  • 具有 RTC 特性的基本计时器
  • 器件比较 总结了可用的系列产品成员

1.2 应用范围

  • 模拟和数字传感器系统
  • 数据记录器
  • 连接到 USB 主机

1.3 说明

TI 的 MSP430™系列的超低功耗微控制器包含数个采用外设集的器件，可广泛应用于各种 应用。此架构与多种低功耗模式配合使用，是延长便携式测量应用电池寿命的最优 选择。该微控制器 具有 一个强大的 16 位精简指令集 (RISC) CPU，使用 16 位寄存器以及常数发生器，以便获得最高编码效率。此数控振荡器 (DCO) 可使器件在 3.5µs（典型值）内从低功耗模式唤醒至激活模式。

MSP430F5529、MSP430F5527、MSP430F5525 和 MSP430F5521 微控制器具有支持 USB 2.0 的集成 USB 和 PHY、4 个 16 位计时器、1 个高性能 12 位模数转换器 (ADC)、2 个 USCI、1 个硬件乘法器、DMA、1 个带有警报功能的 RTC 模块和 63 个 I/O 引脚。MSP430F5528、MSP430F5526、MSP430F5524 和 MSP430F5522 微控制器包含同样的外设，但具有 47 个 I/O 引脚。

MSP430F5519、MSP430F5517 和 MSP430F5515 微控制器具有支持 USB 2.0 的集成 USB 和 PHY、4 个 16 位计时器、2 个 USCI、1 个硬件乘法器、DMA、1 个带有警报功能的 RTC 模块和 63 个 I/O 引脚。MSP430F5514 和 MSP430FF5513 微控制器包含同样的外设，但具有 47 个 I/O 引脚。

典型 应用 包括需要与多种 USB 主机连接的模拟和数字传感器系统、数据记录器和其它应用。

要获得完整的模块说明，请参阅《MSP430F5xx 和 MSP430F6xx 系列用户指南》

器件信息(1)

器件型号 封装 封装尺寸(2)
MSP430F5529IPN LQFP (80) 12mm x 12mm
MSP430F5528IRGC VQFN (64) 9mm x 9mm
MSP430F5528IYFF DSBGA (64) 请参见 Section 8
MSP430F5528IZQE MicroStar Junior™BGA (80) 5mm x 5mm
(1) 要获得所有可用器件的最新部件、封装和订购信息，请参见封装选项附录（Section 8）或浏览 TI 网站 www.ti.com.cn。
(2) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参见机械数据（Section 8）。

1.4 功能方框图

Figure 1-1 展示了采用 PN 封装的 MSP430F5529、MSP430F5527、MSP430F5525 和 MSP430F5521 器件的功能方框图。

MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 slas590-block80pin.gifFigure 1-1 功能方框图 – MSP430F5529IPN、MSP430F5527IPN、MSP430F5525IPN、MSP430F5521IPN

Figure 1-2 展示了采用 RGC 和 ZQE 封装的 MSP430F5528、MSP430F5526、MSP430F5524 和 MSP430F5522 器件的功能方框图，以及采用 YFF 封装的 MSP430F5528、MSP430F5526 和 MSP430F5524 器件的功能方框图。

MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 slas590-block64pin.gifFigure 1-2 功能方框图 –
MSP430F5528IRGC、MSP430F5526IRGC、MSP430F5524IRGC、MSP430F5522IRGC
MSP430F5528IZQE、MSP430F5526IZQE、MSP430F5524IZQE、MSP430F5522IZQE
MSP430F5528IYFF、MSP430F5526IYFF、MSP430F5524IYFF

Figure 1-3 展示了采用 PN 封装的 MSP430F5519、MSP430F5517 和 MSP430F5515 器件的功能方框图。

MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 slas590-block80apin.gifFigure 1-3 功能方框图 – MSP430F5519IPN、MSP430F5517IPN、MSP430F5515IPN

Figure 1-4 展示了采用 RGC 和 ZQE 封装的 MSP430F5514 和 MSP430F5513 器件的功能方框图。

MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 slas590-block64apin.gifFigure 1-4 功能方框图 – MSP430F5514IRGC、MSP430F5513IRGC、MSP430F5514IZQE、MSP430F5513IZQE

2 修订历史记录

Changes from November 3, 2015 to September 20, 2018

  • 更改了器件信息 表中 DSBGA 封装的封装尺寸条目Go
  • Added Section 3.1, Related ProductsGo
  • Removed D and E dimension lines from the YFF pinout (for package dimensions, see the Mechanical Data in Section 8)Go
  • Added typical conditions statements at the beginning of Section 5, SpecificationsGo
  • Changed the MIN value of the V(DVCC_BOR_hys) parameter from 60 mV to 50 mV in Section 5.20, PMM, Brownout Reset (BOR)Go
  • Updated notes (1) and (2) and added note (3) in Section 5.26, Wake-up Times From Low-Power Modes and ResetGo
  • Removed ADC12DIV from the formula for the TYP value in the second row of the tCONVERT parameter in Section 5.36, 12-Bit ADC, Timing Parameters, because ADC12CLK is after divisionGo
  • Added second row for tEN_CMP with Test Conditions of "CBPWRMD = 10" and MAX value of 100 µs in Section 5.42, Comparator_BGo
  • Renamed FCTL4.MGR0 and MGR1 bits in the fMCLK,MGR parameter in Section 5.48, Flash Memory, to be consistent with header filesGo
  • Throughout document, changed all instances of "bootstrap loader" to "bootloader"Go
  • Added YFF pin numbers to Table 6-11, TA0 Signal ConnectionsGo
  • Added YFF pin numbers to Table 6-12, TA1 Signal ConnectionsGo
  • Added YFF pin numbers to Table 6-13, TA2 Signal ConnectionsGo
  • 已将先前的“开发工具支持”部分替换为“Section 7.3、工具与软件”Go
  • 更改了格式并添加内容至Section 7.4文档支持Go

3 Device Comparison

Table 3-1 summarizes the available family members.

Table 3-1 Device Comparison(1)(2)

DEVICE FLASH
(KB)		 SRAM
(KB)(5) 		Timer_A(3) Timer_B(4) USCI ADC12_A
(Ch)		 COMP_B
(Ch)		 I/Os PACKAGE
CHANNEL A:
UART, IrDA, SPI		 CHANNEL B:
SPI, I2C
MSP430F5529 128 8 + 2 5, 3, 3 7 2 2 14 ext, 2 int 12 63 80 PN
MSP430F5528 128 8 + 2 5, 3, 3 7 2 2 10 ext, 2 int 8 47 64 RGC, 64 YFF, 80 ZQE
MSP430F5527 96 6 + 2 5, 3, 3 7 2 2 14 ext, 2 int 12 63 80 PN
MSP430F5526 96 6 + 2 5, 3, 3 7 2 2 10 ext, 2 int 8 47 64 RGC, 64 YFF, 80 ZQE
MSP430F5525 64 4 + 2 5, 3, 3 7 2 2 14 ext, 2 int 12 63 80 PN
MSP430F5524 64 4 + 2 5, 3, 3 7 2 2 10 ext, 2 int 8 47 64 RGC, 64 YFF, 80 ZQE
MSP430F5522 32 8 + 2 5, 3, 3 7 2 2 10 ext, 2 int 8 47 64 RGC, 80 ZQE
MSP430F5521 32 6 + 2 5, 3, 3 7 2 2 14 ext, 2 int 12 63 80 PN
MSP430F5519 128 8 + 2 5, 3, 3 7 2 2 – 12 63 80 PN
MSP430F5517 96 6 + 2 5, 3, 3 7 2 2 – 12 63 80 PN
MSP430F5515 64 4 + 2 5, 3, 3 7 2 2 – 12 63 80 PN
MSP430F5514 64 4 + 2 5, 3, 3 7 2 2 – 8 47 64 RGC, 80 ZQE
MSP430F5513 32 4 + 2 5, 3, 3 7 2 2 – 8 47 64 RGC, 80 ZQE
(1) For the most current part, package, and ordering information for all available devices, see the Package Option Addendum in Section 8, or see the TI website at www.ti.com.
(2) Package drawings, thermal data, and symbolization are available at www.ti.com/packaging.
(3) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.
(4) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having 3 and the second instantiation having 5 capture/compare registers and PWM output generators, respectively.
(5) The additional 2KB of USB SRAM that is listed can be used as general-purpose SRAM when USB is not in use.

3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

    Products for TI Microcontrollers

    TI's low-power and high-performance MCUs, with wired and wireless connectivity options, are optimized for a broad range of applications.

    Products for MSP430 Ultra-Low-Power Microcontrollers

    One platform. One ecosystem. Endless possibilities. Enabling the connected world with innovations in ultra-low-power microcontrollers with advanced peripherals for precise sensing and measurement.

    Companion Products for MSP430F5529

    Review products that are frequently purchased or used with this product.

    Reference Designs for MSP430F5529

    The TI Designs Reference Design Library is a robust reference design library that spans analog, embedded processor, and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include schematic or block diagrams, BOMs, and design files to speed your time to market.

4 Terminal Configuration and Functions

4.1 Pin Diagrams

Figure 4-1 shows the pinout for the MSP430F5529, MSP430F5527, MSP430F5525, and MSP430F5521 devices in the 80-pin PN package.

MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 slas590-pinning80.gifFigure 4-1 80-Pin PN Package – MSP430F5529IPN, MSP430F5527IPN, MSP430F5525IPN, MSP430F5521IPN (Top View)

Figure 4-2 shows the pinout for the MSP430F5528, MSP430F5526, MSP430F5524, and MSP430F5522 devices in the 64-pin RGC package.

MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 slas590-pinning64.gif
A.

NOTE:

TI recommends connecting the exposed thermal pad to VSS.
Figure 4-2 64-Pin RGC Package – MSP430F5528IRGC, MSP430F5526IRGC, MSP430F5524IRGC, MSP430F5522IRGC (Top View)

Figure 4-3 shows the pinout for the MSP430F5519, MSP430F5517, and MSP430F5515 devices in the 80-pin PN package.

MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 slas590-pinning80a.gifFigure 4-3 80-Pin PN Package – MSP430F5519IPN, MSP430F5517IPN, MSP430F5515IPN (Top View)

Figure 4-4 shows the pinout for the MSP430F5514 and MSP430F5513 devices in the 64-pin RGC package.

MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 slas590-pinning64a.gif
A.

NOTE:

TI recommends connecting the exposed thermal pad to VSS.
Figure 4-4 64-Pin RGC Package – MSP430F5514IRGC, MSP430F5513IRGC (Top View)

Figure 4-5 shows the pinout for the MSP430F5528, MSP430F5526, MSP430F5524, MSP430F5522, MSP430F5514, and MSP430F5513 devices in the 80-pin ZQE package.

MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 slas590_zqe80.gifFigure 4-5 80-Pin ZQE Package – MSP430F5528IZQE, MSP430F5526IZQE, MSP430F5524IZQE, MSP430F5522IZQE, MSP430F5514IZQE, MSP430F5513IZQE (Top View)

Figure 4-6 shows the pinout for the MSP430F5528, MSP430F5526, and MSP430F5524 devices in the 64-pin YFF package. For package dimensions, see the Mechanical Data in Section 8.

MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 slas590_yff64.gifFigure 4-6 64-Pin YFF Package – MSP430F5528IYFF, MSP430F5526IYFF, MSP430F5524IYFF

4.2 Signal Descriptions

Table 4-1 describes the signals for all device and package options.

Table 4-1 Terminal Functions

TERMINAL I/O(1) DESCRIPTION
NAME NO.
PN RGC YFF ZQE
P6.4/CB4/A4 1 5 B2 C1 I/O General-purpose digital I/O
Comparator_B input CB4
Analog input A4 for ADC (not available on F551x devices)
P6.5/CB5/A5 2 6 B3 D2 I/O General-purpose digital I/O
Comparator_B input CB5
Analog input A5 for ADC (not available on F551x devices)
P6.6/CB6/A6 3 7 A2 D1 I/O General-purpose digital I/O
Comparator_B input CB6
Analog input A6 for ADC (not available on F551x devices)
P6.7/CB7/A7 4 8 C5 D3 I/O General-purpose digital I/O
Comparator_B input CB7
Analog input A7 for ADC (not available on F551x devices)
P7.0/CB8/A12 5 N/A N/A N/A I/O General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
Comparator_B input CB8 (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
Analog input A12 for ADC (not available on F551x devices)
P7.1/CB9/A13 6 N/A N/A N/A I/O General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
Comparator_B input CB9 (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
Analog input A13 for ADC (not available on F551x devices)
P7.2/CB10/A14 7 N/A N/A N/A I/O General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
Comparator_B input CB10 (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
Analog input A14 for ADC (not available on F551x devices)
P7.3/CB11/A15 8 N/A N/A N/A I/O General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
Comparator_B input CB11 (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
Analog input A15 for ADC (not available on F551x devices)
P5.0/A8/VREF+/VeREF+ 9 9 B4 E1 I/O General-purpose digital I/O
Output of reference voltage to the ADC (not available on F551x devices)
Input for an external reference voltage to the ADC (not available on F551x devices)
Analog input A8 for ADC (not available on F551x devices)
P5.1/A9/VREF-/VeREF- 10 10 B5 E2 I/O General-purpose digital I/O
Negative terminal for the ADC reference voltage for both sources, the internal reference voltage, or an external applied reference voltage (not available on F551x devices)
Analog input A9 for ADC (not available on F551x devices)
AVCC1 11 11 A3 F2 Analog power supply
P5.4/XIN 12 12 A5 F1 I/O General-purpose digital I/O
Input terminal for crystal oscillator XT1
P5.5/XOUT 13 13 A6 G1 I/O General-purpose digital I/O
Output terminal of crystal oscillator XT1
AVSS1 14 14 A4 G2 Analog ground supply
P8.0 15 N/A N/A N/A I/O General-purpose digital I/O
P8.1 16 N/A N/A N/A I/O General-purpose digital I/O
P8.2 17 N/A N/A N/A I/O General-purpose digital I/O
DVCC1 18 15 A7 H1 Digital power supply
DVSS1 19 16 A8 J1 Digital ground supply
VCORE(3) 20 17 B8 J2 Regulated core power supply output (internal use only, no external current loading)
P1.0/TA0CLK/ACLK 21 18 B7 H2 I/O General-purpose digital I/O with port interrupt
TA0 clock signal TA0CLK input
ACLK output (divided by 1, 2, 4, 8, 16, or 32)
P1.1/TA0.0 22 19 B6 H3 I/O General-purpose digital I/O with port interrupt
TA0 CCR0 capture: CCI0A input, compare: Out0 output
BSL transmit output
P1.2/TA0.1 23 20 C6 J3 I/O General-purpose digital I/O with port interrupt
TA0 CCR1 capture: CCI1A input, compare: Out1 output
BSL receive input
P1.3/TA0.2 24 21 C8 G4 I/O General-purpose digital I/O with port interrupt
TA0 CCR2 capture: CCI2A input, compare: Out2 output
P1.4/TA0.3 25 22 C7 H4 I/O General-purpose digital I/O with port interrupt
TA0 CCR3 capture: CCI3A input compare: Out3 output
P1.5/TA0.4 26 23 D6 J4 I/O General-purpose digital I/O with port interrupt
TA0 CCR4 capture: CCI4A input, compare: Out4 output
P1.6/TA1CLK/CBOUT 27 24 D7 G5 I/O General-purpose digital I/O with port interrupt
TA1 clock signal TA1CLK input
Comparator_B output
P1.7/TA1.0 28 25 D8 H5 I/O General-purpose digital I/O with port interrupt
TA1 CCR0 capture: CCI0A input, compare: Out0 output
P2.0/TA1.1 29 26 E5 J5 I/O General-purpose digital I/O with port interrupt
TA1 CCR1 capture: CCI1A input, compare: Out1 output
P2.1/TA1.2 30 27 E8 G6 I/O General-purpose digital I/O with port interrupt
TA1 CCR2 capture: CCI2A input, compare: Out2 output
P2.2/TA2CLK/SMCLK 31 28 E7 J6 I/O General-purpose digital I/O with port interrupt
TA2 clock signal TA2CLK input
SMCLK output
P2.3/TA2.0 32 29 E6 H6 I/O General-purpose digital I/O with port interrupt
TA2 CCR0 capture: CCI0A input, compare: Out0 output
P2.4/TA2.1 33 30 F8 J7 I/O General-purpose digital I/O with port interrupt
TA2 CCR1 capture: CCI1A input, compare: Out1 output
P2.5/TA2.2 34 31 F7 J8 I/O General-purpose digital I/O with port interrupt
TA2 CCR2 capture: CCI2A input, compare: Out2 output
P2.6/RTCCLK/DMAE0 35 32 F6 J9 I/O General-purpose digital I/O with port interrupt
RTC clock output for calibration
DMA external trigger input
P2.7/UCB0STE/UCA0CLK 36 33 H8 H7 I/O General-purpose digital I/O with port interrupt
Slave transmit enable – USCI_B0 SPI mode
Clock signal input – USCI_A0 SPI slave mode
Clock signal output – USCI_A0 SPI master mode
P3.0/UCB0SIMO/ UCB0SDA 37 34 G8 H8 I/O General-purpose digital I/O
Slave in, master out – USCI_B0 SPI mode
I2C data – USCI_B0 I2C mode
P3.1/UCB0SOMI/UCB0SCL 38 35 H7 H9 I/O General-purpose digital I/O
Slave out, master in – USCI_B0 SPI mode
I2C clock – USCI_B0 I2C mode
P3.2/UCB0CLK/UCA0STE 39 36 G7 G8 I/O General-purpose digital I/O
Clock signal input – USCI_B0 SPI slave mode
Clock signal output – USCI_B0 SPI master mode
Slave transmit enable – USCI_A0 SPI mode
P3.3/UCA0TXD/ UCA0SIMO 40 37 G6 G9 I/O General-purpose digital I/O
Transmit data – USCI_A0 UART mode
Slave in, master out – USCI_A0 SPI mode
P3.4/UCA0RXD/ UCA0SOMI 41 38 G5 G7 I/O General-purpose digital I/O
Receive data – USCI_A0 UART mode
Slave out, master in – USCI_A0 SPI mode
P3.5/TB0.5 42 N/A N/A N/A I/O General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
TB0 CCR5 capture: CCI5A input, compare: Out5 output
P3.6/TB0.6 43 N/A N/A N/A I/O General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
TB0 CCR6 capture: CCI6A input, compare: Out6 output
P3.7/TB0OUTH/SVMOUT 44 N/A N/A N/A I/O General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
Switch all PWM outputs high impedance input – TB0 (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
SVM output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
P4.0/PM_UCB1STE/ PM_UCA1CLK 45 41 F5 E8 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Slave transmit enable – USCI_B1 SPI mode
Default mapping: Clock signal input – USCI_A1 SPI slave mode
Default mapping: Clock signal output – USCI_A1 SPI master mode
P4.1/PM_UCB1SIMO/ PM_UCB1SDA 46 42 H4 E7 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Slave in, master out – USCI_B1 SPI mode
Default mapping: I2C data – USCI_B1 I2C mode
P4.2/PM_UCB1SOMI/ PM_UCB1SCL 47 43 G4 D9 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Slave out, master in – USCI_B1 SPI mode
Default mapping: I2C clock – USCI_B1 I2C mode
P4.3/PM_UCB1CLK/ PM_UCA1STE 48 44 F4 D8 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Clock signal input – USCI_B1 SPI slave mode
Default mapping: Clock signal output – USCI_B1 SPI master mode
Default mapping: Slave transmit enable – USCI_A1 SPI mode
DVSS2 49 39 H6 F9 Digital ground supply
DVCC2 50 40 H5 E9 Digital power supply
P4.4/PM_UCA1TXD/ PM_UCA1SIMO 51 45 H3 D7 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Transmit data – USCI_A1 UART mode
Default mapping: Slave in, master out – USCI_A1 SPI mode
P4.5/PM_UCA1RXD/ PM_UCA1SOMI 52 46 G3 C9 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: Receive data – USCI_A1 UART mode
Default mapping: Slave out, master in – USCI_A1 SPI mode
P4.6/PM_NONE 53 47 F3 C8 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: no secondary function.
P4.7/PM_NONE 54 48 E4 C7 I/O General-purpose digital I/O with reconfigurable port mapping secondary function
Default mapping: no secondary function.
P5.6/TB0.0 55 N/A N/A N/A I/O General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
TB0 CCR0 capture: CCI0A input, compare: Out0 output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
P5.7/TB0.1 56 N/A N/A N/A I/O General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
TB0 CCR1 capture: CCI1A input, compare: Out1 output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
P7.4/TB0.2 57 N/A N/A N/A I/O General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
TB0 CCR2 capture: CCI2A input, compare: Out2 output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
P7.5/TB0.3 58 N/A N/A N/A I/O General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
TB0 CCR3 capture: CCI3A input, compare: Out3 output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
P7.6/TB0.4 59 N/A N/A N/A I/O General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
TB0 CCR4 capture: CCI4A input, compare: Out4 output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
P7.7/TB0CLK/MCLK 60 N/A N/A N/A I/O General-purpose digital I/O (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
TB0 clock signal TBCLK input (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
MCLK output (not available on F5528, F5526, F5524, F5522, F5514, F5513 devices)
VSSU 61 49 H2 B8, B9 USB PHY ground supply
PU.0/DP 62 50 H1 A9 I/O General-purpose digital I/O. Controlled by USB control register
USB data terminal DP
PUR 63 51 G2 B7 I/O USB pullup resistor pin (open drain). The voltage level at the PUR pin is used to invoke the default USB BSL. Recommended 1-MΩ resistor to ground. See Section 6.5.1 for more information.
PU.1/DM 64 52 G1 A8 I/O General-purpose digital I/O. Controlled by USB control register
USB data terminal DM
VBUS 65 53 F2 A7 USB LDO input (connect to USB power source)
VUSB 66 54 F1 A6 USB LDO output
V18 67 55 E2 B6 USB regulated power (internal use only, no external current loading)
AVSS2 68 56 D2 A5 Analog ground supply
P5.2/XT2IN 69 57 E1 B5 I/O General-purpose digital I/O
Input terminal for crystal oscillator XT2
P5.3/XT2OUT 70 58 D1 B4 I/O General-purpose digital I/O
Output terminal of crystal oscillator XT2
TEST/SBWTCK(4) 71 59 E3 A4 I Test mode pin – selects 4-wire JTAG operation
Spy-Bi-Wire input clock when Spy-Bi-Wire operation activated
PJ.0/TDO(5) 72 60 D3 C5 I/O General-purpose digital I/O
JTAG test data output port
PJ.1/TDI/TCLK(5) 73 61 D4 C4 I/O General-purpose digital I/O
JTAG test data input
Test clock input
PJ.2/TMS(5) 74 62 C1 A3 I/O General-purpose digital I/O
JTAG test mode select
PJ.3/TCK(5) 75 63 C2 B3 I/O General-purpose digital I/O
JTAG test clock
RST/NMI/SBWTDIO(4) 76 64 D5 A2 I/O Reset input, active low(6)
Nonmaskable interrupt input
Spy-Bi-Wire data input/output when Spy-Bi-Wire operation activated
P6.0/CB0/A0 77 1 B1 A1 I/O General-purpose digital I/O
Comparator_B input CB0
Analog input A0 for ADC (not available on F551x devices)
P6.1/CB1/A1 78 2 C3 B2 I/O General-purpose digital I/O
Comparator_B input CB1
Analog input A1 for ADC (not available on F551x devices)
P6.2/CB2/A2 79 3 A1 B1 I/O General-purpose digital I/O
Comparator_B input CB2
Analog input A2 for ADC (not available on F551x devices)
P6.3/CB3/A3 80 4 C4 C2 I/O General-purpose digital I/O
Comparator_B input CB3
Analog input A3 for ADC (not available on F551x devices)
Reserved N/A N/A N/A  (2) Reserved. Connect to ground.
QFN Pad N/A Pad N/A N/A QFN package pad. TI recommends connecting to VSS.
(1) I = input, O = output, N/A = not available
(2) C6, D4, D5, D6, E3, E4, E5, E6, F3, F4, F5, F6, F7, F8, G3 are reserved and should be connected to ground.
(3) VCORE is for internal use only. No external current loading is possible. Connect VCORE to the recommended capacitor value, CVCORE (see Section 5.3).
(4) See Section 6.5 and Section 6.6 for use with BSL and JTAG functions.
(5) See Section 6.6 for use with JTAG function.
(6) When this pin is configured as reset, the internal pullup resistor is enabled by default.

5 Specifications

All graphs in this section are for typical conditions, unless otherwise noted.

Typical (TYP) values are specified at VCC = 3.3 V and TA = 25°C, unless otherwise noted.

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Voltage applied at VCC to VSS –0.3 4.1 V
Voltage applied to any pin (excluding VCORE, VBUS, V18)(2) –0.3 VCC + 0.3 V
Diode current at any device pin ±2 mA
Maximum operating junction temperature, TJ 95 °C
Storage temperature, Tstg(3) –55 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages referenced to VSS. VCORE is for internal device use only. No external DC loading or voltage should be applied.
(3) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

5.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±250
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Pins listed as ±1000 V may actually have higher performance.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process. Pins listed as ±250 V may actually have higher performance.

5.3 Recommended Operating Conditions

MIN NOM MAX UNIT
VCC Supply voltage during program execution and flash programming (AVCC = DVCC1 = DVCC2 = DVCC)(1)(3) PMMCOREVx = 0 1.8 3.6 V
PMMCOREVx = 0, 1 2.0 3.6
PMMCOREVx = 0, 1, 2 2.2 3.6
PMMCOREVx = 0, 1, 2, 3 2.4 3.6
VCC, USB Supply voltage during USB operation, USB PLL disabled,
USB_EN = 1, UPLLEN = 0		 PMMCOREVx = 0 1.8 3.6 V
PMMCOREVx = 0, 1 2.0 3.6
PMMCOREVx = 0, 1, 2 2.2 3.6
PMMCOREVx = 0, 1, 2, 3 2.4 3.6
Supply voltage during USB operation, USB PLL enabled(5),
USB_EN = 1, UPLLEN = 1		 PMMCOREVx = 2 2.2 3.6
PMMCOREVx = 2, 3 2.4 3.6
VSS Supply voltage (AVSS = DVSS1 = DVSS2 = DVSS) 0 V
TA Operating free-air temperature I version –40 85 °C
TJ Operating junction temperature I version –40 85 °C
CVCORE Recommended capacitor at VCORE(2) 470 nF
CDVCC/ CVCORE Capacitor ratio of DVCC to VCORE 10 ratio
fSYSTEM Processor frequency (maximum MCLK frequency)(4) (see Figure 5-1) PMMCOREVx = 0,
1.8 V ≤ VCC ≤ 3.6 V (default condition)		 0 8.0 MHz
PMMCOREVx = 1,
2.0 V ≤ VCC ≤ 3.6 V		 0 12.0
PMMCOREVx = 2,
2.2 V ≤ VCC ≤ 3.6 V		 0 20.0
PMMCOREVx = 3,
2.4 V ≤ VCC ≤ 3.6 V		 0 25.0
fSYSTEM_USB Minimum processor frequency for USB operation 1.5 MHz
USB_wait Wait state cycles during USB operation 16 cycles
(1) TI recommends powering AVCC and DVCC from the same source. A maximum difference of 0.3 V between AVCC and DVCC can be tolerated during power up and operation.
(2) A capacitor tolerance of ±20% or better is required.
(3) The minimum supply voltage is defined by the supervisor SVS levels when it is enabled. See the Section 5.22 threshold parameters for the exact values and further details.
(4) Modules may have a different maximum input clock specification. See the specification of the respective module in this data sheet.
(5) USB operation with USB PLL enabled requires PMMCOREVx ≥ 2 for proper operation.
MSP430F5529 MSP430F5528 MSP430F5527 MSP430F5526 MSP430F5525 MSP430F5524 MSP430F5522 MSP430F5521 MSP430F5519 MSP430F5517 MSP430F5515 MSP430F5514 MSP430F5513 slas590-op_cond.gifFigure 5-1 Maximum System Frequency

5.4 Active Mode Supply Current Into VCC Excluding External Current

over recommended operating free-air temperature (unless otherwise noted)(1)(2)(3)
PARAMETER EXECUTION MEMORY VCC PMMCOREVx FREQUENCY (fDCO = fMCLK = fSMCLK) UNIT
1 MHz 8 MHz 12 MHz 20 MHz 25 MHz
TYP MAX TYP MAX TYP MAX TYP MAX TYP MAX
IAM, Flash Flash 3.0 V 0 0.36 0.47 2.32 2.60 mA
1 0.40 2.65 4.0 4.4
2 0.44 2.90 4.3 7.1 7.7
3 0.46 3.10 4.6 7.6 10.1 11.0
IAM, RAM RAM 3.0 V 0 0.20 0.24 1.20 1.30 mA
1 0.22 1.35 2.0 2.2
2 0.24 1.50 2.2 3.7 4.2
3 0.26 1.60 2.4 3.9 5.3 6.2
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF.
(3) Characterized with program executing typical data processing. USB disabled (VUSBEN = 0, SLDOEN = 0).
fACLK = 32786 Hz, fDCO = fMCLK = fSMCLK at specified frequency.
XTS = CPUOFF = SCG0 = SCG1 = OSCOFF= SMCLKOFF = 0.

5.5 Low-Power Mode Supply Currents (Into VCC) Excluding External Current

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(1)(2)
PARAMETER VCC PMMCOREVx –40°C 25°C 60°C 85°C UNIT
TYP MAX TYP MAX TYP MAX TYP MAX
ILPM0,1MHz Low-power mode 0(3)(9) 2.2 V 0 73 77 85 80 85 97 µA
3.0 V 3 79 83 92 88 95 105
ILPM2 Low-power mode 2(4)(9) 2.2 V 0 6.5 6.5 12 10 11 17 µA
3.0 V 3 7.0 7.0 13 11 12 18
ILPM3,XT1LF Low-power mode 3, crystal mode(5)(9) 2.2 V 0 1.60 1.90 2.6 5.6 µA
1 1.65 2.00 2.7 5.9
2 1.75 2.15 2.9 6.1
3.0 V 0 1.8 2.1 2.9 2.8 5.8 8.3
1 1.9 2.3 2.9 6.1
2 2.0 2.4 3.0 6.3
3 2.0 2.5 3.9 3.1 6.4 9.3
ILPM3,VLO Low-power mode 3, VLO mode(6)(9) 3.0 V 0 1.1 1.4 2.7 1.9 4.9 7.4 µA
1 1.1 1.4 2.0 5.2
2 1.2 1.5 2.1 5.3
3 1.3 1.6 3.0 2.2 5.4 8.5
ILPM4 Low-power mode 4(7)(9) 3.0 V 0 0.9 1.1 1.5 1.8 4.8 7.3 µA
1 1.1 1.2 2.0 5.1
2 1.2 1.2 2.1 5.2
3 1.3 1.3 1.6 2.2 5.3 8.1
ILPM4.5 Low-power mode 4.5(8) 3.0 V 0.15 0.18 0.35 0.26 0.5 1.0 µA
(1) All inputs are tied to 0 V or to VCC. Outputs do not source or sink any current.
(2) The currents are characterized with a Micro Crystal MS1V-T1K crystal with a load capacitance of 12.5 pF. The internal and external load capacitance are chosen to closely match the required 12.5 pF.
(3) Current for watchdog timer clocked by SMCLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 0, OSCOFF = 0 (LPM0); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 1 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0).
(4) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 0, SCG1 = 1, OSCOFF = 0 (LPM2); fACLK = 32768 Hz, fMCLK = 0 MHz, fSMCLK = fDCO = 0 MHz; DCO setting = 1 MHz operation, DCO bias generator enabled.
USB disabled (VUSBEN = 0, SLDOEN = 0)
(5) Current for watchdog timer and RTC clocked by ACLK included. ACLK = low frequency crystal operation (XTS = 0, XT1DRIVEx = 0).
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = 32768 Hz, fMCLK = fSMCLK = fDCO = 0 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0)
(6) Current for watchdog timer and RTC clocked by ACLK included. ACLK = VLO.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 0 (LPM3); fACLK = fVLO, fMCLK = fSMCLK = fDCO = 0 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0)
(7) CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1 (LPM4); fDCO = fACLK =  fMCLK = fSMCLK = 0 MHz
USB disabled (VUSBEN = 0, SLDOEN = 0)
(8) Internal regulator disabled. No data retention.
CPUOFF = 1, SCG0 = 1, SCG1 = 1, OSCOFF = 1, PMMREGOFF = 1 (LPM4.5); fDCO = fACLK =  fMCLK = fSMCLK = 0 MHz
(9) Current for brownout, high-side supervisor (SVSH) normal mode included. Low-side supervisor and monitor disabled (SVSL, SVML). High-side monitor disabled (SVMH). RAM retention enabled.

5.6 Thermal Resistance Characteristics

THERMAL METRIC VALUE UNIT
RθJA Junction-to-ambient thermal resistance, still air Low-K board (JESD51-3) LQFP (PN) 70 °C/W
VQFN (RGC) 55
BGA (ZQE) 84
High-K board (JESD51-7) LQFP (PN) 45
VQFN (RGC) 25
BGA (ZQE) 46
RθJC Junction-to-case thermal resistance LQFP (PN) 12 °C/W
VQFN (RGC) 12
BGA (ZQE) 30
RθJB Junction-to-board thermal resistance LQFP (PN) 22 °C/W
VQFN (RGC) 6
BGA (ZQE) 20

5.7 Schmitt-Trigger Inputs – General-Purpose I/O(1)
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7,
P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN TYP MAX UNIT
VIT+ Positive-going input threshold voltage 1.8 V 0.80 1.40 V
3 V 1.50 2.10
VIT– Negative-going input threshold voltage 1.8 V 0.45 1.00 V
3 V 0.75 1.65
Vhys Input voltage hysteresis (VIT+ – VIT–) 1.8 V 0.3 0.85 V
3 V 0.4 1.0
RPull Pullup and pulldown resistor(2) For pullup: VIN = VSS
For pulldown: VIN = VCC 		20 35 50 kΩ
CI Input capacitance VIN = VSS or VCC 5 pF
(1) Same parametrics apply to clock input pin when crystal bypass mode is used on XT1 (XIN) or XT2 (XT2IN).
(2) Also applies to RST pin when pullup or pulldown resistor is enabled.

5.8 Inputs – Ports P1 and P2(1)
(P1.0 to P1.7, P2.0 to P2.7)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
t(int) External interrupt timing(2) External trigger pulse duration to set interrupt flag 2.2 V, 3 V 20 ns
(1) Some devices may contain additional ports with interrupts. See the block diagram and terminal function descriptions.
(2) An external signal sets the interrupt flag every time the minimum interrupt pulse duration t(int) is met. It may be set by trigger signals shorter than t(int).

5.9 Leakage Current – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7)
(P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3, RST/NMI)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
Ilkg(Px.y) High-impedance leakage current See (1)(2) 1.8 V, 3 V –50 50 nA
(1) The leakage current is measured with VSS or VCC applied to the corresponding pin(s), unless otherwise noted.
(2) The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup or pulldown resistor is disabled.

5.10 Outputs – General-Purpose I/O (Full Drive Strength)
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7,
P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
VOH High-level output voltage
(see Figure 5-8 and Figure 5-9)		 I(OHmax) = –3 mA(1) 1.8 V VCC – 0.25 VCC V
I(OHmax) = –10 mA(2) VCC – 0.60 VCC
I(OHmax) = –5 mA(1) 3 V VCC – 0.25 VCC
I(OHmax) = –15 mA(2) VCC – 0.60 VCC
VOL Low-level output voltage
(see Figure 5-6 and Figure 5-7)		 I(OLmax) = 3 mA(1) 1.8 V VSS VSS + 0.25 V
I(OLmax) = 10 mA(2) VSS VSS + 0.60
I(OLmax) = 5 mA(1) 3 V VSS VSS + 0.25
I(OLmax) = 15 mA(2) VSS VSS + 0.60
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±48 mA to hold the maximum voltage drop specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined should not exceed ±100 mA to hold the maximum voltage drop specified.

5.11 Outputs – General-Purpose I/O (Reduced Drive Strength)
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7,
P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)(3)
PARAMETER TEST CONDITIONS VCC MIN MAX UNIT
VOH High-level output voltage
(see Figure 5-4 and Figure 5-5)		 I(OHmax) = –1 mA(1) 1.8 V VCC – 0.25 VCC V
I(OHmax) = –3 mA(2) VCC – 0.60 VCC
I(OHmax) = –2 mA(1) 3.0 V VCC – 0.25 VCC
I(OHmax) = –6 mA(2) VCC – 0.60 VCC
VOL Low-level output voltage
(see Figure 5-2 and Figure 5-3)		 I(OLmax) = 1 mA(1) 1.8 V VSS VSS + 0.25 V
I(OLmax) = 3 mA(2) VSS VSS + 0.60
I(OLmax) = 2 mA(1) 3.0 V VSS VSS + 0.25
I(OLmax) = 6 mA(2) VSS VSS + 0.60
(1) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±48 mA to hold the maximum voltage drop specified.
(2) The maximum total current, I(OHmax) and I(OLmax), for all outputs combined, should not exceed ±100 mA to hold the maximum voltage drop specified.
(3) Selecting reduced drive strength may reduce EMI.

5.12 Output Frequency – General-Purpose I/O
(P1.0 to P1.7, P2.0 to P2.7, P3.0 to P3.7, P4.0 to P4.7,
P5.0 to P5.7, P6.0 to P6.7, P7.0 to P7.7, P8.0 to P8.2, PJ.0 to PJ.3)

over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN MAX UNIT
fPx.y Port output frequency (with load) See (1)(2) VCC = 1.8 V,
PMMCOREVx = 0		 16 MHz
VCC = 3 V,
PMMCOREVx = 3		 25
fPort_CLK Clock output frequency ACLK, SMCLK, MCLK,
CL = 20 pF(2) 		VCC = 1.8 V,
PMMCOREVx = 0		 16 MHz
VCC = 3 V,
PMMCOREVx = 3		 25
(1) A resistive divider with 2 × R1 between VCC and VSS is used as load. The output is connected to the center tap of the divider. For full drive strength, R1 = 550 Ω. For reduced drive strength, R1 = 1.6 kΩ. CL = 20 pF is connected to the output to VSS.
(2) The output voltage reaches at least 10% and 90% VCC at the specified toggle frequency.

 
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