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  • HD3SS3212-Q1 双通道差分 2:1/1:2 USB3.2 多路复用器/多路信号分离器

    • ZHCSIR3A Septmeber   2018  – June 2019 HD3SS3212-Q1

      PRODUCTION DATA.  

  • CONTENTS
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  • HD3SS3212-Q1 双通道差分 2:1/1:2 USB3.2 多路复用器/多路信号分离器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 High-Speed Performance Parameters
    7. 6.7 Switching Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 Output Enable and Power Savings
    4. 8.4 Device Functional Modes
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Applications
      1. 9.2.1 Down Facing Port for USB3.1 Type C
        1. 9.2.1.1 Design Requirements
        2. 9.2.1.2 Detailed Design Procedure
        3. 9.2.1.3 Application Curves
    3. 9.3 Systems Examples
      1. 9.3.1 Up Facing Port for USB 3.2 Type C
      2. 9.3.2 PCIe/SATA/USB
      3. 9.3.3 PCIE/eSATA
      4. 9.3.4 USB/eSATA
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 接收文档更新通知
    2. 12.2 社区资源
    3. 12.3 商标
    4. 12.4 静电放电警告
    5. 12.5 术语表
  13. 13机械、封装和可订购信息
  14. 重要声明
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DATA SHEET

HD3SS3212-Q1 双通道差分 2:1/1:2 USB3.2 多路复用器/多路信号分离器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 符合面向汽车应用的 AEC-Q100 标准
    • 温度等级 2：–40°C 至 +105°C，TA
  • 提供面向支持第 1 代和第 2 代 USB 3.2 数据速率的 USB Type-C™ 生态系统的多路复用器/多路信号分离器解决方案
  • 与 MIPI DSI/CSI、FPD-Link III、LVDS 以及 PCIe 第 II 代、第 III 代兼容
  • 运行速率高达 10Gbps
  • -3dB 差动带宽宽达 8GHz 以上
  • 出色的动态特性（5GHz 时）
    • 串扰 = –28dB
    • 关断隔离 = –19dB
    • 插入损耗 = –2dB
    • 回损 = –8dB
  • 双向“多路复用器/多路信号分离器”差分开关
  • 支持 0V 至 2V 的共模电压
  • 3.3V 的单电源电压 VCC
  • 采用汽车友好型 QFN 封装
    （2.5mm x 4.5mm，间距为 0.5mm）

2 应用

  • USB Type-C™ 生态系统
  • 汽车媒体接口
  • 音响主机
  • 后座娱乐系统
  • FPD-Link II 和 FPD-Link III 开关
  • MIPI DSI/CSI-2 开关

3 说明

HD3SS3212-Q1 是一款采用多路复用器或多路信号分离器配置的高速双向无源开关。它适用于支持 USB 3.2 第 1 代和第 2 代数据速率的 USB Type-C™ 应用。SEL 控制引脚可在两个差动通道（端口 B 到端口 A 或端口 C 到端口 A）之间切换。

HD3SS3212-Q1 是一款通用的模拟差动无源开关。该器件适用于任何要求 0V 至 2V 共模电压范围和差动振幅高达 1800mVpp 的差动信号的高速接口应用。自适应跟踪功能可确保通道在整个共模电压范围内保持不变。

该器件的出色动态特性允许进行高速开关，使信号眼图具有最小的衰减，并且不会明显增加抖动。它在运行时消耗的功率低于 1.65mW。OEn 引脚具有关断模式，从而可实现低于 0.02µW 的功耗。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
HD3SS3212-Q1 VQFN (20) 2.50mm × 4.50mm ×
0.5mm 间距
  1. 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

Device Images

空格

简化原理图

HD3SS3212-Q1 simp_schematic_slaseq6.gif

4 修订历史记录

Changes from * Revision (September 2018) to A Revision

  • 将文档从预告信息 更改为生产 数据Go

5 Pin Configuration and Functions

RKS Package
20-Pin VQFN
Top View

Pin Functions

PIN TYPE(1) DESCRIPTION
NAME NO.
VCC 6 P 3.3-V power
OEn 2 I Active-low chip enable
L: Normal operation
H: Shutdown
A0p 3 I/O Port A, channel 0, high-speed positive signal
A0n 4 I/O Port A, channel 0, high-speed negative signal
GND 5, 11, 20 G Ground
A1p 7 I/O Port A, channel 1, high-speed positive signal
A1n 8 I/O Port A, channel 1, high-speed negative signal
SEL 9 I Port select pin.
L: Port A to Port B
H: Port A to Port C
C1n 12 I/O Port C, channel 1, high-speed negative signal (connector side)
C1p 13 I/O Port C, channel 1, high-speed positive signal (connector side)
C0n 14 I/O Port C, channel 0, high-speed negative signal (connector side)
C0p 15 I/O Port C, channel 0, high-speed positive signal (connector side)
B1n 16 I/O Port B, channel 1, high-speed negative signal (connector side)
B1p 17 I/O Port B, channel 1, high-speed positive signal (connector side)
B0n 18 I/O Port B, channel 0, high-speed negative signal (connector side)
B0p 19 I/O Port B, channel 0, high-speed positive signal (connector side)
NC1 1 NA Can be left not connected or can be fed to VCC or tied to GND.
NC2 10 NA
(1) The high-speed data ports incorporate 20-kΩ pulldown resistors that are switched in when a port is not selected and switched out when the port is selected.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage –0.5 4 V
Voltage Differential I/O –0.5 2.5 V
Control pins –0.5 VCC+ 0.5
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Theseare stress ratings only, which do not imply functional operation of the device at these or anyother conditions beyond those indicated under Recommended OperatingConditions. Exposure to absolute-maximum-rated conditions for extended periods mayaffect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1)
HBM ESD Classification Level 2 		±2000 V
Charged-device model (CDM), per AEC Q100- 011
CDM ESD Classification Level C6 		±500
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN MAX UNIT
VCC Supply voltage 2.7 3.6 V
Vih Input high voltage (SEL, OEn pins) 1.7 VCC V
Vil Input low voltage (SEL, OEn pins) –0.1 0.8 V
Vdiff High-speed signal pins differential voltage 0 1.8 Vpp
Vcm High speed signal pins common mode voltage 0 2 V
TA Operating free-air/ambient temperature HD3SS3212-Q1 -40 105 °C

6.4 Thermal Information

THERMAL METRIC(1) HD3SS3212-Q1 UNIT
RKS (VQFN)
20 PINS
RθJA Junction-to-ambient thermal resistance 58.6 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 59.9 °C/W
RθJB Junction-to-board thermal resistance 32.1 °C/W
ψJT Junction-to-top characterization parameter 5.9 °C/W
ψJB Junction-to-board characterization parameter 32 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 16.7 °C/W
(1) For more information about traditional and new thermalmetrics, see the Semiconductor and IC Package ThermalMetrics application report.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
ICC Device active current VCC = 3.3 V, OEn = 0 0.5 0.8 mA
ISTDN Device shutdown current VCC = 3.3 V, OEn = VCC 0.005 1 µA
CON Output ON capacitance to GND 0.6 pF
COFF Output OFF capacitance to GND 0.8 pF
RON Output ON resistance VCC = 3.3 V; VCM = 0 to 2 V;
IO = –8 mA		 5 8 Ω
ΔRON On-resistance match between pairs of the same channel VCC = 3.3 V; –0.35 V ≤ VIN ≤ 2.35 V; IO = –8 mA 0.7 Ω
RFLAT_ON On-resistance flatness RON(MAX) – RON(MIN) VCC = 3.3 V; –0.35 V ≤ VIN ≤ 2.35 V 1 Ω
IIH,CTRL Input high current, control pins (SEL, OEn) 1 µA
IIL,CTRL Input low current, control pins (SEL, OEn) 1 µA
IIH,HS Input high current, high-speed pins [Ax/Bx/Cx][p/n] VIN = 2 V for selected port, A and B with SEL = 0, and A and C with
SEL = VCC 		1 µA
IIH,HS Input high current, high-speed pins [Ax/Bx/Cx][p/n] VIN = 2 V for non-selected port, C with SEL = 0, and B with
SEL = VCC(1) 		100 140 µA
IIL,HS Input low current, high-speed pins [Ax/Bx/Cx][p/n] 1 µA
(1) There is a 20-kΩ pull-down in non-selected port.

6.6 High-Speed Performance Parameters

PARAMETER TEST CONDITION MIN TYP MAX UNIT
IL Differential insertion loss ƒ = 0.3 MHz -0.4 dB
ƒ = 0.625 MHz -0.4
ƒ = 2.5 GHz -1
ƒ = 4 GHz -1.8
ƒ = 5 GHz -2.0
BW –3-dB bandwidth 9 GHz
RL Differential return loss ƒ = 0.3 MHz -25 dB
ƒ = 2.5 GHz -11
ƒ = 4 GHz -9
ƒ = 5 GHz -8
OIRR Differential OFF isolation ƒ = 0.3 MHz -75 dB
ƒ = 2.5 GHz -23
ƒ = 4 GHz -21
ƒ = 5 GHz -19
XTALK Differential crosstalk ƒ = 0.3 MHz -70 dB
ƒ = 2.5 GHz -35
ƒ = 4 GHz -30
ƒ = 5 GHz -28

6.7 Switching Characteristics

PARAMETER MIN TYP MAX UNIT
tPD Switch propagation delay (see Figure 3) ƒ > 1 GHz 80 ps
tSW_ON Switching time SEL-to-Switch ON (see Figure 2) 0.5 µs
tSW_OFF Switching time SEL-to-Switch OFF (see Figure 2) 0.5 µs
tSW_OEn_ON Switching time OEn-to-Switch ON 2 µs
tSW_OEn_OFF Switching time OEn-to-Switch OFF 0.1 µs
tSK_INTRA_A0B0 Intra-pair output skew for path A0 to B0. (see Figure 3) Intra-pair Skew = P - N 4.5 ps
tSK_INTRA_A0C0 Intra-pair output skew for path A0 to C0. (see Figure 3) Intra-pair Skew = P - N 1.25 ps
tSK_INTRA_A1B1 Intra-pair output skew for path A1 to B1. (see Figure 3) Intra-pair Skew = P - N -0.75 ps
tSK_INTRA_A1C1 Intra-pair output skew for path A1 to C1. (see Figure 3) Intra-pair Skew = P - N -4 ps
tSK_INTER Inter-pair output skew (see Figure 3) 20 ps

7 Parameter Measurement Information

HD3SS3212-Q1 tim_test_setup_LASE74.gifFigure 1. Test Setup
HD3SS3212-Q1 tim_on_and_off_LASE74.gifFigure 2. Switch On and Off Timing Diagram
HD3SS3212-Q1 tim_diag_test_setup_LASE74.gifFigure 3. Timing Diagrams and Test Setup

8 Detailed Description

8.1 Overview

The HD3SS3212-Q1 is a generic analog differential passive switch that can work for any high-speed interface applications requiring a common mode voltage range of 0 V to 2 V and differential signaling with differential amplitude up to 1800 mVpp. It employs adaptive tracking that ensures the channel remains unchanged for the entire common mode voltage range.

Excellent dynamic characteristics of the device allow high-speed switching with minimum attenuation to the signal eye diagram with very little added jitter. It consumes less than 1.65 mW of power when operational and has a shutdown mode exercisable by OEn pin resulting less than 0.02 µW.

8.2 Functional Block Diagram

HD3SS3212-Q1 fbd_LASE74.gif

8.3 Feature Description

8.3.1 Output Enable and Power Savings

The HD3SS3212-Q1 has two power modes, active/normal operating mode and standby/shutdown mode. During standby mode, the device consumes very-little current to save the maximum power. To enter standby mode, the OEn control pin is pulled high through a resistor and must remain high. For active/normal operation, the OEn control pin should be pulled low to GND or dynamically controlled to switch between H or L.

HD3SS3212-Q1 consumes < 1.65 mW of power when operational and has a shutdown mode exercisable by the EN pin resulting < 0.02 µW.

8.4 Device Functional Modes

Table 1. Port Select Control Logic(1)

PORT A CHANNEL PORT B OR PORT C CHANNEL CONNECTED TO PORT A CHANNEL
SEL = L SEL = H
A0p B0p C0p
A0n B0n C0n
A1p B1p C1p
A1n B1n C1n
(1) The HD3SS3212 can tolerate polarity inversions for all differential signals on Ports A, B, and C. Take care to ensure the same polarity is maintained on Port A versus Ports B/C.

9 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component specification, and TI does not warrant its accuracy or completeness. TI’s customers are responsible for determining suitability of components for their purposes. Customers should validate and test their design implementation to confirm system functionality.

9.1 Application Information

The HD3SS3212-Q1 is a generic 2-channel high-speed mux/demux type of switch that can be used for routing high-speed signals between two different locations on a circuit board. The HD3SS3212-Q1 supports several high-speed data protocols with a differential amplitude of <1800 mVpp and a common mode voltage of <2.0 V, as with USB 3.2 and DisplayPort 1.4. The device’s one select input (SEL) pin can easily be controlled by an available GPIO pin within a system or from a microcontroller.

The HD3SS3212-Q1 with its adaptive common mode tracking technology can support applications where the common mode is different between the RX and TX pair. The two USB 3.2 Type C connector applications show both a host and device side. The cable between the two connectors swivels the pairs to properly route the signals to the correct pin. The other applications are more generic because different connectors can be used.

Many interfaces require AC coupling between the transmitter and receiver. The 0201 capacitors are the preferred option to provide AC coupling; 0402 size capacitors also work. Avoid the 0603 or larger size capacitors and C-packs. When placing AC coupling capacitors, symmetric placement is best. The designer should place them along the TX pairs on the system board, which are usually routed on the top layer of the board.

The AC coupling capacitors have several placement options. Because the switch requires a bias voltage, the designer must place the capacitors on one side of the switch. If they are placed on both sides of the switch, a biasing voltage should be provided. Figure 4 shows a few placement options. The coupling capacitors are placed between the switch and endpoint. In this situation, the switch is biased by the system/host controller.

HD3SS3212-Q1 sch_ac_switch_ep_slaseq6.gifFigure 4. AC Coupling Capacitors between Switch TX and Endpoint TX

In Figure 5, the coupling capacitors are placed on the host transmit pair and endpoint transmit pair. In this situation, the switch on top is biased by the endpoint and the lower switch is biased by the host controller.

HD3SS3212-Q1 sch_ac_host_ep_slaseq6.gifFigure 5. AC Coupling Capacitors on Host TX and Endpoint TX

If the common mode voltage in the system is higher than 2 V, the coupling capacitors are placed on both sides of the switch (shown in Figure 6). A biasing voltage of <2 V is required.

HD3SS3212-Q1 sch_ac_both_slaseq6.gif
VBIAS can be GND
Capacitor and resistor values depend upon application
Figure 6. AC Coupling Capacitors on Both Sides of Switch

The HD3SS3212-Q1 can be used with the USB Type C connector to support the connector’s flip ability. Figure 7 provides the generic location for the AC coupling capacitors for this application.

HD3SS3212-Q1 sch_ac_for_USB_C_slaseq6.gifFigure 7. AC Coupling Capacitors for USB Type C

9.2 Typical Applications

9.2.1 Down Facing Port for USB3.1 Type C

HD3SS3212-Q1 app_down_facing_slaseq6.gifFigure 8. Down Facing Port for USB3.1 Type C Connector

 
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