ZHCSII4G July   2018  – October 2024 DLP230NP

PRODUCTION DATA  

  1.   1
  2. 1 特性
  3. 2 显示应用
  4. 3 说明
  5. 4 Pin Configuration and Functions
  6. 5 Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  Storage Conditions
    3. 5.3  ESD Ratings
    4. 5.4  Recommended Operating Conditions
    5. 5.5  Thermal Information
    6. 5.6  Electrical Characteristics
    7. 5.7  Timing Requirements
    8. 5.8  Switching Characteristics
    9. 5.9  System Mounting Interface Loads
    10. 5.10 Micromirror Array Physical Characteristics
    11. 5.11 Micromirror Array Optical Characteristics
    12. 5.12 Window Characteristics
    13. 5.13 Chipset Component Usage Specification
  7. 6 Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 Feature Description
      1. 6.3.1 Power Interface
      2. 6.3.2 Low-Speed Interface
      3. 6.3.3 High-Speed Interface
      4. 6.3.4 Timing
    4. 6.4 Device Functional Modes
    5. 6.5 Optical Interface and System Image Quality Considerations
      1. 6.5.1 Numerical Aperture and Stray Light Control
      2. 6.5.2 Pupil Match
      3. 6.5.3 Illumination Overfill
    6. 6.6 Micromirror Array Temperature Calculation
    7. 6.7 Micromirror Power Density Calculation
    8. 6.8 Micromirror Landed-On/Landed-Off Duty Cycle
      1. 6.8.1 Definition of Micromirror Landed-On/Landed-Off Duty Cycle
      2. 6.8.2 Landed Duty Cycle and Useful Life of the DMD
      3. 6.8.3 Landed Duty Cycle and Operational DMD Temperature
      4. 6.8.4 Estimating the Long-Term Average Landed Duty Cycle of a Product or Application
  8. 7 Application and Implementation
    1. 7.1 Application Information
    2. 7.2 Typical Application
      1. 7.2.1 Design Requirements
      2. 7.2.2 Detailed Design Procedure
      3. 7.2.3 Application Curve
  9. 8 Layout
    1. 8.1 Layout Guidelines
    2. 8.2 Layout Example
  10. 9 Power Supply Recommendations
    1. 9.1 Power Supply Power-Up Procedure
    2. 9.2 Power Supply Power-Down Procedure
    3. 9.3 Power Supply Sequencing Requirements
  11. 10Device and Documentation Support
    1. 10.1 Device Support
      1. 10.1.1 第三方产品免责声明
      2. 10.1.2 Device Nomenclature
      3. 10.1.3 Device Markings
    2. 10.2 Chipset Resources
    3. 10.3 接收文档更新通知
    4. 10.4 支持资源
    5. 10.5 Trademarks
    6. 10.6 静电放电警告
    7. 10.7 术语表
  12. 11Revision History
  13. 12Mechanical, Packaging, and Orderable Information

4 Pin Configuration and Functions

DLP230NP FQP Package, 54-Pin CLGA (Bottom View)Figure 4-1 FQP Package, 54-Pin CLGA (Bottom View)
Table 4-1 Pin Functions – Connector Pins
PIN(1)TYPESIGNALDATA RATEDESCRIPTIONPACKAGE NET LENGTH(2) (mm)
NAMENO.
DATA INPUTS
D_N(0)A2ISubLVDSDoubleData, negative1.96
D_N(1)A1ISubLVDSDoubleData, negative1.42
D_N(2)C1ISubLVDSDoubleData, negative1.35
D_N(3)B4ISubLVDSDoubleData, negative3.36
D_N(4)F5ISubLVDSDoubleData, negative4.29
D_N(5)D4ISubLVDSDoubleData, negative3.20
D_N(6)E1ISubLVDSDoubleData, negative1.76
D_N(7)F3ISubLVDSDoubleData, negative2.66
D_P(0)A3ISubLVDSDoubleData, positive1.97
D_P(1)B1ISubLVDSDoubleData, positive1.49
D_P(2)C2ISubLVDSDoubleData, positive1.44
D_P(3)A4ISubLVDSDoubleData, positive3.45
D_P(4)E5ISubLVDSDoubleData, positive4.32
D_P(5)D5ISubLVDSDoubleData, positive3.27
D_P(6)E2ISubLVDSDoubleData, positive1.85
D_P(7)F2ISubLVDSDoubleData, positive2.75
DCLK_NC3ISubLVDSDoubleClock, negative1.94
DCLK_PD3ISubLVDSDoubleClock, positive2.02
CONTROL INPUTS
LS_WDATAA12ILPSDR(1)SingleWrite data for low speed interface2.16
LS_CLKB12ILPSDRSingleClock for low-speed interface3.38
DMD_DEN_ARSTZB14ILPSDRSingleAsynchronous reset DMD signal. A low signal places the DMD in reset. A high signal releases the DMD from reset and places it in active mode.0.67
DMD_DEN_ARSTZF1ILPSDRSingle14.90
LS_RDATAC13OLPSDRSingleRead data for low-speed interface2.44
POWER
VBIAS(3)A15PowerSupply voltage for positive bias level at micromirrors
VBIAS(3)A5Power
VOFFSET(3)F13PowerSupply voltage for HVCMOS core logic. Supply voltage for stepped high level at micromirror address electrodes.
Supply voltage for offset level at micromirrors
VOFFSET(3)F4Power
VRESETB15PowerSupply voltage for negative reset level at micromirrors
VRESETB5Power
VDD(3)C15PowerSupply voltage for LVCMOS core logic. Supply voltage for LPSDR inputs.
Supply voltage for normal high level at micromirror address electrodes
VDDC5Power
VDDD14Power
VDDD15Power
VDDE14Power
VDDE15Power
VDDF14Power
VDDF15Power
VDDIC14PowerSupply voltage for SubLVDS receivers
VDDIC4Power
VDDID13Power
VDDIE13Power
VSSA13GroundCommon return.
Ground for all power
VSSA14Ground
VSSB13Ground
VSSB2Ground
VSSB3Ground
VSSC12Ground
VSSD1Ground
VSSD12Ground
VSSD2Ground
VSSE12Ground
VSSE3Ground
VSSE4Ground
VSSF12Ground
(1) Low-speed interface is LPSDR and adheres to the Electrical Characteristics and AC/DC Operating Conditions table in JEDEC Standard No. 209B, Low Power Double Data Rate (LPDDR). See JESD209B.
(2) Net trace lengths inside the package:
Relative dielectric constant for the FQP ceramic package is 9.8.
Propagation speed = 11.8 / sqrt (9.8) = 3.769in/ns.
Propagation delay = 0.265ns/inch = 265ps/in = 10.43ps/mm
(3) The following power supplies are all required to operate the DMD: VDD, VDDI, VOFFSET, VBIAS, VRESET. All VSS connections are also required.
Table 4-2 Pin Functions—Test Pads
NUMBERSYSTEM BOARD
A6Do not connect.
A7Do not connect.
A8Do not connect.
A9Do not connect.
A10Do not connect.
A11Do not connect.
F6Do not connect.
F7Do not connect.
F8Do not connect.
F9Do not connect.
F10Do not connect.
F11Do not connect.