UCC27324-Q1 双通道 4A 峰值高速低侧电源 MOSFET 驱动器
- ZHCSIF6D March 2008 – November 2023 UCC27324-Q1
  
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UCC27324-Q1 双通道 4A 峰值高速低侧电源 MOSFET 驱动器

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

符合汽车应用要求
业界通用引脚排列
可在米勒平坦区提供 ±4A 的高电流驱动
即使在低电源电压下也能实现高效的恒流源
与电源电压无关的 TTL 和 CMOS 兼容输入
1.8nF 负载时的上升时间和下降时间典型值分别为 20ns 和 15ns
输入下降和上升时的典型传播延迟时间分别为 25ns 和 35ns
电源电压为 4V 至 15V
电源电流为 0.3mA
可以并联双输出以获得更高的驱动电流
T_J 额定值范围为 –40°C 至 125°C
并联双极和 CMOS 晶体管的 TrueDrive™ 输出架构

2 应用

开关电源供电
直流/直流转换器
电机控制器
线路驱动器
D 类开关放大器

3 说明

UCC27324-Q1 高速双路 MOSFET 驱动器可向容性负载提供大峰值电流。通过使用本身能够最大限度减少击穿电流的设计，这些驱动器可在 MOSFET 开关切换期间，在米勒平坦区域提供最需要的 4A 电流。独特的双极和 MOSFET 混合输出级并联，可在低电源电压下实现高效的拉电流和灌电流。

该器件采用标准的 SOIC-8 (D) 封装。

器件信息

器件型号	封装⁽¹⁾	封装尺寸（标称值）
UCC27324-Q1	SOIC (8)	4.90mm × 3.91mm

(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

方框图

4 Pin Configuration and Functions

NC – No internal connection

Figure 4-1 D Package8-Pin SOICTop View

Table 4-1 Pin Functions

PIN		I/O	DESCRIPTION
NO.	NAME	I/O	DESCRIPTION
1	NC	—	No connection. Should be grounded.
2	INA	I	Input A. Input signal of the A driver. Has logic-compatible threshold and hysteresis. If not used, this input should be tied to either V_DD or GND. It should not be left floating.
3	GND	—	Common ground. Should be connected very closely to the source of the power MOSFET that the driver is driving.
4	INB	I	Input B. Input signal of the B driver. Has logic-compatible threshold and hysteresis. If not used, this input should be tied to either V_DD or GND. It should not be left floating.
5	OUTB	O	Driver output B. The output stage can provide 4-A drive current to the gate of a power MOSFET.
6	V_DD	I	Supply. Supply voltage and the power input connection for this device.
7	OUTA	O	Driver output A. The output stage can provide 4-A drive current to the gate of a power MOSFET.
8	NC	—	No connection. Should be grounded.

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾⁽²⁾

			MIN	MAX	UNIT
V_DD	Supply voltage		–0.3	16	V
I_O	Output current (OUTA, OUTB)	DC, I_{OUT_DC}		0.3	A
I_O	Output current (OUTA, OUTB)	Pulsed (0.5 μs), I_{OUT_PULSED}		4.5	A
T_J	Junction operating temperature		–55	150	°C
T_lead	Lead temperature			300	°C
T_stg	Storage temperature, soldering, 10 s		–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) All voltages are with respect to GND. Currents are positive into and negative out of the specified terminal.

5.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per AEC Q100-002⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per AEC Q100-011	±1000	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

5.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_DD	Supply voltage	4		15	V

5.4 Thermal Information

THERMAL METRIC⁽¹⁾		UCC27324-Q1	UNIT
		D (SOIC)
		8 PINS
R_θJA	Junction-to-ambient thermal resistance	113	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	61.7	°C/W
R_θJB	Junction-to-board thermal resistance	53.2	°C/W
ψ_JT	Junction-to-top characterization parameter	16	°C/W
ψ_JB	Junction-to-board characterization parameter	52.7	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	—	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

5.5 Overall Electrical Characteristics

V_CC = 4.5 V to 15 V, T_A = –40°C to 125°C (unless otherwise noted), T_A = T_J

PARAMETER		TEST CONDITIONS		TYP	MAX	UNIT
I_DD	Static operating current	INA = 0 V	INB = 0 V	2	80	μA
		INA = 0 V	INB = HIGH	300	450
		INA = HIGH	INB = 0 V	300	450
		INA = HIGH	INB = HIGH	600	800

5.6 Power Dissipation Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER			TEST CONDITIONS		MIN	TYP	MAX	UNIT
P_D	Power dissipation		T_A = 25°C			650	mW	μA

5.7 Input (INA, INB) Electrical Characteristics

V_CC = 4.5 V to 15 V, T_A = –40°C to 125°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
V_IH	Logic 1 input threshold		1.6	2.2	2.5	V
V_IL	Logic 0 input threshold		1.8	2.7	3.5	V
	Input current	0 V ≤ V_IN ≤ V_DD	–10	0	10	μA

5.8 Output (OUTA, OUTB) Electrical Characteristics

V_CC = 4.5 V to 15 V, T_A = –40°C to 125°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
	Output current⁽¹⁾	V_DD = 14 V	4		A
R_OH	Output resistance high⁽²⁾	I_OUT = –10 mA	0.6	1.5	Ω
R_OL	Output resistance low⁽²⁾	I_OUT = 10 mA	0.4	1	Ω

(1) Parameter not tested in production

(2) Output pullup resistance here is a DC measurement that measures resistance of PMOS structure only, not N-channel structure.

5.9 Switching Characteristics

V_CC = 4.5 V to 15 V, T_A = –40°C to 125°C (unless otherwise noted) (see Figure 5-1)

PARAMETER		TEST CONDITIONS	TYP	MAX	UNIT
t_R	Rise time (OUTA, OUTB)	C_LOAD = 1.8 nF	20	40	ns
t_F	Fall time (OUTA, OUTB)	C_LOAD = 1.8 nF	15	40	ns
t_D1	Delay time, IN rising (IN to OUT)	C_LOAD = 1.8 nF	25	40	ns
t_D2	Delay time, IN falling (IN to OUT)	C_LOAD = 1.8 nF	35	50	ns

Figure 5-1 Switching Waveforms for Noninverting Driver

5.10 Typical Characteristics

V_DD = 12 V

I_OUT = 10 mA

Figure 5-2 Fall Time vs Temperature

V_DD = 12 V

Figure 5-4 Input to Output Propagation Delay vs Temperature

Figure 5-6 Output Pulldown Resistance vs Supply Voltage

V_DD = 12 V

C_LOAD = 1.8 nF

Figure 5-3 Rise Time vs Temperature

Figure 5-5 Output Pullup Resistance vs Supply Voltage

6 Detailed Description

6.1 Overview

The UCC27324-Q1 device represents Texas Instruments' latest generation of dual-channel, low-side, high-speed gate-driver devices featuring a 4-A source and sink capability. With industry leading switching characteristics, automotive qualification, and a host of other features shown on the first page, the UCC27324-Q1 provides an efficient, robust, and reliable solution to your high current low-side driver needs in automotive applications.

6.2 Functional Block Diagram

6.3 Feature Description

6.3.1 Input Stage

The input thresholds have a 3.3-V logic sensitivity over the full range of V_DD voltage, yet it is equally compatible with 0 V to V_DD signals.

The inputs of UCC27324-Q1 device are designed to withstand 500-mA reverse current without damage to the device or logic upset. The input stage of each driver should be driven by a signal with a short rise or fall time. This condition is satisfied in typical power-supply applications, where the input signals are provided by a PWM controller or logic gates with fast transition times (<200 ns). The input stages to the drivers function as a digital gate, and they are not intended for applications where a slow changing input voltage is used to generate a switching output when the logic threshold of the input section is reached. While this may not be harmful to the driver, the output of the driver may switch repeatedly at a high frequency.

Users should not attempt to shape the input signals to the driver in an attempt to slow down (or delay) the signal at the output. If limiting the rise or fall times to the power device is desired, limit the rise or fall times to the power device, then an external resistance can be added between the output of the driver and the load device, which is generally a power MOSFET gate. The external resistor also may help remove power dissipation from the device package, as discussed in the Section 9.3 section.

6.3.2 Output Stage

Noninverting outputs of the UCC27324-Q1 are intended to drive external N-channel MOSFETs.

Each output stage is capable of supplying ±4-A peak current pulses and swings to both V_DD and GND. The pullup and pulldown circuits of the driver are constructed of bipolar and MOSFET transistors in parallel. The peak output current rating is the combined current from the bipolar and MOSFET transistors. The output resistance is the R_DS(ON) of the MOSFET transistor when the voltage on the driver output is less than the saturation voltage of the bipolar transistor. Each output stage also provides a very low impedance to overshoot and undershoot, due to the body diode of the external MOSFET. This means that, in many cases, external Schottky-clamp diodes are not required.

The UCC27324-Q1 device delivers a 4-A gate drive when it is most needed during the MOSFET switching transition—at the Miller plateau region—providing improved efficiency gains. A unique bipolar and MOSFET hybrid output stage in parallel also allows efficient current sourcing at low supply voltages.

6.4 Device Functional Modes

Table 6-1 lists the device functions.

Table 6-1 Function Table

INPUTS		UCC27324-Q1 OUTPUTS
INA	INB	OUTA	OUTB
L	L	L	L
L	H	L	H
H	L	H	L
H	H	H	H

7 Application and Implementation

Note:

以下应用部分中的信息不属于TI 器件规格的范围，TI 不担保其准确性和完整性。TI 的客户应负责确定器件是否适用于其应用。客户应验证并测试其设计，以确保系统功能。

7.1 Application Information

High-frequency power supplies often require high-speed high-current drivers such as the UCC27324-Q1 device. A leading application is the need to provide a high-power buffer stage between the PWM output of the control device and the gates of the primary power MOSFET or IGBT switching devices. In other cases, the driver is used to drive the power device gates through a drive transformer. Synchronous rectification supplies must also simultaneously drive multiple devices, which can present an extremely large load to the control circuitry.

Drivers are used when using the primary PWM regulator to directly drive the switching devices is not feasible for one or more reasons. The PWM device may not have the brute drive capability required for the intended switching MOSFET, limiting the switching performance in the application. In other cases, minimizing the effect of high-frequency switching noise by placing the high-current driver physically close to the load may be necessary. Also, newer devices that target the highest operating frequencies may not incorporate onboard gate drivers at all. The PWM outputs are intended to drive only the high-impedance input to a driver such as the UCC27324-Q1. Finally, the control device may be under thermal stress because power dissipation, and an external driver can help by moving the heat from the controller to an external package.

7.1.1 Parallel Outputs

The A and B drivers may be combined into a single driver by connecting the INA an INB inputs together and the OUTA and OUTB outputs together (respectively). Then, a single signal can control the paralleled combination as shown in Figure 7-1.

Figure 7-1 Combined Input and Output Configuration