具有较高的轻负载效率的 UCC28064A Natural Interleaving™ 转换模式 PFC 控制器
- ZHCSIB2B December 2017 – October 2019 UCC28064A
  
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具有较高的轻负载效率的 UCC28064A Natural Interleaving™ 转换模式 PFC 控制器

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

降低了输入滤波器和输出电容器纹波电流
- 为了实现更高系统可靠性和更小大容量电容器而减少的电流纹波
- 缩小的电磁干扰 (EMI) 滤波器尺寸
高轻负载效率
- 具有输入电压补偿功能的用户可调节相位管理
- 具有可调突发阈值的突发模式
- 有助于符合 EUP Lot6 Tier II、CoC Tier II 和 DOE Level VI 标准
无传感器电流整形简化了电路板布局并提升了效率
输入线路前馈可实现快速线路瞬态响应
浪涌安全电流限制：
- 在浪涌期间防止 MOSFET 导通
- 消除输出整流器中的 CCM 操作和反向恢复事件
采用 16 引脚 SOIC 封装，工作温度范围为 –40°C 至 +125°C
使用 UCC28064A 及其 WEBENCH® 电源设计器创建定制设计

2 应用

高清、超高清和 LED 电视
一体式计算机
游戏
适配器
家用音频系统

3 说明

与之前的同类产品相比，UCC28064A 交错式 PFC 控制器具有更高的功率额定值。该器件采用了 Natural Interleaving™ 技术。两个通道均作为主通道运行（即没有从通道），而且这两个通道同步至同一频率。这种方法可以实现更快的响应、出色的相间导通时间匹配以及每个通道的转换模式。该器件具有突发模式功能，可获得较高的轻负载效率。由于具有突发模式，因此在轻负载运行期间无需关闭 PFC 即可实现待机功率目标。而且，由于具有该模式，在与 UCC25630x LLC 控制器和 UCC24624 同步整流器控制器配对使用时，该器件无需使用辅助反激式转换器。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
UCC28064A	SOIC (16)	9.90mm x 3.91mm

如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

Device Images

简化应用

4 修订历史记录

Changes from A Revision (October 2018) to B Revision

Changed 更改了“简化应用”示意图Go

5 说明（续）

扩展的系统级保护特性包括输入欠压和压降恢复、输出过压、开环、过载、软启动、相位故障检测以及热关断保护。附加的失效防护过压保护 (OVP) 特性可防止到一个中间电压的短路，如果没有检测到此短路的话，有可能导致非常严重的器件故障。该器件具有高级非线性增益，可针对线路和负载瞬态事件提供快速而平滑的响应。特殊的线路压降处理可避免严重的电流中断。在突发模式期间，不发生切换时偏置电流会大幅降低，从而提高了待机性能。

6 Pin Configuration and Functions

D Package

16-Pin SOIC

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NO.	I/O	DESCRIPTION
AGND	6	-	Analog ground
BRST	9	I	Burst mode threshold input
COMP	5	O	Error amplifier output
CS	10	I	Current sense input
GDA	14	O	Phase A gate driver output
GDB	11	O	Phase B gate driver output
HVSEN	8	I	High voltage output sense
PGND	13	-	Power ground
PHB	4	I	Phase B enable disable threshold input
TSET	3	I	Timing set
VCC	12	-	Bias supply input
VINAC	7	I	Input AC voltage sense
VSENSE	2	I	Error amplifier input
VREF	15	O	Voltage reference output
ZCDA	16	I	Phase A zero current detection input
ZCDB	1	I	Phase B zero current detection input

7 Specifications

7.1 Absolute Maximum Ratings

All voltages are with respect to GND, −40°C < T_J = T_A < 125°C, currents are positive into and negative out of the specified terminal, unless otherwise noted.

			MIN	MAX	UNIT
	Continuous input voltage	VCC⁽¹⁾	−0.5	21	V
		COMP⁽²⁾, PHB, HVSEN⁽³⁾, VINAC⁽³⁾, VSENSE⁽³⁾, TSET, BRST	–0.5	7
		ZCDA, ZCDB	–0.5	4
		CS⁽⁴⁾	–0.5	3
		GDA, GDB⁽⁵⁾	–0.5	VCC + 0.3
	Continuous input current	VCC		20	mA
		ZCDA, ZCDB		±5
		GDA, GDB⁽⁵⁾	–25	25
		VREF	–2
	Peak input current	CS	–30		mA
T_J	Operating junction temperature		–40	125	°C
T_SOL	Soldering 10 s			260	°C
T_stg	Storage temperature		–65	150	°C

(1) Voltage on VCC is internally clamped. VCC may exceed the continuous absolute maximum input voltage rating if the source is current limited below the absolute maximum continuous VCC input current level.

(2) In normal use, COMP is connected to capacitors and resistors and is internally limited in voltage swing.

(3) In normal use, VINAC, VSENSE, and HVSEN are connected to high-value resistors and are internally limited in negative-voltage swing. Although not recommended for extended use, VINAC, VSENSE, and HVSEN can survive input currents as high as -10mA from negative voltage sources, and input currents as high as +0.5mA from positive voltage sources.

(4) In normal use, CS is connected to a series resistor to limit peak input current during brief system line-inrush conditions. In these situations, negative voltage on CS may exceed the continuous absolute maximum rating.

(5) No GDA or GDB current limiting is required when driving a power MOSFET gate. However, a small series resistor may be required to damp resonant ringing due to stray inductance.

7.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

All voltages are with respect to GND, −40°C < T_J = T_A < 125°C, currents are positive into and negative out of the specified terminal, unless otherwise noted.

	MIN	MAX	UNIT
VCC input voltage from a low-impedance source	14	21	V
VCC input current from a high-impedance source	8	18	mA
VINAC input voltage	0	6	V
VREF load current	0	–2	mA
ZCDA, ZCDB series resistor	20	80	kΩ
TSET resistor to program PWM on-time	66.5	400	kΩ
HVSEN input voltage	0.8	4.5	V
PHB Phase management threshold voltage	0	2	V
BRST Burst mode threshold voltage	0	V_PHB - 0.6 V	V

7.4 Thermal Information

THERMAL METRIC		UCC28064A	UNIT
		SOIC (D)
		16 PINS
R_θJA	Junction-to-ambient thermal resistance⁽⁴⁾	91.6	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance⁽³⁾	52.1	°C/W
R_θJB	Junction-to-board thermal resistance⁽²⁾	48.6	°C/W
ψ_JT	Junction-to-top characterization parameter⁽¹⁾	14.9	°C/W
ψ_JB	Junction-to-board characterization parameter⁽⁵⁾	48.3	°C/W

(1) The junction-to-top characterization parameter, ψ_JT, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

(2) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB temperature, as described in JESD51-8.

(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDECstandard test exists, but a close description can be found in the ANSI SEMI standard G30-88.

(4) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as specified in JESD51-7, in an environment described in JESD51-2a.

(5) The junction-to-board characterization parameter, ψ_JB, estimates the junction temperature of a device in a real system and is extracted from the simulation data for obtaining R_θJA, using a procedure described in JESD51-2a (sections 6 and 7).

7.5 Electrical Characteristics

At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 0V, BRST = 0V, R_TSET = 133 kΩ, all voltages are with respect to GND, all outputs unloaded, −40°C < T_J = T_A < 125°C, and currents are positive into and negative out of the specified terminal, unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
VCC BIAS SUPPLY
VCC_SHUNT	VCC shunt voltage⁽¹⁾	I_VCC = 10 mA	22	24	26	V
I_VCC(UVLO)	VCC current, UVLO	VCC = 9.3 V prior to turn on		125	200	µA
I_VCC(stby)	VCC current, disabled	VSENSE = 0 V		150	210	µA
I_VCC(on)	VCC current, enabled	VSENSE = 2 V		5	8	mA
I_VCC(BURST)	VCC current burst mode no switching	V_COMP < V_BURST		650	850	µA
UNDERVOLTAGE LOCKOUT (UVLO)
VCC_ON	VCC turnon threshold	VCC rising	9.45	10.35	11.1	V
VCC_OFF	VCC turnoff threshold	VCC falling	8.8	9.6	10.7	V
ΔVCC_UVLO	UVLO Hysteresis	VCC_ON - VCC_OFF	0.68	0.8	0.9	V
REFERENCE
V_REF	VREF output voltage, no load	I_VREF = 0 mA	5.82	6.00	6.18	V
ΔV_{REF_LOAD}	VREF change with load	0 mA ≤ I_VREF ≤ −2 mA	-6	-1		mV
ΔV_{REF_VCC}	VREF change with VCC	12 V ≤ VCC ≤ 20 V		2	10	mV
ERROR AMPLIFIER
VSENSEreg25	VSENSE input regulation voltage	T_A = 25°C	5.85	6	6.15	V
VSENSEreg	VSENSE input regulation voltage		5.82	6	6.18	V
I_VSENSE	VSENSE input bias current	In regulation	50	100	150	nA
V_ENAB	VSENSE enable threshold, rising		1.15	1.25	1.35	V
	VSENSE enable hysteresis		0.02	0.07	0.15	V
V_{COMP_CLMP}	COMP high voltage, clamped	VSENSE = VSENSEreg – 0.3 V	4.70	4.95	5.10	V
V_{COMP_SAT}	COMP low voltage, saturated	VSENSE = VSENSEreg + 0.3 V		0.03	0.125	V
g_M1	VSENSE to COMP transconductance, small signal	0.99(VSENSEreg) < VSENSE < 1.01(VSENSEreg), COMP = 3 V	40	55	70	µS
V_{SENSE_gM2_SINK}	VSENSE high-going threshold to enable COMP large signal gain, percent	Relative to VSENSEreg, COMP = 3 V	3.25	5	6.75	%
V_{SENSE_gM2_SOURCE}	VSENSE low-going threshold to enable COMP large signal gain, percent	Relative to VSENSEreg, COMP = 3 V	–6.75	−5	−3.25	%
g_{M2_SOURCE}	VSENSE to COMP transconductance, large signal	VSENSE = VSENSEreg – 0.4 V , COMP = 3 V	210	290	370	µS
g_{M2_SINK}	VSENSE to COMP transconductance, large signal	VSENSE = VSENSEreg + 0.4 V, COMP = 3 V	210	290	370	µS
I_{COMP_SOURCE_MAX}	COMP maximum source current	VSENSE = 5 V, COMP = 3 V	-170	-125	-80	µA
R_COMPDCHG	COMP discharge resistance	HVSEN = 5.2 V, COMP = 3 V	1.6	2	2.4	kΩ
I_DODCHG	COMP discharge current during Dropout	VSENSE = 5 V, VINAC = 0.3 V, COMP = 1V	3.2	4	4.8	µA
V_{LOW_OV}	VSENSE overvoltage threshold, rising	Relative to VSENSEreg	6.5	8	9.5	%
ΔV_{LOW_OV_HYST}	VSENSE overvoltage hysteresis	Relative to V_{LOW_OV}	-3	-2	-1.5	%
V_{HIGH_OV}	VSENSE 2nd overvoltage threshold, rising	Relative to VSENSEreg	9.3	11	12.7	%
SOFT START
V_SSTHR	COMP Soft-Start threshold, falling	VSENSE = 1.5 V	10	23	35	mV
I_SS,FAST	COMP Soft-Start current, fast	SS-state, V_ENAB < VSENSE < VREF/2	-170	-125	-80	µA
I_SS,SLOW	COMP Soft-Start current, slow	SS-state, VREF/2 < VSENSE < 0.88VREF	-20	-16	-11.5	µA
K_EOSS	VSENSE End-of-Soft-Start threshold factor	Percent of VSENSEreg	96.5%	98.3%	99.8%
OUTPUT MONITORING
V_{HV_OV_FLT}	HVSEN threshold to overvoltage fault	HVSEN rising	4.64	4.87	5.1	V
V_{HV_OV_CLR}	HVSEN threshold to overvoltage clear	HVSEN falling	4.45	4.67	4.8	V
GATE DRIVE
V_{GDx_H}	GDA, GDB output voltage, high	I_GDA, I_GDB = −100 mA	10.7	12.4	15	V
R_{GDx_H}	GDA, GDB on-resistance, high	I_GDA, I_GDB = −100 mA		8.8	16.7	Ω
V_{GDx_L}	GDA, GDB output voltage, low	I_GDA, I_GDB = 100 mA		0.18	0.32	V
R_{GDx_L}	GDA, GDB on-resistance, low	I_GDA, I_GDB = 100 mA		2	3.2	Ω
V_{GDx_H_VCCH}	GDA, GDB output voltage high, clamped	VCC = 20 V, I_GDA, I_GDB = −5 mA	11.8	13.5	15	V
V_{GDx_H_VCCL}	GDA, GDB output voltage high, low VCC	VCC = 12 V, I_GDA, I_GDB = −5 mA	10	10.5	11.5	V
V_{GDx_L_UVLO}	GDA, GDB output voltage, UVLO	VCC = 3.0 V, I_GDA, I_GDB = 2.5 mA		100	200	mV
t_{GDx_RISE}	Rise time	1 V to 9 V, C_LOAD = 1 nF		18	30	ns
t_{GDx_FALL}	Fall time	9 V to 1 V, C_LOAD = 1 nF		12	25	ns
ZERO CURRENT DETECTOR
V_{ZCDx_TRIG}	ZCDA, ZCDB voltage threshold, falling		0.8	1	1.2	V
V_{ZCDx_ARM}	ZCDA, ZCDB voltage threshold, rising		1.5	1.7	1.9	V
V_{ZCDx_CLMP_H}	ZCDA, ZCDB clamp, high	I_ZCDA = +2 mA, I_ZCDB = +2 mA	2.6	3	3.4	V
V_{ZCDx_CLMP_L}	ZCDA, ZCDB clamp, low	I_ZCDA = −2 mA, I_ZCDB = −2 mA	-0.40	−0.2	0	V
I_ZCDx	ZCDA, ZCDB input bias current	ZCDA = 1.4 V, ZCDB = 1.4 V	-0.5	0	0.5	µA
t_{ZCDx_DEL}	ZCDA, ZCDB delay to GDA, GDB outputs	From ZCDx input falling to 1 V to respective gate drive output rising 10%		50	100	ns
t_{ZCDx_BLNK}	ZCDA, ZCDB blanking time	From GDx rising to GDx falling		100		ns
CURRENT SENSE
I_CS	CS input bias current, dual-phase	At rising threshold	-200	-166	-120	µA
V_{CS_DPh}	CS current-limit rising threshold, dual-phase		-0.22	-0.2	-0.18	V
V_{CS_SPh}	CS current-limit rising threshold, single-phase	PHB = 6 V	-0.183	-0.166	-0.149	V
V_{CS_RST}	CS current-limit reset falling threshold		-0.025	–0.015	-0.002	V
t_{CS_DEL}	CS current-limit response time	From CS exceeding threshold−0.05 V to GDx dropping 10%		60	100	ns
t_{CS_BLNK}	CS blanking time	From GDx rising and falling edges		100		ns
VINAC INPUT
I_VINAC	VINAC input bias current, above brownout	VINAC = 2 V	-0.5	0	0.5	µA
V_BOTHR	VINAC brownout threshold		1.33	1.45	1.6	V
t_BODLY	VINAC brownout filter time	VINAC below the brownout threshold for the brownout filter time	500	640	810	ms
t_BORST	VINAC brownout reset time	VINAC above the brownout threshold for the brownout reset time after Brown out event	300	450	600	ms
I_BOHYS	VINAC brownout hysteresis current	VINAC = 1 V for > t_BODLY	1.6	1.95	2.25	µA
V_DODET	VINAC dropout detection threshold	VINAC falling	0.310	0.35	0.38	V
t_DODLY	VINAC dropout filter time	VINAC below the dropout detection threshold for the dropout filter time	3.5	5	7	ms
V_DOCLR	VINAC dropout clear threshold	VINAC rising	0.67	0.71	0.75	V
PULSE-WIDTH MODULATOR
K_TL	On-time factor, two phases operating, low VINAC_PK	VINAC=1.6V, VCOMP=4V⁽²⁾	3.0	4.15	5.3	µs/V
K_TH	On-time factor, two phases operating, high VINAC_PK	VINAC= 5V, VCOMP = 4V⁽²⁾	0.36	0.43	0.5	µs/V
K_TSL	On-time factor, single-phase operating, low VINAC_PK	VINAC=1.6V, VCOMP = 1.5V, PHB = 2V⁽²⁾	6.1	8.3	10.5	µs/V
K_TSH	On-time factor, single-phase operating, high VINAC_PK	VINAC= 5V, VCOMP = 1.5V, PHB=2V⁽²⁾	0.73	0.87	1.01	µs/V
t_{ZCC_I}	Zero-crossing distortion correction additional on time	COMP = 0.5 V, VINAC = 0.1 V	15	23.6	32.2	µs
t_{ZCC_II}	Zero-crossing distortion correction additional on time	COMP = 0.5 V, VINAC = 1.6 V	0.7	1.1	1.5	µs
t_MIN	Minimum Switching period	R_TSET = 133 kΩ, VCOMP = 0.3, VINAC = 3 V⁽²⁾	1.9	2.7	3.5	µs
t_START	PWM restart time	ZCDA = ZCDB = 2 V⁽³⁾	160	210	265	µs
t_{ONMAX_L}	Maximum FET on time at low VINAC	VSENSE = 5.8 V, VINAC=1.6V	15.1	20.4	26.2	µs
t_{ONMAX_H}	Maximum FET on time at High VINAC	VSENSE = 5.8 V, VINAC= 5V	1.5	2	2.4	µs
t_{ONMAX_SL}	Maximum FET on time at low VINAC, Single Phase operation.	VSENSE = 5.8V, VINAC=1.6V, PHB = 6V	11.8	16	20.2	µs
t_{ONMAX_SH}	Maximum FET on time at hgih VINAC, single phase operation	VSENSE = 5.8V, VINAC=5 V, PHB = 6V	1.37	1.66	1.95	µs
Δt_{ONMAX_AB_L}	Phase B to phase A on-time matching error	VSENSE = 5.8 V, VINAC=1.6V	–6		6	%
Δt_{ONMAX_AB_H}	Phase B to phase A on-time matching error	VSENSE = 5.8 V, VINAC= 5V	-6		6	%
ΔV_{BRST_HYST}	BRST Hysteresis, COMP voltage rising	BRST = 1V, VINAC = 1.5 V	30	50	70	mV
ΔV_{PHB_HYST}	PHB Hysteresis COMP voltage rising	PHB = 3V, VINAC = 2.5 V	80	150	210	mV
I_{PHB_RANGE}	PHB pin sourced current when high input voltage	VINAC = 3.75V, PHB = 2V	2	3	4.1	µA
I_{BRST_RANGE}	BRST pin sourced current when high input voltage	VINAC = 3.75V, BRST = 2V	2	3	4.1	µA
V_VINAC_{_}_{RANGE_THF}	VINAC range falling threshold	PHB = 2V, BRST = 2V	2.95	3.15	3.3	V
ΔV_{INAC_RANGE}	VINAC range Hysteresis at rising edge	PHB = 2V, BRST=2V	300	350	400	mV
THERMAL SHUTDOWN
T_J	Thermal shutdown temperature	Temperature rising⁽⁴⁾		160		°C
T_J	Thermal restart temperature	Temperature falling⁽⁴⁾		140		°C

(1) Excessive VCC input voltage and current will damage the device. This clamp will not protect the device from an unregulated bias supply. If an unregulated bias supply is used, a series-connected Fixed Positive-Voltage Regulator such as the UA78L15A is recommended. See the Absolute Maximum Ratings table for the limits on VCC voltage, current, and junction temperature.

(2) Gate drive on-time is proportional to (VCOMP – 0.125 V). The on-time proportionality factor, KT, scales linearly with the value of RTSET and is different in two-phase and single-phase modes. The minimum switching period is proportional to RTSET.

(3) An output on-time is generated at both GDA and GDB if both ZCDA and ZCDB negative-going edges are not detected for the restart time. In single-phase mode, the restart time applies for the ZCDA input and the GDA output.

(4) Thermal shutdown occurs at temperatures higher than the normal operating range. Device performance above the normal operating temperature is not specified or assured.

7.6 Typical Characteristics

V_VCC = 16 V, V_AGND = V_PGND = 0 V, V_VINAC = 3 V, V_VSENSE = 6 V, V_HVSEN = 3 V, V_PHB = 0 V, R_TSET = 133 kΩ; all voltages are with respect to GND, all outputs unloaded, T_J = 25°C, and currents are positive into and negative out of the specified terminal, unless otherwise noted.

Figure 1. RTSET Resistance and Zero-Crossing Distortion Correction Additional On Time

Figure 3. VINAC Brownout Hysteresis Current

Figure 5. UVLO On Off Thresholds

Figure 7. VCC Bias Supply Current

Figure 9. Error Amplifier Transconductance vs VSENSE

Figure 11. Error Amplifier Output Current vs Output Voltage

C_LOAD = 4.7 nF

Figure 13. Gate Drive Falling vs Time

UCC28064A tc_gate_fall-t_delay_lus837.gif

C_LOAD = 4.7 nF

Figure 15. Gate Drive Falling and Delay From CS Input vs Time

Figure 2. VINAC Brownout Detection Threshold

Figure 4. VREF Output Voltage

Figure 6. UVLO Hysteresis

UCC28064A eaiout_vs_vsensevin_slusde9.gif

Soft-start period completed

Figure 8. Error Amplifier Output Current vs Input Voltage

Figure 10. Error Amplifier Transconductance vs Temperature

C_LOAD = 4.7 nF

Figure 12. Gate Drive Rising vs Time

UCC28064A tc_gate_rise-t_delay_lus837.gif

C_LOAD = 4.7 nF

Figure 14. Gate Drive Rising and Delay From ZCD Input vs Time

8 Detailed Description

8.1 Overview

Transition mode (TM) control is a popular choice for the boost power factor correction topology at lower power levels. Some advantages of this control method are its lower complexity in achieving high power factor and because lower cost boost diode with higher reverse recovery current specification may be used. In TM control MOSFET is turned on always when no current is flowing into diode. Interleaved Transition Mode Control retains this benefit and generally extends the applicability up to much higher power levels while simultaneously conferring the interleaving benefits of reduced input and output ripple current and system thermal optimization.

In UCC28064A, burst mode was introduced respect its predecessor (UCC28063) to achieve higher efficiency in light load conditions. Input voltage feed-forward and threshold adjustment is also available to ensure the user can optimize performance across line and load conditions. When operating single phase on time of the switching phase is doubled with the purpose of compensating the missing power from the not switching phase. In this way for the same COMP value the converter should provide the same output power regardless if operating single phase mode or dual phase mode. Unfortunately this is not always the case. Component variations and MOSFETs turn-off delay can lead to big differences (for the same COMP voltage) in the output power delivery. The Phase Management and Light-Load Operation section will discuss some ways to deal with the variations.

Line voltage feed-forward compensation provides several benefits: it maintains constant bandwidth of the control loop versus line voltage variation, avoids high current in the MOSFETs, inductors, and line filter when line transitions from low to high happens, and helps to keep simple Phase Management control because the COMP pin voltage is almost proportional to Load. Burst Mode enables high efficiency at light load and soft-on and soft-off in burst mode reduces risk of audible noise. The optimal load current at which the converter should enter burst mode can be different for different input voltages. These thresholds can be customized by the user.

Interleaving control and phase management facilitates high efficiency 80+ and Energy Star designs with reduced input and output ripple. The Natural Interleaving method allows TM operation and achieves 180 degrees between the phases by On-time management. Moreover Natural interleaving method does not rely on tight tolerance requirements on the inductors. Negative current sensing is implemented on the total input current instead of just the MOSFET current which prevents MOSFET switching during inrush surges or in any mode where the inductor current may enter in continuous conduction mode (CCM). This prevents reverse recovery conduction events between the MOSFET and output rectifier.

Independent output voltage sense circuits with their separate fault management behaviors provide a high degree of redundancy against PFC stage over-voltage. Brownout, over voltage protection on HVSEN pin (HVSENSE OV), under voltage lockout (UVLO), and device over-temperature faults will all cause a complete Soft-Start cycle. Other faults such as short duration AC Drop-Out, minor over-voltage or cycle-by-cycle over-current cause a live recovery process to initiate by pulling down the COMP pin or by terminating the pulses early.

The error amplifier transconductance is designed to allow smaller compensation components and optimum transient response for large changes in line or load. The Soft-Start process is carefully optimized. A complete Soft-Start is implemented. It is dependent on the output voltage sense to speed up start-up from low AC line and to minimize the effect of excessive capacitance on the COMP pin during start-up into no-load. If some faults events are triggered COMP pin is fast pulled down to zero. This complete discharge of COMP aids with preventing excessive currents on recovery from an AC Brown-Out event.