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  • OPA858 5.5GHz 增益带宽积、7V/V 增益稳定型 FET 输入放大器

    • ZHCSI18A April   2018  – July 2018 OPA858

      PRODUCTION DATA.  

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  • OPA858 5.5GHz 增益带宽积、7V/V 增益稳定型 FET 输入放大器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      高速飞行时间接收器
      2.      光电二极管电容与带宽和噪声
  4. 4 修订历史记录
  5. 5 Device Comparison Table
  6. 6 Pin Configuration and Functions
    1.     Pin Functions
  7. 7 Specifications
    1. 7.1 Absolute Maximum Ratings
    2. 7.2 ESD Ratings
    3. 7.3 Recommended Operating Conditions
    4. 7.4 Thermal Information
    5. 7.5 Electrical Characteristics
    6. 7.6 Typical Characteristics
  8. 8 Parameter Measurement Information
    1. 8.1 Parameter Measurement Information
  9. 9 Detailed Description
    1. 9.1 Overview
    2. 9.2 Functional Block Diagram
    3. 9.3 Feature Description
      1. 9.3.1 Input and ESD Protection
      2. 9.3.2 Feedback Pin
      3. 9.3.3 Wide Gain-Bandwidth Product
      4. 9.3.4 Slew Rate and Output Stage
      5. 9.3.5 Current Noise
    4. 9.4 Device Functional Modes
      1. 9.4.1 Split-Supply and Single-Supply Operation
      2. 9.4.2 Power-Down Mode
  10. 10Application and Implementation
    1. 10.1 Application Information
      1. 10.1.1 Using the OPA858 as a Transimpedance Amplifier
    2. 10.2 Typical Application
      1. 10.2.1 Design Requirements
      2. 10.2.2 Detailed Design Procedure
      3. 10.2.3 Application Curves
  11. 11Power Supply Recommendations
  12. 12Layout
    1. 12.1 Layout Guidelines
    2. 12.2 Layout Example
  13. 13器件和文档支持
    1. 13.1 接收文档更新通知
    2. 13.2 社区资源
    3. 13.3 商标
    4. 13.4 静电放电警告
    5. 13.5 术语表
  14. 14机械、封装和可订购信息
  15. 重要声明
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DATA SHEET

OPA858 5.5GHz 增益带宽积、7V/V 增益稳定型 FET 输入放大器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 高增益带宽积：5.5GHz
  • 解补偿，增益 ≥ 7V/V（稳定）
  • 超低偏置电流 MOSFET 输入：10pA
  • 低输入电压噪声：2.5nV/√Hz
  • 压摆率：2000V/µs
  • 低输入电容：
    • 共模：0.6pF
    • 差动：0.2pF
  • 宽输入共模范围：
    • 与正电源相差 1.4V
    • 包括负电源
  • TIA 配置下的输出摆幅为 2.5VPP
  • 电源电压范围：3.3V 至 5.25V
  • 静态电流：20.5mA
  • 采用 8 引脚 WSON 封装
  • 温度范围：–40 至 +125°C

2 应用

  • 高速跨阻放大器
  • 激光测距
  • 激光雷达接收器
  • 液位变送器（光学）
  • 光学时域反射法 (OTDR)
  • 分布式温度检测
  • 3D 扫描仪
  • 飞行时间 (ToF) 系统
  • 自主驾驶系统

    • 空白

3 说明

OPA858 是一款具有 CMOS 输入的低噪声运算放大器，适用于宽带跨阻和电压放大器 应用。当将该器件配置为跨阻放大器 (TIA) 时，5.5GHz 增益带宽积 (GBWP) 可为 需要 在数十至数百千欧范围内的跨阻增益下实现高闭环带宽的应用提供支持。

下图展示了当将 OPA858 配置为 TIA 时，该放大器的带宽和噪声性能与光电二极管电容的函数关系。计算总噪声时所依据的带宽范围为：从直流到左轴上计算得出的 f-3dB 频率。OPA858 封装 具有 反馈引脚 (FB)，可简化输入和输出之间的反馈网络连接。

OPA858 经过优化，可用于光学飞行时间 (ToF) 系统，下图所示系统便是一个例子，其中 OPA858 是与 TDC7201 时数转换器搭配使用。OPA858 可搭配高速模数转换器 (ADC) 和用以驱动该 ADC 的差动输出放大器（如 THS4541 或 LMH5401），用于高分辨率激光雷达系统。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
OPA858 WSON (8) 2.00mm × 2.00mm
  1. 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。

Device Images

高速飞行时间接收器

OPA858 alt_adc_interface_OPA858_sbos852.gif

光电二极管电容与带宽和噪声

OPA858 D209_SBOS629.gif

4 修订历史记录

Changes from * Revision (April 2018) to A Revision

  • Changed 将器件状态从“预告信息”更改为“生产数据” Go

5 Device Comparison Table

DEVICE INPUT TYPE MINIMUM STABLE GAIN VOLTAGE NOISE (nV/√Hz) INPUT CAPACITANCE (pF) GAIN BANDWIDTH (GHz)
OPA858 CMOS 7 V/V 2.5 0.8 5.5
OPA855 Bipolar 7 V/V 0.98 0.8 8
LMH6629 Bipolar 10 V/V 0.69 5.7 4

6 Pin Configuration and Functions

DSG Package
8-Pin WSON With Exposed Thermal Pad
Top View
OPA858 OPA85X_DSG_pin_diagram.gif
NC - no internal connection

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
FB 1 I Feedback connection to output of amplifier
IN– 3 I Inverting input
IN+ 4 I Noninverting input
NC 2 — Do not connect
OUT 6 O Amplifier output
PD 8 I Power down connection. PD = logic low = power off mode; PD = logic high = normal operation
VS– 5 — Negative voltage supply
VS+ 7 — Positive voltage supply
Thermal pad — Connect the thermal pad to VS–

7 Specifications

7.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VS Total supply voltage (VS+ – VS–) 5.5 V
VIN+, VIN– Input voltage (VS–) – 0.5 (VS+) + 0.5
VID Differential input voltage 1
VOUT Output voltage (VS–) – 0.5 (VS+) + 0.5
IIN Continuous input current ±10 mA
IOUT Continuous output current(2) ±100
TJ Junction temperature 150 °C
TA Operating free-air temperature 125
TSTG Storage temperature –65 150
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Long-term continuous output current for electromigration limits.

7.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±1000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VS Total supply voltage (VS+ – VS–) 3.3 5 5.25 V

7.4 Thermal Information

THERMAL METRIC(1) OPA858 UNIT
DSG (WSON)
8 PINS
RθJA Junction-to-ambient thermal resistance 80.1 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 100 °C/W
RθJB Junction-to-board thermal resistance 45 °C/W
ψJT Junction-to-top characterization parameter 6.8 °C/W
ψJB Junction-to-board characterization parameter 45.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 22.7 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

7.5 Electrical Characteristics

VS+ = 5 V, VS– = 0 V, G = 7 V/V, RF = 453 Ω, input common-mode biased at midsupply, RL = 200 Ω, output load is referenced to midsupply, and TA = 25℃ (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT TEST LEVEL(1)
AC PERFORMANCE
SSBW Small-signal bandwidth VOUT = 100 mVPP 1.2 GHz C
LSBW Large-signal bandwidth VOUT = 2 VPP 600 MHz C
GBWP Gain-bandwidth product 5.5 GHz C
Bandwidth for 0.1-dB flatness 130 MHz C
SR Slew rate (10% - 90%) VOUT = 2-V step 2000 V/µs C
tr Rise time VOUT = 100-mV step 0.3 ns C
tf Fall time VOUT = 100-mV step 0.3 ns C
Settling time to 0.1% VOUT = 2-V step 8 ns C
Settling time to 0.001% VOUT = 2-V step 3000 ns C
Overshoot or undershoot VOUT = 2-V step 7% C
Overdrive recovery 2x output overdrive (0.1% recovery) 200 ns C
HD2 Second-order harmonic distortion f = 10 MHz, VOUT = 2 VPP 88 dBc C
f = 100 MHz, VOUT = 2 VPP 64
HD3 Third-order harmonic distortion f = 10 MHz, VOUT = 2 VPP 86 dBc C
f = 100 MHz, VOUT = 2 VPP 68
en Input-referred voltage noise f = 1 MHz 2.5 nV/√Hz C
ZOUT Closed-loop output impedance f = 1 MHz 0.15 Ω C
DC PERFORMANCE
AOL Open-loop voltage gain 72 75 dB A
VOS Input offset voltage TA = 25°C –5 ±0.8 5 mV A
ΔVOS/ΔT Input offset voltage drift TA = –40°C to +125°C ±2 µV/°C B
IBN, IBI Input bias current TA = 25°C ±0.4 5 pA A
IBOS Input offset current TA = 25°C ±0.01 5 pA A
CMRR Common-mode rejection ratio VCM = ±0.5 V, referenced to midsupply 70 90 dB A
INPUT
Common-mode input resistance 1 GΩ C
CCM Common-mode input capacitance 0.62 pF C
Differential input resistance 1 GΩ C
CDIFF Differential input capacitance 0.2 pF C
VIH Common-mode input range (high) CMRR > 66 dB, VS+ = 3.3 V 1.7 1.9 V A
VIL Common-mode input range (low) CMRR > 66 dB, VS+ = 3.3 V 0 0.4 V A
VIH Common-mode input range (high) CMRR > 66 dB 3.4 3.6 V A
TA = –40°C to +125°C, CMRR > 66 dB 3.4 B
VIL Common-mode input range (low) CMRR > 66 dB 0 0.4 V A
TA = –40°C to +125°C, CMRR > 66 dB 0.35 B
OUTPUT
VOH Output voltage (high) TA = 25°C, VS+ = 3.3 V 2.3 2.4 V A
VOH Output voltage (high) TA = 25°C 3.95 4.1 V A
TA = –40°C to +125°C 3.9 B
VOL Output voltage (low) TA = 25°C, VS+ = 3.3 V 1.05 1.15 V A
VOL Output voltage (low) TA = 25°C 1.05 1.15 V A
TA = –40°C to +125°C 1.2 B
Linear output drive (sink and source) RL = 10 Ω, AOL > 60 dB 65 80 mA A
TA = –40°C to +125°C, RL = 10 Ω,
AOL > 60 dB		 64 B
ISC Output short-circuit current 85 105 mA A
POWER SUPPLY
VS Operating voltage 3.3 5.25 V A
IQ Quiescent current VS+ = 5 V 18 20.5 24 mA A
IQ Quiescent current VS+ = 3.3 V 17.5 20 23.5 mA A
IQ Quiescent current VS+ = 5.25 V 18 21 24 mA A
IQ Quiescent current TA = 125°C 24.5 mA B
IQ Quiescent current TA = –40°C 18.5 mA B
PSRR+ Positive power-supply rejection ratio 74 84 dB A
PSRR– Negative power-supply rejection ratio 70 80
POWER DOWN
Disable voltage threshold Amplifier OFF below this voltage 0.65 1 V A
Enable voltage threshold Amplifier ON above this voltage 1.5 1.8 V A
Power-down quiescent current 70 140 µA A
PD bias current 70 200 µA A
Turnon time delay Time to VOUT = 90% of final value 13 ns C
Turnoff time delay 120 ns C
(1) Test levels (all values set by characterization and simulation): (A) 100% tested at 25°C, overtemperature limits by characterization and simulation; (B) Not tested in production, limits set by characterization and simulation; (C) Typical value only for information.

7.6 Typical Characteristics

VS+ = 2.5 V, VS– = –2.5 V, VIN+ = 0 V, RF = 453 Ω, Gain = 7 V/V, RL = 200 Ω, output load referenced to midsupply, and TA = 25°C (unless otherwise noted)
OPA858 D100_SBOS629.gif
VOUT = 100 mVPP; see Figure 43 and Figure 44 for circuit configuration
Figure 1. Small-Signal Frequency Response vs Gain
OPA858 D103_SBOS629.gif
VOUT = 100 mVPP
Figure 3. Small-Signal Frequency Response vs Output Load
OPA858 D105_SBOS629.gif
VOUT = 100 mVPP; see Figure 45 for circuit configuration
Figure 5. Small-Signal Frequency Response vs Capacitive Load
OPA858 D107_SBOS629.gif
VOUT = 2 VPP
Figure 7. Large-Signal Response for 0.1-dB Gain Flatness
OPA858 D109_SBOS629.gif
Small-Signal Response
Figure 9. Closed-Loop Output Impedance vs Frequency
OPA858 D111_SBOS629.gif
Figure 11. Voltage Noise Density vs Frequency
OPA858 D113_SBOS629.gif
Figure 13. Harmonic Distortion (HD2) vs Output Swing
OPA858 D115_SBOS629.gif
VOUT = 2 VPP
Figure 15. Harmonic Distortion (HD2) vs Output Load
OPA858 D117_SBOS629.gif
VOUT = 2 VPP
Figure 17. Harmonic Distortion (HD2) vs Gain
OPA858 D119_SBOS629.gif
Average Rise and Fall Time (10% - 90%) = 450 ps
Figure 19. Small-Signal Transient Response
OPA858 D121_SBOS629.gif
Figure 21. Small-Signal Transient Response vs Capacitive Load
OPA858 D123_SBOS629.gif
VS+ = 5 V, VS– = Ground
Figure 23. Turnon Transient Response
OPA858 D125_SBOS629.gif
Small-Signal Response
Figure 25. Common-Mode Rejection Ratio vs Frequency
OPA858 D160_SBOS629.gif
2 Typical Units
Figure 27. Quiescent Current vs Supply Voltage
OPA858 D162_SBOS629.gif
30 Units Tested
Figure 29. Quiescent Current (Amplifier Disabled) vs Ambient Temperature
OPA858 D164_SBOS629.gif
µ = 1 µV/°C σ = 2.2 µV/°C 28 Units Tested
Figure 31. Offset Voltage vs Ambient Temperature
OPA858 D166_SBOS629.gif
VS = 5 V 3 Typical Units
Figure 33. Offset Voltage vs Input Common-Mode Voltage
OPA858 D168_SBOS629.gif
VS = 3.3 V 3 Typical Units
Figure 35. Offset Voltage vs Output Swing
OPA858 D170_SBOS629.gif
Figure 37. Offset Voltage vs Output Swing vs Ambient Temperature
OPA858 D172_SBOS629.gif
Figure 39. Input Bias Current vs Input Common-Mode Voltage
OPA858 D141_SBOS629.gif
µ = –0.28 mV σ = 0.8 mV 4555 units tested
Figure 41. Offset Voltage Distribution
OPA858 D102_SBOS629.gif
VOUT = 100 mVPP
Figure 2. Small-Signal Frequency Response vs Supply Voltage
OPA858 D104_SBOS629.gif
VOUT = 100 mVPP
Figure 4. Small-Signal Frequency Response vs Ambient Temperature
OPA858 D106_SBOS629.gif
VOUT = 2 VPP
Figure 6. Large-Signal Frequency Response vs Gain
OPA858 D108_SBOS629.gif
VS = 3.3 V VOUT = 1 VPP
Figure 8. Large-Signal Frequency Response
OPA858 D500_SBOS852.gif
Small-Signal Response
Figure 10. Open-Loop Magnitude and Phase vs Frequency
OPA858 D112_SBOS629.gif
Frequency = 10 MHz
Figure 12. Voltage Noise Density vs Ambient Temperature
OPA858 D114_SBOS629.gif
Figure 14. Harmonic Distortion (HD3) vs Output Swing
OPA858 D116_SBOS629.gif
VOUT = 2 VPP
Figure 16. Harmonic Distortion (HD3) vs Output Load
OPA858 D118_SBOS629.gif
VOUT = 2 VPP
Figure 18. Harmonic Distortion (HD3) vs Gain
OPA858 D120_SBOS629.gif
Average Rise and Fall Time (10% - 90%) = 750 ps
Figure 20. Large-Signal Transient Response
OPA858 D122_SBOS629.gif
2x Output Overdrive
Figure 22. Output Overload Response
OPA858 D124_SBOS629.gif
VS+ = 5 V, VS– = Ground
Figure 24. Turnoff Transient Response
OPA858 D126_SBOS629.gif
Small-Signal Response
Figure 26. Power Supply Rejection Ratio vs Frequency
OPA858 D161_SBOS629.gif
2 Typical Units
Figure 28. Quiescent Current vs Ambient Temperature
OPA858 D163_SBOS629.gif
3 Typical Units
Figure 30. Offset Voltage vs Supply Voltage
OPA858 D165_SBOS629.gif
VS = 3.3 V 3 Typical Units
Figure 32. Offset Voltage vs Input Common-Mode Voltage
OPA858 D167_SBOS629.gif
Figure 34. Offset Voltage vs Input Common-Mode Voltage vs Ambient Temperature
OPA858 D169_SBOS629.gif
VS = 5 V 3 Typical Units
Figure 36. Offset Voltage vs Output Swing
OPA858 D171_SBOS629.gif
3 Typical Units
Figure 38. Input Bias Current vs Ambient Temperature
OPA858 D140_SBOS629.gif
µ = 20.35 mA σ = 0.2 mA 4555 units tested
Figure 40. Quiescent Current Distribution
OPA858 D142_SBOS629.gif
µ = –0.1 pA σ = 0.39 pA 4555 units tested
Figure 42. Input Bias Current Distribution

8 Parameter Measurement Information

8.1 Parameter Measurement Information

The various test setup configurations for the OPA858 are shown below

OPA858 Param_NonInv_G7.gifFigure 43. Noninverting Configuration
OPA858 Param_Inv_Gn7.gifFigure 44. Inverting Configuration (Gain = –7 V/V)
OPA858 Param_CapLoad.gifFigure 45. Capacitive Load Driver Configuration

9 Detailed Description

9.1 Overview

The ultra-wide, 5.5-GHz gain bandwidth product (GBWP) of the OPA858, combined with the broadband voltage noise of 2.5 nV/√Hz, produces a viable amplifier for wideband transimpedance applications, high-speed data acquisition systems, and applications with weak signal inputs that require low-noise and high-gain front ends. The OPA858 combines multiple features to optimize dynamic performance. In addition to the wide, small-signal bandwidth, the OPA858 has 600 MHz of large signal bandwidth (VOUT = 2 VPP) and a slew rate of 2000 V/µs.

The OPA858 is offered in a 2-mm × 2-mm, 8-pin WSON package that features a feedback (FB) pin for a simple feedback network connection between the amplifiers output and inverting input. Excess capacitance on an amplifiers input pin can reduce phase margin causing instability. This problem is exacerbated in the case of very wideband amplifiers like the OPA858. To reduce the effects of stray capacitance on the input node, the OPA858 pinout features an isolation pin (NC) between the feedback and inverting input pins that increases the physical spacing between them thereby reducing parasitic coupling at high frequencies. The OPA858 also features a very low capacitance input stage with only 0.8-pF of total input capacitance.

9.2 Functional Block Diagram

The OPA858 is a classic, voltage feedback operational amplifier (op amp) with two high-impedance inputs and a low-impedance output. Standard application circuits are supported, like the two basic options shown in Figure 46 and Figure 47. The DC operating point for each configuration is level-shifted by the reference voltage (VREF), which is typically set to midsupply in single-supply operation. VREF is typically connected to ground in split-supply applications.

OPA858 noninv_amp.gifFigure 46. Noninverting Amplifier
OPA858 inv_amp.gifFigure 47. Inverting Amplifier

9.3 Feature Description

9.3.1 Input and ESD Protection

The OPA858 is fabricated on a low-voltage, high-speed, BiCMOS process. The internal, junction breakdown voltages are low for these small geometry devices, and as a result, all device pins are protected with internal ESD protection diodes to the power supplies as Figure 48 shows. There are two antiparallel diodes between the inputs of the amplifier that clamp the inputs during an overrange or fault condition.

OPA858 fd_esd.gifFigure 48. Internal ESD Structure

9.3.2 Feedback Pin

The OPA858 pin layout is optimized to minimize parasitic inductance and capacitance, which is critical in high-speed analog design. The FB pin (pin 1) is internally connected to the output of the amplifier. The FB pin is separated from the inverting input of the amplifier (pin 3) by a no connect (NC) pin (pin 2). The NC pin must be left floating. There are two advantages to this pin layout:

  1. A feedback resistor (RF) can connect between the FB and IN– pin on the same side of the package (see Figure 49) rather than going around the package.
  2. The isolation created by the NC pin minimizes the capacitive coupling between the FB and IN– pins by increasing the physical separation between the pins.

OPA858 OPA85X_FB-Pin.gifFigure 49. RF Connection Between FB and IN– Pins

9.3.3 Wide Gain-Bandwidth Product

Figure 10 shows the open-loop magnitude and phase response of the OPA858. Calculate the gain bandwidth product of any op amp by determining the frequency at which the AOL is 60 dB and multiplying that frequency by a factor of 1000. The second pole in the AOL response occurs before the magnitude crosses 0 dB, and the resultant phase margin is less than 0°. This indicates instability at a gain of 0 dB (1 V/V). Amplifiers that are not unity-gain stable are known as decompensated amplifiers. Decompensated amplifiers typically have higher gain-bandwidth product, higher slew rate, and lower voltage noise, compared to a unity-gain stable amplifier with the same amount of quiescent power consumption.

Figure 50 shows the open-loop magnitude (AOL) of the OPA858 as a function of temperature. The results show minimal variation over temperature. The phase margin of the OPA858 configured in a noise gain of 7 V/V (16.9 dB) is close to 55° across temperature. Similarly Figure 51 shows the AOL magnitude of the OPA858 as a function of process variation. The results show the AOL curve for the nominal process corner and the variation one standard deviation from the nominal. The simulated results suggest less than 1° of phase margin difference within a standard deviation of process variation when the amplifier is configured in a gain of 7 V/V.

One of the primary applications for the OPA858 is as a high-speed transimpedance amplifier (TIA), as Figure 59 shows. The low-frequency noise gain of a TIA is 0 dB (1 V/V). At high frequencies the ratio of the total input capacitance and the feedback capacitance set the noise gain. To maximize the TIA closed-loop bandwidth, the feedback capacitance is typically smaller than the input capacitance, which implies that the high-frequency noise gain is greater than 0 dB. As a result, op amps configured as TIAs are not required to be unity-gain stable, which makes a decompensated amplifier a viable option for a TIA. What You Need To Know About Transimpedance Amplifiers – Part 1 and What You Need To Know About Transimpedance Amplifiers – Part 2 describe transimpedance amplifier compensation in greater detail.

OPA858 D204_SBOS629.gifFigure 50. Open-Loop Gain vs Temperature
OPA858 D205_SBOS629.gifFigure 51. Open-Loop Gain vs Process Variation

 
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