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  • 带集成式合成器的 LMX8410L 高性能混合器

    • ZHCSHV3A March   2018  – November 2018 LMX8410L

      PRODUCTION DATA.  

  • CONTENTS
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  • 带集成式合成器的 LMX8410L 高性能混合器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化方框图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Configurations and Feature Description
        1. 7.3.1.1 RF, LO and IF Interfaces
          1. 7.3.1.1.1 RF Interface
          2. 7.3.1.1.2 LO Interface
            1. 7.3.1.1.2.1 LO Interface as Output Port
            2. 7.3.1.1.2.2 LO Interface as Input Port
          3. 7.3.1.1.3 Baseband Interface
        2. 7.3.1.2 Device Configurations Overview
          1. 7.3.1.2.1 Initialize the Device
          2. 7.3.1.2.2 Configure LO Modes
          3. 7.3.1.2.3 Set Up External LO Clock
          4. 7.3.1.2.4 Perform DCOC (DC Offset Correction)
          5. 7.3.1.2.5 Turn Off SM Clock
          6. 7.3.1.2.6 Perform IMRR (Image Rejection Ratio) Calibration
        3. 7.3.1.3 State Machine Clock
          1. 7.3.1.3.1 Set Divider Values For Internal LO Mode
          2. 7.3.1.3.2 Set Divider Values For External LO Mode
        4. 7.3.1.4 DCOC (DC Offset Correction)
          1. 7.3.1.4.1 RF Input Power Restriction During DCOC
          2. 7.3.1.4.2 Set Up DCOC Clock Divider
        5. 7.3.1.5 Image Rejection Calibration
          1. 7.3.1.5.1 Phase Calibration
          2. 7.3.1.5.2 Gain Calibration
        6. 7.3.1.6 IF Amplifier Common Mode Configurations
        7. 7.3.1.7 Synchronization Mode (Internal LO Mode Only)
          1. 7.3.1.7.1 Synchronization of the LO_OUT Output to the Fosc Input
          2. 7.3.1.7.2 Synchronization of I/Q Outputs to Fosc Inputs Using Internal LO
    4. 7.4 Device Functional Modes
      1. 7.4.1 Internal LO Mode
        1. 7.4.1.1 VCO Range Uncertainty for 7.5 to 7.7 GHz
      2. 7.4.2 External LO Mode
    5. 7.5 Programming
      1. 7.5.1 General Comments Regarding Programming
      2. 7.5.2 Recommended Initial Power Up Sequence
      3. 7.5.3 Recommended and Power on Reset Bit Values
    6. 7.6 Register Map
      1. 7.6.1  R0 Register (Address = 0x0) [reset = X]
        1. Table 9. R0 Register Field Descriptions
      2. 7.6.2  R1 Register (Address = 0x1) [reset = 0x3]
        1. Table 10. R1 Register Field Descriptions
      3. 7.6.3  R2 Register (Address = 0x2) [reset = X]
        1. Table 11. R2 Register Field Descriptions
      4. 7.6.4  R9 Register (Address = 0x9) [reset = X]
        1. Table 12. R9 Register Field Descriptions
      5. 7.6.5  R10 Register (Address = 0xA) [reset = 0x80]
        1. Table 13. R10 Register Field Descriptions
      6. 7.6.6  R11 Register (Address = 0xB) [reset = 0x10]
        1. Table 14. R11 Register Field Descriptions
      7. 7.6.7  R14 Register (Address = 0xE) [reset = 0x70]
        1. Table 15. R14 Register Field Descriptions
      8. 7.6.8  R36 Register (Address = 0x24) [reset = 0x64]
        1. Table 16. R36 Register Field Descriptions
      9. 7.6.9  R37 Register (Address = 0x25) [reset = 0x200]
        1. Table 17. R37 Register Field Descriptions
      10. 7.6.10 R38 Register (Address = 0x26) [reset = 0x0]
        1. Table 18. R38 Register Field Descriptions
      11. 7.6.11 R39 Register (Address = 0x27) [reset = 0x2710]
        1. Table 19. R39 Register Field Descriptions
      12. 7.6.12 R40 Register (Address = 0x28) [reset = 0x0]
        1. Table 20. R40 Register Field Descriptions
      13. 7.6.13 R41 Register (Address = 0x29) [reset = 0x0]
        1. Table 21. R41 Register Field Descriptions
      14. 7.6.14 R42 Register (Address = 0x2A) [reset = 0x0]
        1. Table 22. R42 Register Field Descriptions
      15. 7.6.15 R43 Register (Address = 0x2B) [reset = 0x0]
        1. Table 23. R43 Register Field Descriptions
      16. 7.6.16 R44 Register (Address = 0x2C) [reset = 0xA2]
        1. Table 24. R44 Register Field Descriptions
      17. 7.6.17 R46 Register (Address = 0x2E) [reset = 0x1]
        1. Table 25. R46 Register Field Descriptions
      18. 7.6.18 R58 Register (Address = 0x3A) [reset = 0x8000]
        1. Table 26. R58 Register Field Descriptions
      19. 7.6.19 R59 Register (Address = 0x3B) [reset = 0x1]
        1. Table 27. R59 Register Field Descriptions
      20. 7.6.20 R69 Register (Address = 0x45) [reset = 0x0]
        1. Table 28. R69 Register Field Descriptions
      21. 7.6.21 R70 Register (Address = 0x46) [reset = 0xC350]
        1. Table 29. R70 Register Field Descriptions
      22. 7.6.22 R75 Register (Address = 0x4B) [reset = 0x0]
        1. Table 30. R75 Register Field Descriptions
      23. 7.6.23 R78 Register (Address = 0x4E) [reset = 0x0]
        1. Table 31. R78 Register Field Descriptions
      24. 7.6.24 R79 Register (Address = 0x4F) [reset = 0x7000]
        1. Table 32. R79 Register Field Descriptions
      25. 7.6.25 R80 Register (Address = 0x50) [reset = 0xA]
        1. Table 33. R80 Register Field Descriptions
      26. 7.6.26 R81 Register (Address = 0x51) [reset = 0x0]
        1. Table 34. R81 Register Field Descriptions
      27. 7.6.27 R82 Register (Address = 0x52) [reset = 0x23]
        1. Table 35. R82 Register Field Descriptions
      28. 7.6.28 R83 Register (Address = 0x53) [reset = 0x2000]
        1. Table 36. R83 Register Field Descriptions
      29. 7.6.29 R84 Register (Address = 0x54) [reset = 0x1900]
        1. Table 37. R84 Register Field Descriptions
      30. 7.6.30 R88 Register (Address = 0x58) [reset = 0x0]
        1. Table 38. R88 Register Field Descriptions
      31. 7.6.31 R94 Register (Address = 0x5E) [reset = 0x8080]
        1. Table 39. R94 Register Field Descriptions
      32. 7.6.32 R95 Register (Address = 0x5F) [reset = X]
        1. Table 40. R95 Register Field Descriptions
      33. 7.6.33 R103 Register (Address = 0x67) [reset = X]
        1. Table 41. R103 Register Field Descriptions
      34. 7.6.34 R110 Register (Address = 0x6E) [reset = X]
        1. Table 42. R110 Register Field Descriptions
      35. 7.6.35 R111 Register (Address = 0x6F) [reset = 0x0]
        1. Table 43. R111 Register Field Descriptions
      36. 7.6.36 R112 Register (Address = 0x70) [reset = 0x0]
        1. Table 44. R112 Register Field Descriptions
      37. 7.6.37 R121 Register (Address = 0x79) [reset = 0x0]
        1. Table 45. R121 Register Field Descriptions
      38. 7.6.38 R123 Register (Address = 0x7B) [reset = 0x3]
        1. Table 46. R123 Register Field Descriptions
      39. 7.6.39 R126 Register (Address = 0x7E) [reset = X]
        1. Table 47. R126 Register Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
      1. 10.1.1 High Frequency Trace Routing
      2. 10.1.2 Power Trace Routing
    2. 10.2 Layout Examples
  11. 11器件和文档支持
    1. 11.1 文档支持
      1. 11.1.1 相关文档
    2. 11.2 接收文档更新通知
    3. 11.3 社区资源
    4. 11.4 商标
    5. 11.5 静电放电警告
    6. 11.6 术语表
  12. 12机械、封装和可订购信息
  13. 重要声明
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DATA SHEET

带集成式合成器的 LMX8410L 高性能混合器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 宽带射频输入：4 至 10GHz
  • 大型中频带宽：直流至 1350MHz
  • 输入 IP3：5GHz 射频输入时为 28dBm
  • 噪声系数：5GHz 射频输入时为 15dB
  • 高电压转换增益：5GHz 射频输入时为 11dB
  • 集成宽带射频输入平衡-非平衡变压器
  • 自动离线直流失调电压校正为 ±2mV
  • 可编程 IMRR 校准
  • 针对多个器件的同步功能
  • 高性能集成 LO 合成器：5GHz 载波条件下具有 56.5dBc 的 DSB 集成噪声
  • 外部 LO 模式：可旁路绕开集成 LO 合成器；支持外部 LO 注入
  • 集成低噪声 LDO
  • 7mm × 7mm 48 引脚 QFN 封装

2 应用

  • 测试和测量设备
  • 无线基础设施
  • 相控阵雷达
  • 微波回程
  • 卫星通信
  • 软件定义无线电

3 说明

LMX8410L 是一款具有集成 LO 和 IF 放大器的高性能宽带（射频输入为 4 至 10GHz）I/Q 解调器。在 IIP3 为 28dBm 而 NF 为 15dB（频率均为 5GHz）的情况下，该器件可提供出色的动态范围，适用于高性能 应用中使用 DP83869。该器件可提供 2.7GHz 的大型复杂带宽，适用于高数据速率 应用。

LMX8410L 提供自动直流失调电压校正算法，可将失调电压降至 ±2mV 以下。使用 SPI 接口可以精确控制 I 和 Q 通道的增益和相位，从而实现高镜像抑制。

LMX8410L 具有高度集成度，可提供高性能，同时还能节省布板空间并降低复杂性。它集成了宽带射频输入平衡-非平衡变压器，因此无需外部平衡-非平衡变压器。它集成了高性能 PLL 和 VCO，因此无需外部 LO 和 LO 驱动器。该器件还集成了一个 IF 放大器和几个低噪声 LDO，进一步简化了电路板。

LMX8410L 集成了一个极低噪声的合成器，PLL FOM 为 –236dBc/Hz，在 5GHz 载波条件下提供高达 56.5dBc 的 DSB 集成噪声。LO 允许跨多个器件进行相位同步。高性能合成器输出可用于驱动另一级或数据转换器。对于共享外部 LO 的 应用 ，可以旁路掉集成的 LO。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
LMX8410L VQFN (48) 7.00mm × 7.00mm
  1. 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品附录。

Device Images

简化方框图

LMX8410L fbd_snas730.gif

4 修订历史记录

Changes from * Revision (March 2018) to A Revision

  • 首次发布生产数据产品说明书 Go
  • Changed many numbers in electrical specifications table. Go
  • Added typical performance characteristics section. Go
  • Changed and added significant details in detailed descriptions sections. Added sections, changed several portions of the register map.Go

5 Pin Configuration and Functions

RGZ Package
48-Pin QFN
Top View
LMX8410L po_snas730.gif

Pin Functions

PIN I/O DESCRIPTION
NAME NAME
1 CE Input Chip Enable input. Active HIGH powers on the device. 1.8V to 3.3V logic.
2 VBIAS_VCO2 Bypass VCO bias. Requires connecting 10-µF capacitor to VCO ground. Place close to pin. If using external LO, this pin should either be floated or configured the same way as internal LO mode.
3 VBIAS_VCO1 Bypass VCO bias. Requires connecting 10-µF capacitor to VCO ground. Place close to pin. If using external LO, this pin should either be floated or configured the same way as internal LO mode.
4 GND Ground VCO ground. VBIAS pin capacitors must bypass to this point.
5 SYNC Input Trigger pin for synchronizing multiple devices. If using external LO, tie this pin to GND.
6 GND Ground Digital ground. VCC_DIG bypass capacitors must bypass to this point.
7 VCC_DIG Supply Digital supply. TI recommends connecting 0.1-µF capacitor to digital ground.
8 OSCINP Input Reference input clock (+). High input impedance. Requires connecting series capacitor (0.1 µF recommended). If using external LO, tie this pin to GND.
9 OSCINM Input Reference input clock (–). High input impedance. Requires connecting series capacitor (0.1 µF recommended). If using external LO, tie this pin to GND.
10 VREG_OSCIN Bypass Internal LDO output. Requires connecting 1-µF capacitor to digital ground. Place close to pin. If using external LO, this pin should either be floated or configured the same way as internal LO mode.
11 MUXOUT Output Readback or lock detect output. Pin mode configured by internal register settings.
12 VCC_CP Supply Charge pump supply. TI recommends connecting 0.1 µF and 100 pF to charge pump ground. Place close to pin. This pin must be connected to VCC, even if using external LO.
13 CP Output Charge pump output. TI recommends connecting C1 of loop filter close to pin. If using external LO, this pin should either be floated or configured the same way as internal LO mode.
14 GND Ground Charge pump ground. VCC_CP bypass capacitors must bypass to this point.
15 GND Ground MASH engine ground. VCC_MASH bypass capacitors must bypass to this point.
16 VCC_MASH Supply MASH engine supply. TI recommends connecting 0.1 µF and 100 pF to MASH engine ground. Place close to pin. This pin must be connected to VCC, even if using external LO.
17 LO_M Input/Output Internal LO differential output (–) or external LO differential input (–). In differential output mode, requires connecting 50-Ω resistor pullup to VCC as close as possible to pin. In differential input mode, remove the pull up resistors or inductors. The input should be capacitively coupled with internal biasing. See LO Interface for more information.
18 LO_P Input/Output Internal LO differential output (+) or external LO differential input (+). In differential output mode, requires connecting 50-Ω resistor pullup to VCC as close as possible to pin. In differential input mode, remove the pull up resistors or inductors. The input should be capacitively coupled with internal biasing. See LO Interface for more information.
19 VCC_BUF Supply LO buffer supply. TI recommends connecting 0.1 µF and 100 pF to VCO ground. This pin must be connected to VCC, even if using external LO.
20 GND Ground IF amplifier Q-channel ground. Q-channel VCC5 bypass capacitors must bypass to this point.
21 IF_QM Output IF amplifier Q-channel differential output (–). TI recommends connecting series 50-Ω resistor close to pin.
22 IF_QP Output IF amplifier Q-channel differential output (+). TI recommends connecting series 50-Ω resistor close to pin.
23 VCC5_IFQ Supply IF amplifier Q-channel 5-V supply. TI recommends connecting 0.1 µF and 100 pF to IF amplifier Q-channel ground. Place close to pin.
24 SCK Input SPI clock signal. High impedance CMOS input. 1.8-V to 3.3-V logic.
25 SDI Input SPI data signal. High impedance CMOS input. 1.8-V to 3.3-V logic.
26 CSB Input SPI chip select signal. High impedance CMOS input. 1.8-V to 3.3-V logic.
27 VCC_IFQ Supply IF mixer Q-channel supply. TI recommends connecting 0.1 µF and 100 pF to digital ground.
28 NC N/A No connect. Pin is not internally connected and may be floated or shorted to other nodes.
29 VCC_RFQ Supply RF Q-channel supply. TI recommends connecting 0.1 µF and 100 pF to digital ground.
32 GND Ground RF input path ground.
31 RF Input RF input. Single-ended. Must be AC coupled.
32 GND Ground RF input path ground.
33 VCC_RFI Supply RF I-channel supply. TI recommends connecting 0.1 µF and 100 pF to digital ground.
34 GND Ground Should be connected IF ground.
35 VCC_IFI Supply IF mixer I-channel supply. TI recommends connecting 0.1 µF and 100 pF to digital ground.
36 VCM_IN Input Common-mode voltage input. When the VCM_CONFIG register is set to external (0xF), the voltage on this pin sets the common-mode voltage of the IF amplifiers.
37 NC Ground Connect this pin to IF ground.
38 VCC5_IFI Supply IF amplifier I-channel 5-V supply. TI recommends connecting 0.1 µF and 100 pF to IF amplifier I-channel ground. Place close to pin.
39 IF_IP Output IF amplifier I-channel differential output (+). TI recommends connecting series 50-Ω resistor close to pin.
40 IF_IM Output IF amplifier I-channel differential output (–). TI recommends connecting series 50-Ω resistor close to pin.
41 GND Ground IF amplifier I-channel ground. I-channel VCC5 bypass capacitors should bypass to this point.
42 VBIAS_VARAC Bypass VCO varactor bias. Requires connecting 10µF capacitor to VCO ground. If using external LO, this pin should either be floated or configured the same way as internal LO mode.
43 GND Ground VCO ground. Varactor bias bypass capacitor should bypass to this point.
44 VTUNE Input VCO tuning voltage input. If using internal LO, connect the output of the loop filter to this point. If using external LO, tie this pin to GND.
45 VREG_VCO Bypass VCO LDO output node. Requires connecting 10-µF capacitor to VCO ground. Place close to pin. This capacitor must be present even if used in external LO mode.
46 VCC_VCO Supply VCO supply. TI recommends connecting 0.1-µF and 100-pF capacitors to VCO ground. This pin must be connected to VCC, even if using external LO.
47 VREF_VCO Bypass VCO LDO reference node. Requires connecting 1-µF capacitor to VCO ground. If using external LO, this pin should either be floated or configured the same way as internal LO mode.
48 GND Ground VCO ground. VCO LDO, LDO reference, and supply bypass capacitors must bypass to this point.
49 PAD Ground Die attach pad. Internally connected to ground. TI recommends shorting ground pins to this pad on the same plane, if possible.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Power supply voltage, 3.3-V rail –0.3 3.6 V
VCC5 Power supply voltage, 5-V rail –0.3 5.3 V
PD Power dissipation 5 W
TJ Junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins 2500 V
Charged device model (CDM), per JEDEC specificationJESD22-C101, all pins 500

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Power supply voltage, 3.3V rail 3.15 3.3 3.45 V
VCC5 Power supply voltage, 5V rail 4.75 5 5.25 V
TA Ambient temperature –40 25 85 °C
TJ Junction temperature 125 °C

 
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