带集成式合成器的 LMX8410L 高性能混合器
- ZHCSHV3A March 2018 – November 2018 LMX8410L
  
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带集成式合成器的 LMX8410L 高性能混合器

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

宽带射频输入：4 至 10GHz
大型中频带宽：直流至 1350MHz
输入 IP3：5GHz 射频输入时为 28dBm
噪声系数：5GHz 射频输入时为 15dB
高电压转换增益：5GHz 射频输入时为 11dB
集成宽带射频输入平衡-非平衡变压器
自动离线直流失调电压校正为 ±2mV
可编程 IMRR 校准
针对多个器件的同步功能
高性能集成 LO 合成器：5GHz 载波条件下具有 56.5dBc 的 DSB 集成噪声
外部 LO 模式：可旁路绕开集成 LO 合成器；支持外部 LO 注入
集成低噪声 LDO
7mm × 7mm 48 引脚 QFN 封装

2 应用

测试和测量设备
无线基础设施
相控阵雷达
微波回程
卫星通信
软件定义无线电

3 说明

LMX8410L 是一款具有集成 LO 和 IF 放大器的高性能宽带（射频输入为 4 至 10GHz）I/Q 解调器。在 IIP3 为 28dBm 而 NF 为 15dB（频率均为 5GHz）的情况下，该器件可提供出色的动态范围，适用于高性能应用中使用 DP83869。该器件可提供 2.7GHz 的大型复杂带宽，适用于高数据速率应用。

LMX8410L 提供自动直流失调电压校正算法，可将失调电压降至 ±2mV 以下。使用 SPI 接口可以精确控制 I 和 Q 通道的增益和相位，从而实现高镜像抑制。

LMX8410L 具有高度集成度，可提供高性能，同时还能节省布板空间并降低复杂性。它集成了宽带射频输入平衡-非平衡变压器，因此无需外部平衡-非平衡变压器。它集成了高性能 PLL 和 VCO，因此无需外部 LO 和 LO 驱动器。该器件还集成了一个 IF 放大器和几个低噪声 LDO，进一步简化了电路板。

LMX8410L 集成了一个极低噪声的合成器，PLL FOM 为 –236dBc/Hz，在 5GHz 载波条件下提供高达 56.5dBc 的 DSB 集成噪声。LO 允许跨多个器件进行相位同步。高性能合成器输出可用于驱动另一级或数据转换器。对于共享外部 LO 的应用，可以旁路掉集成的 LO。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
LMX8410L	VQFN (48)	7.00mm × 7.00mm

如需了解所有可用封装，请参阅产品说明书末尾的可订购产品附录。

Device Images

简化方框图

4 修订历史记录

Changes from * Revision (March 2018) to A Revision

首次发布生产数据产品说明书 Go
Changed many numbers in electrical specifications table. Go
Added typical performance characteristics section. Go
Changed and added significant details in detailed descriptions sections. Added sections, changed several portions of the register map.Go

5 Pin Configuration and Functions

RGZ Package

48-Pin QFN

Top View

Pin Functions

PIN		I/O	DESCRIPTION
NAME	NAME	I/O	DESCRIPTION
1	CE	Input	Chip Enable input. Active HIGH powers on the device. 1.8V to 3.3V logic.
2	VBIAS_VCO2	Bypass	VCO bias. Requires connecting 10-µF capacitor to VCO ground. Place close to pin. If using external LO, this pin should either be floated or configured the same way as internal LO mode.
3	VBIAS_VCO1	Bypass	VCO bias. Requires connecting 10-µF capacitor to VCO ground. Place close to pin. If using external LO, this pin should either be floated or configured the same way as internal LO mode.
4	GND	Ground	VCO ground. VBIAS pin capacitors must bypass to this point.
5	SYNC	Input	Trigger pin for synchronizing multiple devices. If using external LO, tie this pin to GND.
6	GND	Ground	Digital ground. VCC_DIG bypass capacitors must bypass to this point.
7	VCC_DIG	Supply	Digital supply. TI recommends connecting 0.1-µF capacitor to digital ground.
8	OSCINP	Input	Reference input clock (+). High input impedance. Requires connecting series capacitor (0.1 µF recommended). If using external LO, tie this pin to GND.
9	OSCINM	Input	Reference input clock (–). High input impedance. Requires connecting series capacitor (0.1 µF recommended). If using external LO, tie this pin to GND.
10	VREG_OSCIN	Bypass	Internal LDO output. Requires connecting 1-µF capacitor to digital ground. Place close to pin. If using external LO, this pin should either be floated or configured the same way as internal LO mode.
11	MUXOUT	Output	Readback or lock detect output. Pin mode configured by internal register settings.
12	VCC_CP	Supply	Charge pump supply. TI recommends connecting 0.1 µF and 100 pF to charge pump ground. Place close to pin. This pin must be connected to VCC, even if using external LO.
13	CP	Output	Charge pump output. TI recommends connecting C1 of loop filter close to pin. If using external LO, this pin should either be floated or configured the same way as internal LO mode.
14	GND	Ground	Charge pump ground. VCC_CP bypass capacitors must bypass to this point.
15	GND	Ground	MASH engine ground. VCC_MASH bypass capacitors must bypass to this point.
16	VCC_MASH	Supply	MASH engine supply. TI recommends connecting 0.1 µF and 100 pF to MASH engine ground. Place close to pin. This pin must be connected to VCC, even if using external LO.
17	LO_M	Input/Output	Internal LO differential output (–) or external LO differential input (–). In differential output mode, requires connecting 50-Ω resistor pullup to V_CC as close as possible to pin. In differential input mode, remove the pull up resistors or inductors. The input should be capacitively coupled with internal biasing. See LO Interface for more information.
18	LO_P	Input/Output	Internal LO differential output (+) or external LO differential input (+). In differential output mode, requires connecting 50-Ω resistor pullup to V_CC as close as possible to pin. In differential input mode, remove the pull up resistors or inductors. The input should be capacitively coupled with internal biasing. See LO Interface for more information.
19	VCC_BUF	Supply	LO buffer supply. TI recommends connecting 0.1 µF and 100 pF to VCO ground. This pin must be connected to VCC, even if using external LO.
20	GND	Ground	IF amplifier Q-channel ground. Q-channel VCC5 bypass capacitors must bypass to this point.
21	IF_QM	Output	IF amplifier Q-channel differential output (–). TI recommends connecting series 50-Ω resistor close to pin.
22	IF_QP	Output	IF amplifier Q-channel differential output (+). TI recommends connecting series 50-Ω resistor close to pin.
23	VCC5_IFQ	Supply	IF amplifier Q-channel 5-V supply. TI recommends connecting 0.1 µF and 100 pF to IF amplifier Q-channel ground. Place close to pin.
24	SCK	Input	SPI clock signal. High impedance CMOS input. 1.8-V to 3.3-V logic.
25	SDI	Input	SPI data signal. High impedance CMOS input. 1.8-V to 3.3-V logic.
26	CSB	Input	SPI chip select signal. High impedance CMOS input. 1.8-V to 3.3-V logic.
27	VCC_IFQ	Supply	IF mixer Q-channel supply. TI recommends connecting 0.1 µF and 100 pF to digital ground.
28	NC	N/A	No connect. Pin is not internally connected and may be floated or shorted to other nodes.
29	VCC_RFQ	Supply	RF Q-channel supply. TI recommends connecting 0.1 µF and 100 pF to digital ground.
32	GND	Ground	RF input path ground.
31	RF	Input	RF input. Single-ended. Must be AC coupled.
32	GND	Ground	RF input path ground.
33	VCC_RFI	Supply	RF I-channel supply. TI recommends connecting 0.1 µF and 100 pF to digital ground.
34	GND	Ground	Should be connected IF ground.
35	VCC_IFI	Supply	IF mixer I-channel supply. TI recommends connecting 0.1 µF and 100 pF to digital ground.
36	VCM_IN	Input	Common-mode voltage input. When the VCM_CONFIG register is set to external (0xF), the voltage on this pin sets the common-mode voltage of the IF amplifiers.
37	NC	Ground	Connect this pin to IF ground.
38	VCC5_IFI	Supply	IF amplifier I-channel 5-V supply. TI recommends connecting 0.1 µF and 100 pF to IF amplifier I-channel ground. Place close to pin.
39	IF_IP	Output	IF amplifier I-channel differential output (+). TI recommends connecting series 50-Ω resistor close to pin.
40	IF_IM	Output	IF amplifier I-channel differential output (–). TI recommends connecting series 50-Ω resistor close to pin.
41	GND	Ground	IF amplifier I-channel ground. I-channel VCC5 bypass capacitors should bypass to this point.
42	VBIAS_VARAC	Bypass	VCO varactor bias. Requires connecting 10µF capacitor to VCO ground. If using external LO, this pin should either be floated or configured the same way as internal LO mode.
43	GND	Ground	VCO ground. Varactor bias bypass capacitor should bypass to this point.
44	VTUNE	Input	VCO tuning voltage input. If using internal LO, connect the output of the loop filter to this point. If using external LO, tie this pin to GND.
45	VREG_VCO	Bypass	VCO LDO output node. Requires connecting 10-µF capacitor to VCO ground. Place close to pin. This capacitor must be present even if used in external LO mode.
46	VCC_VCO	Supply	VCO supply. TI recommends connecting 0.1-µF and 100-pF capacitors to VCO ground. This pin must be connected to VCC, even if using external LO.
47	VREF_VCO	Bypass	VCO LDO reference node. Requires connecting 1-µF capacitor to VCO ground. If using external LO, this pin should either be floated or configured the same way as internal LO mode.
48	GND	Ground	VCO ground. VCO LDO, LDO reference, and supply bypass capacitors must bypass to this point.
49	PAD	Ground	Die attach pad. Internally connected to ground. TI recommends shorting ground pins to this pad on the same plane, if possible.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

		MIN	MAX	UNIT
V_CC	Power supply voltage, 3.3-V rail	–0.3	3.6	V
V_CC5	Power supply voltage, 5-V rail	–0.3	5.3	V
P_D	Power dissipation		5	W
T_J	Junction temperature	–40	150	°C
T_stg	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Rating may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Condition. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins	2500	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specificationJESD22-C101, all pins	500	V

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_CC	Power supply voltage, 3.3V rail	3.15	3.3	3.45	V
V_CC5	Power supply voltage, 5V rail	4.75	5	5.25	V
T_A	Ambient temperature	–40	25	85	°C
T_J	Junction temperature			125	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾⁽²⁾		LMX8410L	UNIT
		RGZ (VQFN)
		48 PINS
R_θJA	Junction-to-ambient thermal resistance	21.9	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	9.4	°C/W
R_θJB	Junction-to-board thermal resistance	5.6	°C/W
Ψ_JT	Junction-to-top characterization parameter	0.1	°C/W
Ψ_JB	Junction-to-board characterization parameter	5.6	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.4	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

(2) Thermal model based on JEDEC standard coupon, 50.8 mm × 50.8 mm × 1.6 mm, six-layer Cu, 0.5 oz top layer, 2 oz else. 6 × 6 thermal vias in DAP, 0.2 mm diameter.

6.5 Electrical Characteristics

Measurements are done at 25 degree C. Parameters are measured at IF = 65MHz with high side injection, unless otherwise noted. Measurements are done with external VCM = 1.7V.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
POWER SUPPLY
V_CC	Power supply voltage, 3.3-V rail		3.15	3.3	3.45	V
I_CC	Power supply current, 3.3-V rail	Internal LO		650		mA
I_CC	Power supply current, 3.3-V rail	External LO		330		mA
V_CC5	Power supply voltage, 5-V rail		4.75	5	5.25	V
I_CC5	Power supply current both channels I and Q, 5-V rail			130		mA
FREQUENCY RANGES
F_RF	RF port frequency range		4000		10000	MHz
F_LO	LO port frequency range		4000		10000	MHz
F_IF	IF port frequency range (3dB bandwidth)		DC		1350	MHz
DYNAMIC PERFORMANCE
NF	Noise figure	RF = 4 GHz		15		dB
		RF = 5 GHz		15
		RF = 6 GHz		16
		RF = 7 GHz		17
		RF = 8 GHz		18
		RF = 9 GHz		19
		RF = 10 GHz		19
G	Voltage gain⁽¹⁾	RF = 4 GHz		11		dB
		RF = 5 GHz		11
		RF = 6 GHz		10.5
		RF = 7 GHz		9.5
		RF = 8 GHz		9
		RF = 9 GHz		8
		RF = 10 GHz		7
IIP3	Input intercept point, 3rd order⁽²⁾	RF = 4 GHz		28		dBm
		RF = 5 GHz		28
		RF = 6 GHz		26.5
		RF = 7 GHz		27
		RF = 8 GHz		26.5
		RF = 9 GHz		27
		RF = 10 GHz		27
IIP2	Input intercept point, 2nd order (uncalibrated)	RF = 4 GHz		48		dBm
		RF = 5 GHz		48
		RF = 6 GHz		46
		RF = 7 GHz		44
		RF = 8 GHz		45
		RF = 9 GHz		44
		RF = 10 GHz		42
SP_2x2	2×2 spur [RF input power at –10 dBm]	RF = 4 GHz		-58		dBc
		RF = 5 GHz		-58
		RF = 6 GHz		-58
		RF = 7 GHz		-54
		RF = 8 GHz		-52
		RF = 9 GHz		-50
		RF = 10 GHz		-48
SP_3x3	3×3 spur [RF input power at –10 dBm]	RF = 4 GHz		-75		dBc
		RF = 5 GHz		-75
		RF = 6 GHz		-75
		RF = 7 GHz		-75
		RF = 8 GHz		-75
		RF = 9 GHz		-75
		RF = 10 GHz		-75
O_P1dB	Output 1-dB compression point	RF = 4 GHz		12		dBm
		RF = 5 GHz		12
		RF = 6 GHz		12
		RF = 7 GHz		12
		RF = 8 GHz		12
		RF = 9 GHz		12
		RF = 10 GHz		12
IRR	Image rejection ratio [calibrated]	RF = 4 GHz		43		dB
		RF = 5 GHz		43
		RF = 6 GHz		44
		RF = 7 GHz		44
		RF = 8 GHz		43
		RF = 9 GHz		42
		RF = 10 GHz		36
ISO_RFxIF	RF to IF isolation	RF = 4 GHz		40		dB
		RF = 5 GHz		40
		RF = 6 GHz		40
		RF = 7 GHz		40
		RF = 8 GHz		40
		RF = 9 GHz		40
		RF = 10 GHz		40
LEAK_RFxIF	LO to IF leakage	LO = 4 GHz		-35		dBm
		LO = 5 GHz		-35
		LO = 6 GHz		-35
		LO = 7 GHz		-35
		LO = 8 GHz		-35
		LO = 9 GHz		-35
		LO = 10 GHz		-35
LEAK_LOxRF	LO to RF leakage (internal Lo mode)	LO = 4 GHz		-60		dBm
		LO = 5 GHz		-60
		LO = 6 GHz		-52
		LO = 7 GHz		-50
		LO = 8 GHz		-50
		LO = 9 GHz		-45
		LO = 10 GHz		–40
PERFORMANCE TUNING
G_{IQ_CAL}	I/Q gain calibration range	IMRR_GCAL register full range		±0.5		dB
G_{IQ_STEP}	I/Q gain calibration step size			0.05		dB
PH_{IQ_CAL}	I/Q phase calibration range	IMRR_PCAL register full range		±20		Deg
PH_{IQ_STEP}	I/Q phase calibration step size	Step size can be made reduced to 0.25 deg in fine accuracy mode		0.45		Deg
V_DCOC	calibrated differential DC offset			+/- 2		mV
PORTS
S11_RF	RF return loss	RF = 4 GHz		8		dB
		RF = 5 GHz		19		dB
		RF = 6 GHz		21		dB
		RF = 7 GHz		16		dB
		RF = 8 GHz		10		dB
		RF = 9 GHz		9		dB
		RF = 10 GHz		9		dB
S11_LO	LO return loss (differential measurement)	RF = 4 GHz		15		dB
		RF = 5 GHz		15		dB
		RF = 6 GHz		20		dB
		RF = 7 GHz		17		dB
		RF = 8 GHz		18		dB
		RF = 9 GHz		17		dB
		RF = 10 GHz		12		dB
P_{LO_IN}	External LO input power	8 GHz RF_IN		6		dBm
P_{LO_OUT}	External LO output power⁽³⁾	<7 GHz RFout		2		dBm
P_{LO_OUT}	External LO output power⁽³⁾	<10 GHz RFout		-1		dBm
V_{IF_RANGE}	IF output voltage swing (differential)			2		VPP
V_CM	IF common mode voltage, internal or external source		1.2	1.7	2	V
Pin_RF	RF input power				5	dBm
LO SYNTHESIZER INPUT SIGNAL PATH
F_OSCIN	Reference oscillator port frequency range	OSC_2X = 0	5		1400	MHz
F_OSCIN	Reference oscillator port frequency range	OSC_2X = 1	5		200	MHz
V_OSCIN	Reference input voltage	AC-coupled required⁽⁴⁾	0.2		2	Vpp
F_MULT	Multiplier frequency (when multiplier enabled)	Input range	30		70	MHz
F_MULT	Multiplier frequency (when multiplier enabled)	Output range	180		250	MHz
LO SYNTHESIZER PHASE DETECTOR AND CHARGE PUMP
F_PD	Phase detector frequency	Integer Mode (FRAC_ORDER = 0)	0.125		400	MHz
		Fractional Mode (FRAC_ORDER = 1,2,3)	5		300
		Fractional Mode (FRAC_ORDER = 4)	5		240
I_CPOUT	Charge pump leakage current	CPG = 0		15		nA
	Effective charge pump current (sum of up and down currents)	CPG = 4		3		mA
		CPG = 1		6
		CPG = 5		9
		CPG = 3		12
		CPG = 7		15
PN_1/F	Normalized PLL flicker noise	F_PD = 100 MHz, F_VCO = 12 GHz⁽⁵⁾		–129		dBc/Hz
PN_FLAT	Normalized PLL thermal noise floor	F_PD = 100 MHz, F_VCO = 12 GHz⁽⁵⁾		–236		dBc/Hz
LO SYNTHESIZER VCO
PNvco	Open loop VCO phase noise	8 GHz VCO, 10 kHz offset		–80		dBc/Hz
		8 GHz VCO, 100 kHz offset		–107
		8 GHz VCO, 1 MHz offset		–128
		8 GHz VCO, 10 MHz offset		–148
		8 GHz VCO, 90 MHz offset		–157
		9.2 GHz VCO, 10 kHz offset		–79
		9.2 GHz VCO, 100 kHz offset		–105
		9.2 GHz VCO, 1 MHz offset		–127
		9.2 GHz VCO, 10 MHz offset		–147
		9.2 GHz VCO, 90 MHz offset		–157
		10.3 GHz VCO, 10 kHz offset		–77
		10.3 GHz VCO, 100 kHz offset		–104
		10.3 GHz VCO, 1 MHz offset		–126
		10.3 GHz VCO, 10 MHz offset		–147
		10.3 GHz VCO, 90 MHz offset		–157
		11.3 GHz VCO, 10 kHz offset		–76
		11.3 GHz VCO, 100 kHz offset		–103
		11.3 GHz VCO, 1 MHz offset		–125
		11.3 GHz VCO, 10 MHz offset		–145
		11.3 GHz VCO, 90 MHz offset		–158
		12.5 GHz VCO, 10 kHz offset		–74
		12.5 GHz VCO, 100 kHz offset		–100
		12.5 GHz VCO, 1 MHz offset		–123
		12.5 GHz VCO, 10 MHz offset		–144
		12.5 GHz VCO, 90 MHz offset		–157
		13.3 GHz VCO, 10 kHz offset		–73
		13.3 GHz VCO, 100 kHz offset		–100
		13.3 GHz VCO, 1 MHz offset		–122
		13.3 GHz VCO, 10 MHz offset		–143
		13.3 GHz VCO, 90 MHz offset		–155
		14.5 GHz VCO, 10 kHz offset		–73
		14.5 GHz VCO, 100 kHz offset		–99
		14.5 GHz VCO, 1 MHz offset		–121
		14.5 GHz VCO, 10 MHz offset		–143
		14.5 GHz VCO, 90 MHz offset		–152
t_{VCO_CAL}	VCO calibration speed, switch across the entire frequency band, F_OSC = 200 MHz, F_PD = 100 MHz⁽⁶⁾	No assist		50		µs
t_{VCO_CAL}		Close frequency		20		µs
K_VCO	VCO gain	8 GHz		89		MHz/V
		9.2 GHz		93
		10.3 GHz		110
		11.3 GHz		124
		12.5 GHz		189
		13.3 GHz		182
		14.5 GHz		205
\|ΔT_CL\|	Allowable temperature drift when VCO is not re-calibrated			125		°C
H2	VCO second harmonic	FVCO = 8 GHz, divider disabled		-30		dBc
H3	VCO third harmonic	FVCO = 8 GHz, divider disabled		-40		dBc
SYNC PIN AND PHASE ALIGNMENT
F_{OSCIN_SYNC}	Maximum usable OSCIN frequency with SYNC pin	Category 3 (int LO mode)	0		100	MHz
F_{OSCIN_SYNC}	Maximum usable OSCIN frequency with SYNC pin	Category 1 or 2	0		1400	MHz
DIGITAL INTERFACE (SCK, SDI, CSB, MUXOUT, SYNC, CE)
V_IH	High level input voltage		1.4		VCC	V
V_IL	Low level input voltage		0		0.4	V
I_IH	High level input current		-50		50	µA
I_IL	Low level input current		-50		50	µA
V_OH	High level output voltage	I_L = –5 mA	VCC – 0.55			V
V_OL	High level output current	I_L = 5 mA			0.55	V

(1) For measurements that require RF input, RF input power is -10dBm unless otherwise specified.

(2) For two-tone measurements, tone separation is 17MHz.

(3) Output power, spurs, and harmonics can vary based on board layout and components.

(4) For lower VCO frequencies, the N divider minimum value can limit the phase detector frequency.

(5) The PLL noise contribution is measured using a clean reference and a wide loop bandwidth and is composed into flicker and flat components. PLL_FLAT = PLL_FOM + 20log(F_VCO / F_PD) + 10log(F_PD / 1Hz). PLL_FLICKER (offset) = PLL_{FLICKER_NORM} + 20log(F_VCO / 1GHz) - 10log(offset frequency / 10kHz). Once these two components are found, the total PLL noise can be calculated as PLL_NOISE = 10log(10^{PLLFLAT / 10} + 10^{PLLFLICKER / 10}).

(6) See Application and Implementation for more details on the different VCO calibration modes.

6.6 Timing Requirements

		MIN	MAX	UNIT
SYNC
t_SETUP	Setup time for pin relative to OSCIN rising edge	2.5		ns
t_HOLD	Hold time for pin relative to OSCIN rising edge	2		ns
DIGITAL WRITE INTERFACE⁽¹⁾
F_{SPI_WRITE}	SPI write speed		50	MHz
t_ES	Clock to enable low time	5		ns
t_CS	Data to clock setup time	2		ns
t_CH	Data to clock hold time	2		ns
t_CWH	Clock pulse width high	5		ns
t_CWL	Clock pulse width low	10		ns
t_CES	Enable to clock setup time	10		ns
t_EWH	Enable pulse width high	10		ns
DIGITAL READBACK INTERFACE⁽²⁾
F_{SPI_READ}	SPI readback speed		50	MHz
t_ES	Clock to enable low time	10		ns
t_CS	Clock to data wait time		10	ns
t_CWH	Clock pulse width high	10		ns
t_CWL	Clock pulse width low	10		ns
t_CES	Enable to clock setup time	10		ns
t_EWH	Enable pulse width high	10		ns

(1) See Figure 1

(2) See Figure 2

Figure 1. Serial Data Input Timing Diagram

There are several other considerations for writing on the SPI:

The R/W bit must be set to 0.
The signal on the SDI pin is clocked into a shift register on each rising edge of the SCK pin.
The CSB must be held low for data to be clocked. Device ignores clock pulses if CSB is held high.
The CSB transition from high to low must occur when SCK is low.
When SCK and SDI lines are shared between devices, TI recommends holding the CSB line high on any devices besides the intended programming target.

LMX8410L timing_SPI_ReadBack_snas730.gif

Figure 2. Serial Data Readback Timing Diagram

There are several other considerations for SPI readback:

The R/W bit must be set to 1.
The MUXOUT pin is always for the address portion of the transaction.
The address on the SDI pin is clocked into a shift register on each rising edge of the SCK pin.
The data portion of the transaction on the SDI line is always ignored.
The data on the MUXOUT pin should be considered valid on each rising edge of the SCK pin, provided all timing requirements are met.
All CSB considerations for SPI writing also apply to SPI readback.

6.7 Typical Characteristics

Figure 3. Voltage Gain Across LO Frequency for Internal LO Mode

Figure 5. Voltage Gain Across IF Frequency for Internal LO Mode

Figure 7. IIP3 Across LO Frequency for Internal LO Mode

Figure 9. IIP3 Across IF Frequency for Internal LO Mode

Figure 11. IIP2: F1-F2 Across LO Frequency for Internal LO Mode

Figure 13. IIP2: F1-F2 Across IF Frequency for Internal LO Mode

Figure 15. IIP2: F1+F2 Across LO Frequency for Internal LO Mode

Figure 17. IIP2: F1+F2 Across IF Frequency for Internal LO Mode

Figure 19. Noise Figure Across LO Frequency for Internal LO Mode

Figure 21. Noise Figure Across IF Frequency for Internal LO Mode

Figure 23. Uncalibrated IQ Phase Difference for Internal LO Mode

Figure 25. Uncalibrated IQ Gain Imbalance for Internal LO Mode

Figure 27. IMRR for Internal LO Mode: Calibrated and Uncalibrated

Minus sign on x-axis means polarity is set to '1'.

Figure 29. IMRR Phase Calibration: Fine Accuracy Mode

Figure 31. IMRR Gain Calibration

Figure 33. 2x2 Spur for External LO Mode

Figure 35. 3x3 Spur for External LO Mode

Figure 37. LO to IF Leakage Level

Figure 39. LO to RF Leakage Level: External LO Mode

Jammer frequency = 8.8GHz, LO = 7.8GHz, IF = 100MHz.
Internal LO phase noise values used for calculation at -40, 25, and 85 degrees C are –155, –154.5 and –154 dBc/Hz, separately.

Figure 41. Noise Figure with Jammer

Figure 43. LO Port Mixed Modes S11

Figure 4. Voltage Gain Across LO frequency for External LO Mode

Figure 6. Voltage Gain Across IF Frequency for External LO Mode

Figure 8. IIP3 Across LO Frequency for External LO Mode

Figure 10. IIP3 Across IF Frequency for External LO Mode

Figure 12. IIP2: F1-F2 Across LO Frequency for External LO Mode

Figure 14. IIP2: F1-F2 Across IF Frequency for External LO Mode

Figure 16. IIP2: F1+F2 Across LO Frequency for External LO Mode

Figure 18. IIP2: F1+F2 Across IF Frequency for External LO Mode

Figure 20. Noise Figure Across LO Frequency for External LO Mode

Figure 22. Noise Figure Across IF Frequency for External LO Mode

Figure 24. Uncalibrated IQ Phase Difference for External LO Mode

Figure 26. Uncalibrated IQ Gain Imbalance for External LO Mode

Figure 28. IMRR for External LO Mode: Calibrated and Uncalibrated

Figure 30. IMRR Phase Calibration: Extended Range Mode

Figure 32. 2x2 Spur for Internal LO Mode

Figure 34. 3x3 Spur for Internal LO Mode

Figure 36. RF to IF Isolation

Figure 38. LO to RF Leakage Level: Internal LO Mode

The LO frequency is capped at 6600MHz because IP1dB exceeds +10dBm when LO frequency goes beyond 6600MHz; The device can be damaged when input power is more than +10dBm.

Figure 40. OP1dB Across LO Frequency

Figure 42. RF Port S11

Board losses and mismatch are not subtracted out. True output power may be higher. This plot shows single-ended LO output power only. Differential output power can be higher.

Figure 44. LO Output Power

Measurements are done at 25 degree C unless temperature is specified in the plots.

For measurements across LO frequency, IF = 65MHz, and LO injection type is high side injection. For measurements across IF frequency, high side injection is applied

For all measurements that require RF input, RF input power = -10 dBm unless otherwise specified.

For two-tone measurements, the separation between two tones is 17MHz.

For all measurements, internal 1.7V VCM is applied.

For all external LO mode measurements, LO power = +6 dBm.

IF baluns used for measurements are: ADT2-18+ from Mini-Circuits™.

LO balun used for measurements is: BIB-100G from PPM-Test™.

RF combiner used for measurements of IP2, IP3 and NF with jammer is: 4426-2 from Narda-MITEQ™.

All path losses are calibrated out.

7 Detailed Description

7.1 Overview

The LMX8410L is a high-performance I/Q demodulator with an RF input range of 4 to 10 GHz and an IF output range of DC to 1350 MHz. This device integrates many components to allow high system performance as well as simplified design. There is an integrated synthesizer that generates wide-band frequencies at very low phase noise, with signal carefully conditioned for driving the mixer LO port. The RF input is single ended, enabled by an integrated wide-band RF balun at the front end. The two mixers on each I/Q channel are highly linear with optimized filtering and interfacing with components on each port. The IF amplifier is a high gain and high linearity component, saving users from matching discrete amplifiers and being restricted by common mode voltages typically encountered when interfacing mixers and ADC’s. In addition to high linearity and low noise performance, the LMX8410L comes equipped with many features to further optimize certain parameters. The automatic DC offset calibration is run by an internal automatic algorithm which will sense and tune the DC offset between the N and P sides of the differential signal of each IF amplifier, thus ensuring optimal performance when directly DC coupled to the ADC. The I/Q calibration knob allows tuning blocks within the mixer and IF amplifier to balance both the gain and the phase of the I/Q output signals, thus giving the user capability to adjust and achieve high image rejection. The internal synthesizer also has a feature of synchronization, which allows multiple LMX8410L designed in parallel to have synchronized LO signal phase.