BQ25910 是一款适用于单节锂离子和锂聚合物电池的集成式三级开关模式并联电池充电管理器件。利用三级转换器,可在保持最高开关模式工作效率的同时降低解决方案尺寸,并提高功率密度。 该器件支持通过高输入电压为各种便携设备快速充电。该解决方案集成了反向阻断 FET (QBLK) 和四个开关 FET(QHSA、QHSB、QLSB、QLSA)。具有充电和系统设置的 I2C 串行接口使得此器件成为一个真正的灵活解决方案。
器件型号 | 封装 | 封装尺寸(标称值) |
---|---|---|
BQ25910 | DSBGA (36) | 2.41mm x 2.44mm |
Changes from A Revision (February 2018) to B Revision
Changes from * Revision (September 2017) to A Revision
PIN | I/O | DESCRIPTION | |
---|---|---|---|
NAME | NO. | ||
BATN | F4 | AI | Negative Battery Sense Terminal – Kelvin connect via 100-Ω resistor as close as possible to negative battery terminal |
BATP | F5 | AI | Positive Battery Sense Terminal – Kelvin connect via 100-Ω resistor as close as possible to positive battery terminal |
CAUX | F2 | P | Auxiliary Capacitor – Bypass CAUX to GND with at least a 4.7-μF, 10-V ceramic capacitor |
CDRV+ | D1 | P | Gate Drive Supply Positive Terminal – CDRV is used to generate multilevel gate drive rails.
Connect a 220-nF, 6.3-V ceramic capacitor across CDRV+ and CDRV-. |
CDRV– | E1 | P | Gate Drive Supply Negative Terminal – CDRV is used to generate multilevel gate drive rails.
Connect a 220-nF, 6.3-V ceramic capacitor across DRV+ and DRV-. |
CFLY+ | A3 | P | Flying Capacitor Positive Terminal – Connect 20-μF, 16-V ceramic capacitor across CFLY+ and CFLY–. Refer to Application and Implementation section for more information on selecting CFLY. |
B3 | |||
C3 | |||
D3 | |||
CFLY– | A5 | P | Flying Capacitor Negative Terminal – Connect 20-μF, 16-V ceramic capacitor across CFLY+ and CFLY–. Refer to Application and Implementation section for more information on selecting CFLY. |
B5 | |||
C5 | |||
D5 | |||
E5 | |||
GND | A6 | - | Ground Return |
B6 | |||
C6 | |||
D6 | |||
E6 | |||
IND_SNS | F6 | AI | Output Inductor Sense Input – Kelvin connect as close as possible to the output of the switched inductor. |
INT | E3 | DO | Open-Drain Interrupt Output – Connect INT to the logic rail via a 10-kΩ resistor. The INT pin sends active low, 256-μs pulse to the host to report charger device status and fault. |
PMID | A2 | P | Reverse Blocking MOSFET and QHSA MOSFET Connection – Given the total input capacitance, place 1 μF on VBUS, and the rest on PMID, as close to the device as possible. Typical value: 10-μF, 25-V ceramic capacitor |
B2 | |||
C2 | |||
D2 | |||
REGN | F3 | P | Gate Drive Supply – Bias supply for internal MOSFETs driver and device. Bypass REGN to GND with a 4.7-μF, 10-V ceramic capacitor. |
SCL | F1 | DI | I2C Interface Open-Drain Clock Line – Connect SCL to the logic rail through a 10-kΩ resistor. |
SDA | E2 | DIO | I2C Interface Open-Drain Data Line – Connect SDA to the logic rail through a 10-kΩ resistor. |
SW | A4 | P | Inductor Connection – Connect to the switched side of the external inductor (Recommended: 330 nH for up to 9-V applications or 470 nH for up to 12-V applications). Refer to Application and Implementation section for more information on selecting inductor. |
B4 | |||
C4 | |||
D4 | |||
E4 | |||
VBUS | A1 | P | Input Supply – VBUS is connected to the external DC supply. Bypass VBUS to GND with at least 1-μF, 25-V ceramic capacitor, placed as close to the device as possible. |
B1 | |||
C1 |
MIN | MAX | UNIT | |||
---|---|---|---|---|---|
Voltage range (with respect to GND) | VBUS (converter not switching) | –2 | 20 | V | |
PMID (converter not switching) | –0.3 | 20 | V | ||
CDRV+, CDRV- | –0.3 | 20 | V | ||
CFLY+ | –0.3 | 16(2) | V | ||
CFLY+ to SW, SW to CFLY–, CFLY– to GND, CAUX to GND | DC | –0.3 | 7 | V | |
Pulse < 30ns | –0.3 | 11 | V | ||
BATP, BATN, IND_SNS | –0.3 | 6 | V | ||
REGN | –0.3 | 6 | V | ||
Voltage range (with respect to GND) | SDA, SCL, /INT | –0.3 | 6 | V | |
Output sink current | /INT | 6 | mA | ||
Junction Temperature, TJ | –40 | 150 | °C | ||
Storage temperature, Tstg | –40 | 150 | °C |