• Menu
  • Product
  • Email
  • PDF
  • Order now

  • IWR1443 单芯片 76 至 81GHz 毫米波传感器

    • ZHCSHP9C May   2017  – October 2018 IWR1443

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • IWR1443 单芯片 76 至 81GHz 毫米波传感器
  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Signal Descriptions
      1. Table 4-1 Signal Descriptions
    3. 4.3 Pin Multiplexing
  5. 5Specifications
    1. 5.1 Absolute Maximum Ratings
    2. 5.2 ESD Ratings
    3. 5.3 Power-On Hours (POH)
    4. 5.4 Recommended Operating Conditions
    5. 5.5 Power Supply Specifications
    6. 5.6 Power Consumption Summary
    7. 5.7 RF Specification
    8. 5.8 Thermal Resistance Characteristics for FCBGA Package [ABL0161]
    9. 5.9 Timing and Switching Characteristics
      1. 5.9.1  Power Supply Sequencing and Reset Timing
      2. 5.9.2  Synchronized Frame Triggering
      3. 5.9.3  Input Clocks and Oscillators
        1. 5.9.3.1 Clock Specifications
      4. 5.9.4  Multibuffered / Standard Serial Peripheral Interface (MibSPI)
        1. 5.9.4.1 Peripheral Description
        2. 5.9.4.2 MibSPI Transmit and Receive RAM Organization
          1. Table 5-8  SPI Timing Conditions
          2. Table 5-9  SPI Master Mode Switching Parameters (CLOCK PHASE = 0, SPICLK = output, SPISIMO = output, and SPISOMI = input)
          3. Table 5-10 SPI Master Mode Switching Parameters (CLOCK PHASE = 1, SPICLK = output, SPISIMO = output, and SPISOMI = input)
        3. 5.9.4.3 SPI Slave Mode I/O Timings
          1. Table 5-11 SPI Slave Mode Switching Parameters (SPICLK = input, SPISIMO = input, and SPISOMI = output)
        4. 5.9.4.4 Typical Interface Protocol Diagram (Slave Mode)
      5. 5.9.5  LVDS Interface Configuration
        1. 5.9.5.1 LVDS Interface Timings
      6. 5.9.6  General-Purpose Input/Output
        1. Table 5-13 Switching Characteristics for Output Timing versus Load Capacitance (CL)
      7. 5.9.7  Controller Area Network Interface (DCAN)
        1. Table 5-14 Dynamic Characteristics for the DCANx TX and RX Pins
      8. 5.9.8  Serial Communication Interface (SCI)
        1. Table 5-15 SCI Timing Requirements
      9. 5.9.9  Inter-Integrated Circuit Interface (I2C)
        1. Table 5-16 I2C Timing Requirements
      10. 5.9.10 Quad Serial Peripheral Interface (QSPI)
        1. Table 5-17 QSPI Timing Conditions
        2. Table 5-18 Timing Requirements for QSPI Input (Read) Timings
        3. Table 5-19 QSPI Switching Characteristics
      11. 5.9.11 JTAG Interface
        1. Table 5-20 JTAG Timing Conditions
        2. Table 5-21 Timing Requirements for IEEE 1149.1 JTAG
        3. Table 5-22 Switching Characteristics Over Recommended Operating Conditions for IEEE 1149.1 JTAG
      12. 5.9.12 Camera Serial Interface (CSI)
        1. Table 5-23 CSI Switching Characteristics
  6. 6Detailed Description
    1. 6.1 Overview
    2. 6.2 Functional Block Diagram
    3. 6.3 External Interfaces
    4. 6.4 Subsystems
      1. 6.4.1 RF and Analog Subsystem
        1. 6.4.1.1 Clock Subsystem
        2. 6.4.1.2 Transmit Subsystem
        3. 6.4.1.3 Receive Subsystem
        4. 6.4.1.4 Radio Processor Subsystem
      2. 6.4.2 Master (Control) System
      3. 6.4.3 Host Interface
    5. 6.5 Accelerators and Coprocessors
    6. 6.6 Other Subsystems
      1. 6.6.1 A2D Data Format Over CSI2 Interface
      2. 6.6.2 ADC Channels (Service) for User Application
        1. Table 6-2 GP-ADC Parameter
    7. 6.7 Identification
    8. 6.8 Boot Modes
      1. 6.8.1 Flashing Mode
      2. 6.8.2 Functional Mode
  7. 7Applications, Implementation, and Layout
    1. 7.1 Application Information
    2. 7.2 Reference Schematic
    3. 7.3 Layout
      1. 7.3.1 Layout Guidelines
      2. 7.3.2 Layout Example
      3. 7.3.3 Stackup Details
  8. 8Device and Documentation Support
    1. 8.1 Device Nomenclature
    2. 8.2 Tools and Software
    3. 8.3 Documentation Support
    4. 8.4 Community Resources
    5. 8.5 商标
    6. 8.6 静电放电警告
    7. 8.7 Export Control Notice
    8. 8.8 Glossary
  9. 9Mechanical, Packaging, and Orderable Information
    1. 9.1 Packaging Information
  10. 重要声明
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

IWR1443 单芯片 76 至 81GHz 毫米波传感器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 器件概述

1.1 特性

  • FMCW 收发器
    • 集成式 PLL、发送器、接收器、基带和 A2D
    • 76 至 81GHz 覆盖范围，具有 4GHz 的连续带宽
    • 四个接收通道
    • 三个发送通道（可以同时使用两个通道）
    • 基于分数 N PLL 的超精确线性调频脉冲引擎
    • TX 功率：12dBm
    • RX 噪声系数：
      • 14dB（76 至 77GHz）
      • 15dB（77 至 81GHz）
    • 1MHz 时的相位噪声：
      • –95dBc/Hz（76 至 77GHz）
      • –93dBc/Hz（77 至 81GHz）
  • 内置的校准和自检
    • ARM®Cortex®基于 ARM® Cortex®-R4F 的无线电控制系统
    • 内置的固件 (ROM)
    • 针对频率和温度进行自校准的系统
  • 适用于嵌入式用户应用的片上可编程内核
    • 计时频率为 200MHz 的集成 Cortex®-R4F 微控制器
    • 片上引导加载程序支持自主模式（从 QSPI 闪存加载用户应用）
    • 集成外设
      • 具有 ECC 的内部存储器
      • 雷达硬件加速器（FFT、对数幅度计算等）
      • 集成计时器（看门狗以及多达四个 32 位计时器或两个 64 位计时器）
      • I2C（支持主模式和从模式）
      • 两个 SPI 端口
      • CAN 端口
      • 多达六个通用 ADC 端口
  • 支持分布式 应用
  • 主机接口
    • 通过 SPI 与外部处理器进行控制连接
    • 通过 MIPI D-PHY 和 CSI2 V1.1 与外部处理器进行数据连接
    • 用于故障报告的中断
  • IWR1443 高级 特性
    • 嵌入式自监控，无需使用主机处理器
    • 复基带架构
    • 嵌入式干扰检测功能
  • 电源管理
    • 内置的 LDO 网络，可增强 PSRR
    • I/O 支持双电压 3.3V/1.8V
  • 时钟源
    • 支持频率为 40MHz 的外部振荡器
    • 支持外部驱动、频率为 40MHz 的时钟（方波/正弦波）
  • 轻松的硬件设计
    • 0.65mm 间距、161 引脚 10.4mm × 10.4mm 覆晶 BGA 封装，可实现轻松组装和低成本 PCB 设计
    • 小尺寸解决方案
  • 运行条件
    • 结温范围:–40°C 至 105°C

1.2 应用

  • 用于测量距离、速度和角度的工业传感器
  • 液箱液位探测雷达
  • 位移感应
  • 现场发送器
  • 交通监控
  • 接近和位置感应
  • 安全和监控
  • 工厂自动化
  • 安全防护装置
IWR1443 front_pg_image.gifFigure 1-1 适用于工业应用的自主 传感器

1.3 说明

IWR1443 器件是一款能够在 76 至 81GHz 频带中运行且基于 FMCW 雷达技术的集成式单芯片毫米波传感器，具有高达 4GHz 的连续线性调频脉冲。该器件采用 TI 的低功耗 45nm RFCMOS 工艺进行构建，并且此解决方案在极小的封装中实现了前所未有的集成度。IWR1443 是适用于工业 应用 （如楼宇自动化、工厂自动化、无人机、物料处理、交通监控和监视）中的低功耗、自监控、超精确雷达系统的理想解决方案。

IWR1443 器件是一种自包含单芯片解决方案，能够简化 76 至 81GHz 频带中的毫米波传感器实施。IWR1443 包含一个具有内置 PLL 和模数转换器的单片实施 3TX、4RX 系统。该器件包含一个支持复数 FFT 和 CFAR 检测且完全可配置的硬件加速器。此外，该器件还包含两个基于 ARM R4F 的处理器子系统：一个处理器子系统用于主控制和其他算法；另一个处理器子系统负责前端配置、控制和校准。简单编程模型更改可支持各种传感器实施，并且能够进行动态重新配置，从而实现多模式传感器。此外，该器件作为完整的平台解决方案进行提供，该解决方案包括硬件参考设计、软件驱动程序、样例配置、API 指南、培训以及用户文档。

器件信息(1)

器件编号 封装 封装尺寸
IWR1443FQAGABLR（卷带） FCBGA (161) 10.4mm × 10.4mm
IWR1443FQAGABL（托盘）
(1) 更多信息请参见 Section 9，机械封装和可订购产品信息。

1.4 功能框图

IWR1443 fbd_swrs211.gif

2 修订历史记录

Changes from February 20, 2018 to October 31, 2018 (from B Revision (February 2018) to C Revision)

  • 将 RX 噪声系数从“15dB（76 至 77GHz）”更新成了“14dB（76 至 77GHz）”Go
  • 将 RX 噪声系数从“16dB（77 至 81GHz）”更新成了“15dB（77 至 81GHz）”Go
  • 将 1MHz 时的相位噪声从“–94dBc/Hz（76 至 77GHz）”更新成了“–95dBc/Hz（76 至 77GHz）”Go
  • 将 1MHz 时的相位噪声从“–91dBc/Hz（77 至 81GHz）”更新成了“–93dBc/Hz（77 至 81GHz）”Go
  • 从“...的高速数据接口”项目中删除了“（即中间数据）”Go
  • 从外部驱动振荡器和外部驱动时钟中删除了 50MHzGo
  • 更新了“器件信息”Go
  • 从功能方框图 中删除了“VMON”框Go
  • Added table note to "Number of transmitters" in Device Features ComparisonGo
  • Updated IWR1443 and IWR1642 Product status from AI to PDGo
  • Updated OSC_CLKOUTGo
  • Updated P7 from "Open Drain" to "Pull Up'Go
  • Updated B10 DESCRIPTIONGo
  • Updated A10, A13, A2, and B2 DESCRIPTIONGo
  • Removed footnote from Flash programming and RS232 UARTGo
  • Updated ESD RatingsGo
  • Updated/Changed Power-On Hours (POH)Go
  • Updated VIOIN in Recommended Operating ConditionsGo
  • Updated VIL 1.8V MAX from "3*VIOIN" to "0.3*VIOIN"Go
  • Updated VOH in Recommended Operating ConditionsGo
  • Updated VOH in Recommended Operating ConditionsGo
  • Updated Recommended Operating ConditionsGo
  • Added "VNWA" to 1.2 V Supply in Power Supply Rails CharacteristicsGo
  • Completely updated Ripple Specifications tableGo
  • Updated Receiver Noise figure values in RF SpecificationGo
  • Updated Receiver 1-dB compression point value from "–5" to "–8"Go
  • Updated "IQ gain mismatch" to "Image Rejection Ratio (IMRR)"Go
  • Removed IQ phase mismatch from RF SpecificationGo
  • Updated RF Specification tableGo
  • Updated footnote in RF SpecificationGo
  • Removed 1v4 signal from Device Wakeup Go
  • Updated Device Wake-up SequenceGo
  • Updated Synchronized Frame Triggering text Go
  • Added Synchronized Frame Triggering subsectionGo
  • Removed TLag from Frame Trigger Timing table Go
  • Updated Crystal Implementation noteGo
  • Updated/Changed fP Parallel resonance crystal frequency from " 40, 50" to "40"Go
  • Completely updated External Clock Mode SpecificationsGo
  • Updated SPI Slave Mode Timing RequirementsGo
  • Added LVDS Interface ConfigurationGo
  • Updated LVDS Interface Lane Config imageGo
  • Updated Timing ParametersGo
  • Updated LVDS Electrical Characteristics Go
  • Updated Timing Requirements for QSPI Input (Read) TimingsGo
  • Added Q12, Q13, Q14, and Q15 to QSPI Switching CharacteristicsGo
  • Updated Data bit rate from 900 Mbps to 600 MbpsGo
  • Removed TCLK-SETTLE and THS-SETTLEGo
  • Updated Clock Subsystem diagramGo
  • Updated/Changed Transmit Subsystem (Per Channel)Go
  • Removed Master System Memory MapGo
  • Updated Host InterfaceGo
  • Updated text in "A2D Data Format Over CSI2 Interface"Go
  • Updated text in ADC Channels (Service) for User ApplicationGo
  • Completely updated GP-ADC Parameter tableGo
  • Updated text in Functional ModeGo
  • Updated Application InformationGo
  • Updated Device NomenclatureGo

3 Device Comparison

Table 3-1 Device Features Comparison

FUNCTION IWR1443 IWR1642
Number of receivers 4 4
Number of transmitters 3 2
On-chip memory 576KB 1.5MB
Max I/F (Intermediate Frequency) (MHz) 15 5
Max real sampling rate (Msps) 37.5 12.5
Max complex sampling rate (Msps) 18.75 6.25
Processor
MCU (R4F) Yes Yes
DSP (C674x) — Yes
Peripherals
Serial Peripheral Interface (SPI) ports 1 2
Quad Serial Peripheral Interface (QSPI) Yes Yes
Inter-Integrated Circuit (I2C) interface 1 1
Controller Area Network (DCAN) interface Yes Yes
Trace — Yes
PWM — Yes
Hardware In Loop (HIL/DMM) — Yes
GPADC Yes Yes
LVDS/Debug Yes Yes
CSI2 Yes —
Hardware accelerator Yes —
1-V bypass mode Yes Yes
JTAG Yes Yes
Product status Product Preview (PP),
Advance Information (AI),
or Production Data (PD) 		PD(1) PD(1)
(1) PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.

3.1 Related Products

For information about other devices in this family of products or related products see the links that follow.

    mmWave SensorsTI’s mmWave sensors rapidly and accurately sense range, angle and velocity with less power using the smallest footprint mmWave sensor portfolio for industrial applications.
    mmWave IWRThe Texas Instruments IWR1xxx family of mmWave Sensors are highly integrated and built on RFCMOS technology operating in 76- to 81-GHz frequency band. The devices have a closed-loop PLL for precise and linear chirp synthesis, includes a built-in radio processor (BIST) for RF calibration and safety monitoring. The devices have a very small-form factor, low power consumption, and are highly accurate. Industrial applications from long range to ultra short range can be realized using these devices.
    Companion Products for IWR1443Review products that are frequently purchased or used in conjunction with this product.
    IWR1443 Reference DesignsThe IWR1443 TI Designs Reference Design Library is a robust reference design library spanning analog, embedded processor and connectivity. Created by TI experts to help you jump-start your system design, all TI Designs include schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download designs at ti.com/tidesigns.
    Power Optimization for IWR1443 77GHz-Level Transmitter Reference DesignThe TIDEP-0091 highlights strategies for power optimization of a IWR1443 76- to 81-GHz mmWave sensor in tank level-probing applications, displacement sensors, 4- to 20-mA sensors, and other low-power applications for detecting range with high accuracy in minimal power envelope.

4 Terminal Configuration and Functions

4.1 Pin Diagram

Figure 4-1 shows the pin locations for the 161-pin FCBGA package. Figure 4-2, Figure 4-3, Figure 4-4, and Figure 4-5 show the same pins, but split into four quadrants.

IWR1443 pin_map_full_iwr14.gifFigure 4-1 Pin Diagram
IWR1443 pin_map_1_iwr14.gifFigure 4-2 Top Left Quadrant
IWR1443 pin_map_2_iwr14.gifFigure 4-3 Top Right Quadrant
IWR1443 pin_map_3_awr12_iwr14.gifFigure 4-4 Bottom Left Quadrant
Figure 4-5 Bottom Right Quadrant

4.2 Signal Descriptions

Table 4-1 Signal Descriptions

FUNCTION SIGNAL NAME PIN NUMBER PIN TYPE DEFAULT PULL STATUS(1) DESCRIPTION
Transmitters TX1 B4 O — Single-ended transmitter1 o/p
TX2 B6 O — Single-ended transmitter2 o/p
TX3 B8 O — Single-ended transmitter3 o/p
Receivers RX1 M2 I — Single-ended receiver1 i/p
RX2 K2 I — Single-ended receiver2 i/p
RX3 H2 I — Single-ended receiver3 i/p
RX4 F2 I — Single-ended receiver4 i/p
CSI2 TX/LVDS TX CSI2_TXP[0] G15 O — Differential data Out – Lane 0
CSI2_TXM[0] G14 O —
CSI2_CLKP J15 O — Differential clock Out
CSI2_CLKM J14 O —
CSI2_TXP[1] H15 O — Differential data Out – Lane 1
CSI2_TXM[1] H14 O —
CSI2_TXP[2] K15 O — Differential data Out – Lane 2
CSI2_TXM[2] K14 O —
CSI2_TXP[3] L15 O — Differential data Out – Lane 3
CSI2_TXM[3] L14 O —
HS_DEBUG1_P M15 O — Differential debug port 1
HS_DEBUG1_M M14 O —
HS_DEBUG2_P N15 O — Differential debug port 2
HS_DEBUG2_M N14 O —
RESERVED B1, B15, D1, D15 —
Reference clock OSC_CLKOUT A14 O — Reference clock output from clocking subsystem after cleanup PLL.
System synchronization SYNC_OUT P11 O Pull Down Low-frequency frame synchronization signal output. Can be used by slave chip in multichip cascading
SYNC_IN N10 I Pull Down Low-frequency frame synchronization signal input.
SPI control interface from external MCU (default slave mode) SPI_CS_1 R7 I Pull Up SPI chip select
SPI_CLK_1 R9 I Pull Down SPI clock
MOSI_1 R8 I Pull Up SPI data input
MISO_1 P5 O Pull Up SPI data output
SPI_HOST_INTR_1 P6 O Pull Down SPI interrupt to host
RESERVED R3, R4, R5, P4 —
Reset NRESET P12 I Open Drain Power on reset for chip. Active low
WARM_RESET N12 IO Open Drain Open-drain fail-safe warm reset signal. Can be driven from PMIC for diagnostic or can be used as status signal that the device is going through reset.
Safety NERROR_OUT N8 O Open Drain Open-drain fail-safe output signal. Connected to PMIC/Processor/MCU to indicate that some severe criticality fault has happened. Recovery would be through reset.
NERROR_IN P7 I Pull Up Fail-safe input to the device. Error output from any other device can be concentrated in the error signaling monitor module inside the device and appropriate action can be taken by firmware
JTAG TMS L13 I Pull Up JTAG port for standard boundary scan
TCK M13 I Pull Down
TDI H13 I Pull Up
TDO J13 O —
Reference oscillator CLKP E14 I — In XTAL mode: Differential port for reference crystal
In External clock mode: Single ended input reference clock port (Output CLKM is grounded in this case)
CLKM F14 O —
Band-gap voltage VBGAP B10 O — Internal voltage reference 0.9V
Power supply VDDIN F13,N11,P15,R6 POW — 1.2-V digital power supply
VIN_SRAM R14 POW — 1.2-V power rail for internal SRAM
VNWA P14 POW — 1.2-V power rail for SRAM array back bias
VIOIN R13 POW — I/O supply (3.3-V or 1.8-V): All CMOS I/Os would operate on this supply.
VIOIN_18 K13 POW — 1.8-V supply for CMOS IO
VIN_18CLK B11 POW — 1.8-V supply for clock module
VIOIN_18DIFF D13 POW — 1.8-V supply for CSI2 port
Reserved G13 POW — No connect
VIN_13RF1 G5,J5,H5 POW — 1.3-V Analog and RF supply,VIN_13RF1 and VIN_13RF2 could be shorted on the board
1.0-V Analog and RF supply input if RFLDO is bypassed
VIN_13RF2 C2,D2 POW —
VIN_18BB K5,F5 POW — 1.8-V Analog baseband power supply
VIN_18VCO B12 POW — 1.8-V RF VCO supply
VSS E5,E6,E8,E10,E11,F9,F11,G6,G7,G8,G10,H7,H9,H11,J6,J7,J8,J10,K7,K8,K9,K10,K11,L5,L6,L8,L10,R15 GND — Digital ground
VSSA A1,A3,A5,A7,A9,A15,B3,B5,B7,B9,B13,B14,C1,C3,C4,C5,C6,C7,C8,C9,C15,E1,E2,E3,E13,E15,F3,G1,G2,G3,H3,J1,J2,J3,K3,L1,L2,L3, M3,N1,N2,N3,R1 GND — Analog ground
Internal LDO output/inputs VOUT_14APLL A10 O — 1.4V internal regulator
VOUT_14SYNTH A13 O — 1.4V internal regulator
VOUT_PA A2,B2 O — 1.0V internal regulator
External clock out PMIC_CLK_OUT P13 O — Dithered clock input to PMIC
MCU_CLK_OUT N9 O — Programmable clock given out to external MCU or the processor
General-purpose I/Os GPIO[0] N4 IO Pull Down General-purpose IO
GPIO[1] N7 IO Pull Down General-purpose IO
GPIO[2] N13 IO Pull Down General-purpose IO
QSPI for Serial Flash QSPI_CS P8 O Pull Up Chip-select output from the device. Device is a master connected to serial flash slave.
QSPI_CLK R10 O Pull Down Clock output from the device. Device is a master connected to serial flash slave.
QSPI[0] R11 IO Pull Down Data IN/OUT
QSPI[1] P9 IO Pull Down Data IN/OUT
QSPI[2] R12 IO Pull Up Data IN/OUT
QSPI[3] P10 IO Pull Up Data IN/OUT
Flash programming and RS232 UART RS232_TX N6 O Pull Down UART pins for programming external flash in preproduction/debug hardware.
RS232_RX N5 I Pull Up
Test and Debug output for preproduction phase. Can be pinned out on production hardware for field debug Analog Test1 / GPADC1 P1 IO — GP ADC channel 1
Analog Test2 / GPADC2 P2 IO — GP ADC channel 2
Analog Test3 / GPADC3 P3 IO — GP ADC channel 3
Analog Test4 / GPADC4 R2 IO — GP ADC channel 4
ANAMUX / GPADC5 C13 IO — GP ADC channel 5
VSENSE / GPADC6 C14 IO — GP ADC channel 6
(1) Status of PULL structures associated with the IO after device POWER UP.

4.3 Pin Multiplexing

Table 4-2 Pin Multiplexing

REGISTER ADDRESS(1) PIN NAME PIN DIGITAL PIN MUX CONFIG VALUE [Bits3:0] FUNCTION PAD STATE
nReset = 0 [ASSERTED]
SIGNAL NAME SIGNAL DESCRIPTION SIGNAL TYPE STATE INTERNAL WEAK PULL STATE
EA00h GPIO_12 P6 0 GPIO_12 General Purpose IO IO Hi-Z Weak Pull Down
1 SPI_HOST1_INTR General Purpose IO [IWR14xx] O
EA04h GPIO_0 N4 0 GPIO_13 General Purpose IO IO Hi-Z Weak Pull Down
1 GPIO_0 General Purpose IO IO
2 PMIC_CLKOUT Dithered Clock Output for PMIC O
EA08h GPIO_1 N7 0 GPIO_16 General Purpose IO IO Hi-Z Weak Pull Down
1 GPIO_1 General Purpose IO IO
2 SYNC_OUT Low Frequency Synchronization Signal output O
EA0Ch MOSI_1 R8 0 GPIO_19 General Purpose IO IO Hi-Z Weak Pull Up
1 MOSI_1 SPI Channel#1 Data Input IO
2 CAN_RX CAN Interface I
EA10h MISO_1 P5 0 GPIO_20 General Purpose IO IO Hi-Z Weak Pull Up
1 MISO_1 SPI Channel#1 Data Output IO
2 CAN_TX CAN Interface O
EA14h SPI_CLK_1 R9 0 GPIO_3 General Purpose IO IO Hi-Z Weak Pull Up
1 SPI_CLK_1 SPI Channel#1 Clock IO
RCOSC_CLK O
EA18h SPI_CS_1 R7 0 GPIO_30 General Purpose IO IO Hi-Z Weak Pull Up
1 SPI_CS_1 SPI Channel#1 Chip Select IO
RCOSC_CLK O
EA1Ch MOSI_2 R3 0 GPIO_21 General Purpose IO IO Hi-Z
1 MOSI_2 SPI Channel#2 Data Input IO
2 I2C_SDA I2C Data IO
EA20h MISO_2 P4 0 GPIO_22 General Purpose IO IO Hi-Z
1 MISO_2 SPI Channel#2 Data Output IO
2 I2C_SCL I2C Clock IO
EA24h SPI_CLK_2 R5 0 GPIO_5 General Purpose IO IO Hi-Z
1 SPI_CLK_2 SPI Channel#2 Clock IO
MSS_UARTA_RX IO
6 MSS_UARTB_TX Debug: Firmware Trace O
7 BSS_UART_TX Debug: Firmware Trace O
EA28h SPI_CS_2 R4 0 GPIO_4 General Purpose IO IO Hi-Z
1 SPI_CS_2 SPI Channel#2 Chip Select IO
MSS_UARTA_TX IO
6 MSS_UARTB_TX Debug: Firmware Trace O
7 BSS_UART_TX Debug: Firmware Trace O
EA2Ch QSPI[0] R11 0 GPIO_8 General Purpose IO IO Hi-Z Weak Pull Down
1 QSPI[0] QSPI Data IN/OUT IO
2 MISO_2 SPI Channel#1 Data Output IO
EA30h QSPI[1] P9 0 GPIO_9 General Purpose IO IO Hi-Z Weak Pull Down
1 QSPI[1] QSPI Data IN/OUT IO
2 MOSI_2 SPI Channel#2 Data Input IO
EA34h QSPI[2] R12 0 GPIO_10 General Purpose IO IO Hi-Z Weak Pull Down
1 QSPI[2] QSPI Data IN/OUT IO
EA38h QSPI[3] P10 0 GPIO_11 General Purpose IO IO Hi-Z Weak Pull Down
1 QSPI[3] QSPI Data IN/OUT I
EA3Ch QSPI_CLK R10 0 GPIO_7 General Purpose IO IO Hi-Z Weak Pull Down
1 QSPI_CLK QSPI Clock output from the device.
Device operates as a master with the serial flash being a slave		 O
2 SPI_CLK_2 SPI Channel#2 Clock IO
EA40h QSPI_CS P8 0 GPIO_6 General Purpose IO IO Hi-Z Weak Pull Up
1 QSPI_CS QSPI Chip Select output from the device.
Device operates as a master with the serial flash being a slave		 O
2 SPI_CS_2 SPI Channel#2 Chip Select IO
NERROR_IN P7 NERROR_IN Failsafe input to the device. Nerror output from any other device can be concentrated in the error signaling monitor module inside the device and appropriate action can be taken by Firmware I Hi-Z
WARM_RESET N12 WARM_RESET Open drain fail safe warm reset signal. Can be driven from PMIC for diagnostic or can be used as status signal that the device is going through reset. IO Hi-Z Input Open Drain
NERROR_OUT N8 NERROR_OUT Open drain fail safe output signal. Connected to PMIC/Processor/MCU to indicate that some severe criticality fault has happened. Recovery would be through reset. O Hi-Z Open Drain
EA50h TCK M13 0 GPIO_17 General Purpose IO IO Hi-Z Weak Pull Down
1 TCK JTAG Clock I
2 MSS_UARTB_TX Debug: Firmware Trace O
6 BSS_UART_RX Debug: Firmware Trace I
EA54h TMS L13 0 GPIO_18 General Purpose IO IO Hi-Z Weak Pull Up
1 TMS JTAG Test Mode Select IO
2 BSS_UART_TX Debug: Firmware Trace O
EA58h TDI H13 0 GPIO_23 General Purpose IO IO Hi-Z Weak Pull Up
1 TDI JTAG Test Data In I
MSS_UARTA_RX IO
EA5Ch TDO J13 0 GPIO_24 General Purpose IO IO Hi-Z
1 TDO JTAG Test Data Out O
MSS_UARTA_TX IO
6 MSS_UARTB_TX Debug: Firmware Trace O
7 BSS_UART_TX Debug: Firmware Trace O
SOP0 Sense On Power [Reset] Line
Impacts boot mode		 I
EA60h MCU_CLKOUT N9 0 GPIO_25 General Purpose IO IO Hi-Z Weak Pull Down
1 MCU_CLKOUT Programmable clock given out to external MCU or the processor O
10 BSS_UART_RX Debug: Firmware Trace I
EA64h GPIO_2 N13 0 GPIO_26 General Purpose IO IO Hi-Z Weak Pull Down
1 GPIO_2 General Purpose IO IO
7 MSS_UARTB_TX Debug: Firmware Trace O
8 BSS_UART_TX Debug: Firmware Trace O
9 SYNC_OUT Low frequency Synchronization signal output O
10 PMIC_CLKOUT Dithered clock input to PMIC O
EA68h PMIC_CLKOUT P13 0 GPIO_27 General Purpose IO IO Hi-Z Weak Pull Down
1 PMIC_CLKOUT Dithered Clock Output for PMIC O
SOP2 Sense On Power [Reset] Line
Impacts boot mode		 I
EA6Ch SYNC_IN N10 0 GPIO_28 General Purpose IO IO Hi-Z Weak Pull Down
1 SYNC_IN Low frequency Synchronization signal input I
6 MSS_UARTB_RX Debug: Firmware Trace I
EA70h SYNC_OUT P11 0 GPIO_29 General Purpose IO IO Hi-Z Weak Pull Down
1 SYNC_OUT Low frequency Synchronization signal output O
RCOSC_CLK O
SOP1 Sense On Power [Reset] Line
Impacts boot mode		 I
EA74h RS232_RX N5 0 GPIO_15 General Purpose IO IO Hi-Z Weak Pull Up
1 RS232_RX Debug: Firmware load to RAM IO
2 MSS_UARTA_RX FLASH Programming
Bootloader Controlled		 I
6 BSS_UART_TX Debug: Firmware Trace O
7 MSS_UARTB_RX Debug: Firmware Trace I
EA78h RS232_TX N6 0 GPIO_14 General Purpose IO IO
1 RS232_TX Debug: Firmware load to RAM IO
5 MSS_UARTA_TX FLASH Programming
Bootloader Controlled		 O
6 MSS_UARTB_TX Debug: Firmware Trace O
7 BSS_UART_TX Debug: Firmware Trace O
(1) Register addresses are of the form FFFF XXXXh, where XXXX is listed here.

5 Specifications

5.1 Absolute Maximum Ratings(1)(2)

over operating Tj temperature range (unless otherwise noted)
PARAMETERS MIN MAX UNIT
VDDIN 1.2 V digital power supply –0.5 1.4 V
VIN_SRAM 1.2 V power rail for internal SRAM –0.5 1.4 V
VNWA 1.2 V power rail for SRAM array back bias –0.5 1.4 V
VIOIN I/O supply (3.3 V or 1.8 V): All CMOS I/Os would operate on this supply. –0.5 3.8 V
VIOIN_18 1.8 V supply for CMOS IO –0.5 2 V
VIN_18CLK 1.8 V supply for clock module –0.5 2 V
VIOIN_18DIFF 1.8 V supply for CSI2 port –0.5 2 V
VIN_13RF1 1.3 V Analog and RF supply, VIN_13RF1 and VIN_13RF2 could be shorted on the board. –0.5 1.45 V
VIN_13RF2
VIN_13RF1 1-V Internal LDO bypass mode. Device supports mode where external Power Management block can supply 1 V on VIN_13RF1 and VIN_13RF2 rails. In this configuration, the internal LDO of the device would be kept bypassed. –0.5 1.4 V
VIN_13RF2
VIN_18BB 1.8-V Analog baseband power supply –0.5 2 V
VIN_18VCO supply 1.8-V RF VCO supply –0.5 2 V
Input and output voltage range Dual-voltage LVCMOS inputs, 3.3 V or 1.8 V (Steady State) –0.3V VIOIN + 0.3 V
Dual-voltage LVCMOS inputs, operated at 3.3 V/1.8 V
(Transient Overshoot/Undershoot) or external oscillator input		 VIOIN + 20% up to
20% of signal period
CLKP, CLKM Input ports for reference crystal –0.5 2 V
Clamp current Input or Output Voltages 0.3 V above or below their respective power rails. Limit clamp current that flows through the internal diode protection cells of the I/O. –20 20 mA
TJ Operating junction temperature range –40 105 ºC
TSTG Storage temperature range after soldered onto PC board –55 150 ºC
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltage values are with respect to VSS, unless otherwise noted.

5.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM) ±2000 V
Charged-device model (CDM) All other pins ±500
Corner pins ±750

5.3 Power-On Hours (POH)(1)

JUNCTION TEMPERATURE (Tj) OPERATING CONDITION NOMINAL CVDD VOLTAGE (V) POWER-ON HOURS [POH] (HOURS)
90% at 85ºC Tj
10% at 105ºC Tj 		50% duty cycle 1.2 80,000
100% at 85ºC Tj 100,000
(1) This information is provided solely for your convenience and does not extend or modify the warranty provided under TI's standard terms and conditions for TI semiconductor products.

5.4 Recommended Operating Conditions

Tjunction temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDDIN 1.2 V digital power supply 1.14 1.2 1.32 V
VIN_SRAM 1.2 V power rail for internal SRAM 1.14 1.2 1.32 V
VNWA 1.2 V power rail for SRAM array back bias 1.14 1.2 1.32 V
VIOIN I/O supply (3.3 V) 3.15 3.3 3.45 V
I/O supply (1.8 V) 1.71 1.8 1.89
VIOIN_18 1.8 V supply for CMOS IO 1.71 1.8 1.9 V
VIN_18CLK 1.8 V supply for clock module 1.71 1.8 1.9 V
VIOIN_18DIFF 1.8 V supply for CSI2 port 1.71 1.8 1.9 V
VIN_13RF1 1.3 V Analog and RF supply. VIN_13RF1 and VIN_13RF2 could be shorted on the board 1.23 1.3 1.36 V
VIN_13RF2
VIN_13RF1
(1-V Internal LDO bypass mode) 		Device supports mode where external Power Management block can supply 1 V on VIN_13RF1 and VIN_13RF2 rails. In this configuration, the internal LDO of the device would be kept bypassed. 0.95 1 1.05 V
VIN_13RF2
(1-V Internal LDO bypass mode)
VIN18BB 1.8-V Analog baseband power supply 1.71 1.8 1.9 V
VIN_18VCO 1.8V RF VCO supply 1.71 1.8 1.9 V
VIH Voltage Input High (1.8 V mode) 1.17 V
Voltage Input High (3.3 V mode) 2.25
VIL Voltage Input Low (1.8 V mode) 0.3*VIOIN V
Voltage Input Low (3.3 V mode) 0.62
VOH High-level output threshold (IOH = 6 mA) (1.8V) 85%*VIOIN mV
High-level output threshold (IOH = 6 mA) (3.3V) VIOIN – 450mV
VOL Low-level output threshold (IOL = 6 mA) 450 mV
NRESET SOP[2:0] VIL (1.8V Mode) 0.2 V
VIH (1.8V Mode) 0.96
VIL (3.3V Mode) 0.3
VIH (3.3V Mode) 1.57

5.5 Power Supply Specifications

Table 5-1 describes the four rails from an external power supply block of the IWR1443 device.

Table 5-1 Power Supply Rails Characteristics

SUPPLY DEVICE BLOCKS POWERED FROM THE SUPPLY RELEVANT IOS IN THE DEVICE
1.8 V Synthesizer and APLL VCOs, crystal oscillator, IF Amplifier stages, ADC, LVDS Input: VIN_18VCO, VIN18CLK, VIN_18BB, VIOIN_18DIFF, VIOIN_18IO
LDO Output: VOUT_14SYNTH, VOUT_14APLL
1.3 V (or 1 V in internal LDO bypass mode) Power Amplifier, Low Noise Amplifier, Mixers and LO Distribution Input: VIN_13RF2, VIN_13RF1
LDO Output: VOUT_PA
3.3 V (or 1.8 V for 1.8 V I/O mode) Digital I/Os Input VIOIN
1.2 V Core Digital and SRAMs Input: VDDIN, VIN_SRAM, VNWA

The 1.3V (1.0V) and 1.8V power supply ripple specifications mentioned in Table 5-2 are defined to meet a target spur level of –105dBc (RF Pin = –15dBm) at the RX. The spur and ripple levels have a dB to dB relationship, for example, a 1dB increase in supply ripple leads to a ~1dB increase in spur level. Values quoted are rms levels for a sinusoidal input applied at the specified frequency.

Table 5-2 Ripple Specifications

FREQUENCY (kHz) RF RAIL VCO/IF RAIL
1.0 V (INTERNAL LDO BYPASS) (µVRMS) 1.3 V (µVRMS) 1.8 V (µVRMS)
137.5 744 648 83
275 4 76 21
550 3 22 11
1100 2 4 6
2200 11 82 13
4400 13 93 19
6600 22 117 29

5.6 Power Consumption Summary

Table 5-3 and Table 5-4 summarize the power consumption at the power terminals.

Table 5-3 Maximum Current Ratings at Power Terminals

PARAMETER SUPPLY NAME DESCRIPTION MIN TYP MAX UNIT
Current consumption VDDIN, VIN_SRAM, VNWA Total current drawn by all nodes driven by 1.2V rail 500 mA
VIN_13RF1, VIN_13RF2 Total current drawn by all nodes driven by 1.3V rail 2000
VIOIN_18, VIN_18CLK, VIOIN_18DIFF, VIN_18BB, VIN_18VCO Total current drawn by all nodes driven by 1.8V rail 850
VIOIN Total current drawn by all nodes driven by 3.3V rail 50

Table 5-4 Average Power Consumption at Power Terminals

PARAMETER CONDITION DESCRIPTION MIN TYP MAX UNIT
Average power consumption 1.0-V internal LDO bypass mode 1TX, 4RX Sampling: 16.66 MSps complex Transceiver, 40-ms frame time, 512 chirps, 512 samples/chirp, 8.5-μs interchirp time (50% duty cycle) Data Port: MIPI-CSI-2 1.73 W
2TX, 4RX 1.88
1.3-V internal LDO enabled mode 1TX, 4RX 1.92
2TX, 4RX 2.1

 
Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale