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  • ADC12DJ2700 5.4GSPS 单通道或 2.7GSPS 双通道 12 位射频采样模数转换器 (ADC)

    • ZHCSHD7A January   2018  – April 2020 ADC12DJ2700

      PRODUCTION DATA.  

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  • ADC12DJ2700 5.4GSPS 单通道或 2.7GSPS 双通道 12 位射频采样模数转换器 (ADC)
  1. 1 特性
    1.     ADC12DJ2700 测量的输入带宽
  2. 2 应用
  3. 3 说明
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Electrical Characteristics: DC Specifications
    6. 6.6  Electrical Characteristics: Power Consumption
    7. 6.7  Electrical Characteristics: AC Specifications (Dual-Channel Mode)
    8. 6.8  Electrical Characteristics: AC Specifications (Single-Channel Mode)
    9. 6.9  Timing Requirements
    10. 6.10 Switching Characteristics
    11. 6.11 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1 Device Comparison
      2. 7.3.2 Analog Inputs
        1. 7.3.2.1 Analog Input Protection
        2. 7.3.2.2 Full-Scale Voltage (VFS) Adjustment
        3. 7.3.2.3 Analog Input Offset Adjust
      3. 7.3.3 ADC Core
        1. 7.3.3.1 ADC Theory of Operation
        2. 7.3.3.2 ADC Core Calibration
        3. 7.3.3.3 Analog Reference Voltage
        4. 7.3.3.4 ADC Overrange Detection
        5. 7.3.3.5 Code Error Rate (CER)
      4. 7.3.4 Temperature Monitoring Diode
      5. 7.3.5 Timestamp
      6. 7.3.6 Clocking
        1. 7.3.6.1 Noiseless Aperture Delay Adjustment (tAD Adjust)
        2. 7.3.6.2 Aperture Delay Ramp Control (TAD_RAMP)
        3. 7.3.6.3 SYSREF Capture for Multi-Device Synchronization and Deterministic Latency
          1. 7.3.6.3.1 SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing)
          2. 7.3.6.3.2 Automatic SYSREF Calibration
      7. 7.3.7 Digital Down Converters (Dual-Channel Mode Only)
        1. 7.3.7.1 Numerically-Controlled Oscillator and Complex Mixer
          1. 7.3.7.1.1 NCO Fast Frequency Hopping (FFH)
          2. 7.3.7.1.2 NCO Selection
          3. 7.3.7.1.3 Basic NCO Frequency Setting Mode
          4. 7.3.7.1.4 Rational NCO Frequency Setting Mode
          5. 7.3.7.1.5 NCO Phase Offset Setting
          6. 7.3.7.1.6 NCO Phase Synchronization
        2. 7.3.7.2 Decimation Filters
        3. 7.3.7.3 Output Data Format
        4. 7.3.7.4 Decimation Settings
          1. 7.3.7.4.1 Decimation Factor
          2. 7.3.7.4.2 DDC Gain Boost
      8. 7.3.8 JESD204B Interface
        1. 7.3.8.1 Transport Layer
        2. 7.3.8.2 Scrambler
        3. 7.3.8.3 Link Layer
          1. 7.3.8.3.1 Code Group Synchronization (CGS)
          2. 7.3.8.3.2 Initial Lane Alignment Sequence (ILAS)
          3. 7.3.8.3.3 8b, 10b Encoding
          4. 7.3.8.3.4 Frame and Multiframe Monitoring
        4. 7.3.8.4 Physical Layer
          1. 7.3.8.4.1 SerDes Pre-Emphasis
        5. 7.3.8.5 JESD204B Enable
        6. 7.3.8.6 Multi-Device Synchronization and Deterministic Latency
        7. 7.3.8.7 Operation in Subclass 0 Systems
      9. 7.3.9 Alarm Monitoring
        1. 7.3.9.1 NCO Upset Detection
        2. 7.3.9.2 Clock Upset Detection
    4. 7.4 Device Functional Modes
      1. 7.4.1 Dual-Channel Mode
      2. 7.4.2 Single-Channel Mode (DES Mode)
      3. 7.4.3 JESD204B Modes
        1. 7.4.3.1 JESD204B Output Data Formats
        2. 7.4.3.2 Dual DDC and Redundant Data Mode
      4. 7.4.4 Power-Down Modes
      5. 7.4.5 Test Modes
        1. 7.4.5.1 Serializer Test-Mode Details
        2. 7.4.5.2 PRBS Test Modes
        3. 7.4.5.3 Ramp Test Mode
        4. 7.4.5.4 Short and Long Transport Test Mode
          1. 7.4.5.4.1 Short Transport Test Pattern
          2. 7.4.5.4.2 Long Transport Test Pattern
        5. 7.4.5.5 D21.5 Test Mode
        6. 7.4.5.6 K28.5 Test Mode
        7. 7.4.5.7 Repeated ILA Test Mode
        8. 7.4.5.8 Modified RPAT Test Mode
      6. 7.4.6 Calibration Modes and Trimming
        1. 7.4.6.1 Foreground Calibration Mode
        2. 7.4.6.2 Background Calibration Mode
        3. 7.4.6.3 Low-Power Background Calibration (LPBG) Mode
      7. 7.4.7 Offset Calibration
      8. 7.4.8 Trimming
      9. 7.4.9 Offset Filtering
    5. 7.5 Programming
      1. 7.5.1 Using the Serial Interface
        1. 7.5.1.1 SCS
        2. 7.5.1.2 SCLK
        3. 7.5.1.3 SDI
        4. 7.5.1.4 SDO
        5. 7.5.1.5 Streaming Mode
    6. 7.6 Register Maps
      1. 7.6.1 Memory Map
      2. 7.6.2 Register Descriptions
        1. 7.6.2.1  Standard SPI-3.0 (0x000 to 0x00F)
          1. Table 46. Standard SPI-3.0 Registers
          2. 7.6.2.1.1 Configuration A Register (address = 0x000) [reset = 0x30]
            1. Table 47. CONFIG_A Field Descriptions
          3. 7.6.2.1.2 Device Configuration Register (address = 0x002) [reset = 0x00]
            1. Table 48. DEVICE_CONFIG Field Descriptions
          4. 7.6.2.1.3 Chip Type Register (address = 0x003) [reset = 0x03]
            1. Table 49. CHIP_TYPE Field Descriptions
          5. 7.6.2.1.4 Chip ID Register (address = 0x004 to 0x005) [reset = 0x0020]
            1. Table 50. CHIP_ID Field Descriptions
          6. 7.6.2.1.5 Chip Version Register (address = 0x006) [reset = 0x01]
            1. Table 51. CHIP_VERSION Field Descriptions
          7. 7.6.2.1.6 Vendor Identification Register (address = 0x00C to 0x00D) [reset = 0x0451]
            1. Table 52. VENDOR_ID Field Descriptions
        2. 7.6.2.2  User SPI Configuration (0x010 to 0x01F)
          1. 7.6.2.2.1 User SPI Configuration Register (address = 0x010) [reset = 0x00]
            1. Table 54. USR0 Field Descriptions
        3. 7.6.2.3  Miscellaneous Analog Registers (0x020 to 0x047)
          1. 7.6.2.3.1 Clock Control Register 0 (address = 0x029) [reset = 0x00]
            1. Table 56. CLK_CTRL0 Field Descriptions
          2. 7.6.2.3.2 Clock Control Register 1 (address = 0x02A) [reset = 0x00]
            1. Table 57. CLK_CTRL1 Field Descriptions
          3. 7.6.2.3.3 SYSREF Capture Position Register (address = 0x02C-0x02E) [reset = Undefined]
            1. Table 58. SYSREF_POS Field Descriptions
          4. 7.6.2.3.4 INA Full-Scale Range Adjust Register (address = 0x030-0x031) [reset = 0xA000]
            1. Table 59. FS_RANGE_A Field Descriptions
          5. 7.6.2.3.5 INB Full-Scale Range Adjust Register (address = 0x032-0x033) [reset = 0xA000]
            1. Table 60. FS_RANGE_B Field Descriptions
          6. 7.6.2.3.6 Internal Reference Bypass Register (address = 0x038) [reset = 0x00]
            1. Table 61. BG_BYPASS Field Descriptions
          7. 7.6.2.3.7 TMSTP± Control Register (address = 0x03B) [reset = 0x00]
            1. Table 62. TMSTP_CTRL Field Descriptions
        4. 7.6.2.4  Serializer Registers (0x048 to 0x05F)
          1. 7.6.2.4.1 Serializer Pre-Emphasis Control Register (address = 0x048) [reset = 0x00]
            1. Table 64. SER_PE Field Descriptions
        5. 7.6.2.5  Calibration Registers (0x060 to 0x0FF)
          1. 7.6.2.5.1  Input Mux Control Register (address = 0x060) [reset = 0x01]
            1. Table 66. INPUT_MUX Field Descriptions
          2. 7.6.2.5.2  Calibration Enable Register (address = 0x061) [reset = 0x01]
            1. Table 67. CAL_EN Field Descriptions
          3. 7.6.2.5.3  Calibration Configuration 0 Register (address = 0x062) [reset = 0x01]
            1. Table 68. CAL_CFG0 Field Descriptions
          4. 7.6.2.5.4  Calibration Status Register (address = 0x06A) [reset = Undefined]
            1. Table 69. CAL_STATUS Field Descriptions
          5. 7.6.2.5.5  Calibration Pin Configuration Register (address = 0x06B) [reset = 0x00]
            1. Table 70. CAL_PIN_CFG Field Descriptions
          6. 7.6.2.5.6  Calibration Software Trigger Register (address = 0x06C) [reset = 0x01]
            1. Table 71. CAL_SOFT_TRIG Field Descriptions
          7. 7.6.2.5.7  Low-Power Background Calibration Register (address = 0x06E) [reset = 0x88]
            1. Table 72. CAL_LP Field Descriptions
          8. 7.6.2.5.8  Calibration Data Enable Register (address = 0x070) [reset = 0x00]
            1. Table 73. CAL_DATA_EN Field Descriptions
          9. 7.6.2.5.9  Calibration Data Register (address = 0x071) [reset = Undefined]
            1. Table 74. CAL_DATA Field Descriptions
          10. 7.6.2.5.10 Channel A Gain Trim Register (address = 0x07A) [reset = Undefined]
            1. Table 75. GAIN_TRIM_A Field Descriptions
          11. 7.6.2.5.11 Channel B Gain Trim Register (address = 0x07B) [reset = Undefined]
            1. Table 76. GAIN_TRIM_B Field Descriptions
          12. 7.6.2.5.12 Band-Gap Reference Trim Register (address = 0x07C) [reset = Undefined]
            1. Table 77. BG_TRIM Field Descriptions
          13. 7.6.2.5.13 VINA Input Resistor Trim Register (address = 0x07E) [reset = Undefined]
            1. Table 78. RTRIM_A Field Descriptions
          14. 7.6.2.5.14 VINB Input Resistor Trim Register (address = 0x07F) [reset = Undefined]
            1. Table 79. RTRIM_B Field Descriptions
          15. 7.6.2.5.15 Timing Adjust for A-ADC, Single-Channel Mode, Foreground Calibration Register (address = 0x080) [reset = Undefined]
            1. Table 80. TADJ_A_FG90 Field Descriptions
          16. 7.6.2.5.16 Timing Adjust for B-ADC, Single-Channel Mode, Foreground Calibration Register (address = 0x081) [reset = Undefined]
            1. Table 81. TADJ_B_FG0 Field Descriptions
          17. 7.6.2.5.17 Timing Adjust for A-ADC, Single-Channel Mode, Background Calibration Register (address = 0x082) [reset = Undefined]
            1. Table 82. TADJ_B_FG0 Field Descriptions
          18. 7.6.2.5.18 Timing Adjust for C-ADC, Single-Channel Mode, Background Calibration Register (address = 0x083) [reset = Undefined]
            1. Table 83. TADJ_B_FG0 Field Descriptions
          19. 7.6.2.5.19 Timing Adjust for C-ADC, Single-Channel Mode, Background Calibration Register (address = 0x084) [reset = Undefined]
            1. Table 84. TADJ_B_FG0 Field Descriptions
          20. 7.6.2.5.20 Timing Adjust for B-ADC, Single-Channel Mode, Background Calibration Register (address = 0x085) [reset = Undefined]
            1. Table 85. TADJ_B_FG0 Field Descriptions
          21. 7.6.2.5.21 Timing Adjust for A-ADC, Dual-Channel Mode Register (address = 0x086) [reset = Undefined]
            1. Table 86. TADJ_A Field Descriptions
          22. 7.6.2.5.22 Timing Adjust for C-ADC Acting for A-ADC, Dual-Channel Mode Register (address = 0x087) [reset = Undefined]
            1. Table 87. TADJ_CA Field Descriptions
          23. 7.6.2.5.23 Timing Adjust for C-ADC Acting for B-ADC, Dual-Channel Mode Register (address = 0x088) [reset = Undefined]
            1. Table 88. TADJ_CB Field Descriptions
          24. 7.6.2.5.24 Timing Adjust for B-ADC, Dual-Channel Mode Register (address = 0x089) [reset = Undefined]
            1. Table 89. TADJ_B Field Descriptions
          25. 7.6.2.5.25 Offset Adjustment for A-ADC and INA Register (address = 0x08A-0x08B) [reset = Undefined]
            1. Table 90. OADJ_A_INA Field Descriptions
          26. 7.6.2.5.26 Offset Adjustment for A-ADC and INB Register (address = 0x08C-0x08D) [reset = Undefined]
            1. Table 91. OADJ_A_INB Field Descriptions
          27. 7.6.2.5.27 Offset Adjustment for C-ADC and INA Register (address = 0x08E-0x08F) [reset = Undefined]
            1. Table 92. OADJ_C_INA Field Descriptions
          28. 7.6.2.5.28 Offset Adjustment for C-ADC and INB Register (address = 0x090-0x091) [reset = Undefined]
            1. Table 93. OADJ_C_INB Field Descriptions
          29. 7.6.2.5.29 Offset Adjustment for B-ADC and INA Register (address = 0x092-0x093) [reset = Undefined]
            1. Table 94. OADJ_B_INA Field Descriptions
          30. 7.6.2.5.30 Offset Adjustment for B-ADC and INB Register (address = 0x094-0x095) [reset = Undefined]
            1. Table 95. OADJ_B_INB Field Descriptions
          31. 7.6.2.5.31 Offset Filtering Control 0 Register (address = 0x097) [reset = 0x00]
            1. Table 96. OSFILT0 Field Descriptions
          32. 7.6.2.5.32 Offset Filtering Control 1 Register (address = 0x098) [reset = 0x33]
            1. Table 97. OSFILT1 Field Descriptions
        6. 7.6.2.6  ADC Bank Registers (0x100 to 0x15F)
          1. 7.6.2.6.1  Timing Adjustment for Bank 0 (0° Clock) Register (address = 0x102) [reset = Undefined]
            1. Table 99. B0_TIME_0 Field Descriptions
          2. 7.6.2.6.2  Timing Adjustment for Bank 0 (–90° Clock) Register (address = 0x103) [reset = Undefined]
            1. Table 100. B0_TIME_90 Field Descriptions
          3. 7.6.2.6.3  Timing Adjustment for Bank 1 (0° Clock) Register (address = 0x112) [reset = Undefined]
            1. Table 101. B1_TIME_0 Field Descriptions
          4. 7.6.2.6.4  Timing Adjustment for Bank 1 (–90° Clock) Register (address = 0x113) [reset = Undefined]
            1. Table 102. B1_TIME_90 Field Descriptions
          5. 7.6.2.6.5  Timing Adjustment for Bank 2 (0° Clock) Register (address = 0x122) [reset = Undefined]
            1. Table 103. B2_TIME_0 Field Descriptions
          6. 7.6.2.6.6  Timing Adjustment for Bank 2 (–90° Clock) Register (address = 0x123) [reset = Undefined]
            1. Table 104. B2_TIME_90 Field Descriptions
          7. 7.6.2.6.7  Timing Adjustment for Bank 3 (0° Clock) Register (address = 0x132) [reset = Undefined]
            1. Table 105. B3_TIME_0 Field Descriptions
          8. 7.6.2.6.8  Timing Adjustment for Bank 3 (–90° Clock) Register (address = 0x133) [reset = Undefined]
            1. Table 106. B3_TIME_90 Field Descriptions
          9. 7.6.2.6.9  Timing Adjustment for Bank 4 (0° Clock) Register (address = 0x142) [reset = Undefined]
            1. Table 107. B4_TIME_0 Field Descriptions
          10. 7.6.2.6.10 Timing Adjustment for Bank 4 (–90° Clock) Register (address = 0x143) [reset = Undefined]
            1. Table 108. B4_TIME_90 Field Descriptions
          11. 7.6.2.6.11 Timing Adjustment for Bank 5 (0° Clock) Register (address = 0x152) [reset = Undefined]
            1. Table 109. B5_TIME_0 Field Descriptions
          12. 7.6.2.6.12 Timing Adjustment for Bank 5 (–90° Clock) Register (address = 0x153) [reset = Undefined]
            1. Table 110. B5_TIME_90 Field Descriptions
        7. 7.6.2.7  LSB Control Registers (0x160 to 0x1FF)
          1. 7.6.2.7.1 LSB Control Bit Output Register (address = 0x160) [reset = 0x00]
            1. Table 112. ENC_LSB Field Descriptions
        8. 7.6.2.8  JESD204B Registers (0x200 to 0x20F)
          1. 7.6.2.8.1  JESD204B Enable Register (address = 0x200) [reset = 0x01]
            1. Table 114. JESD_EN Field Descriptions
          2. 7.6.2.8.2  JESD204B Mode Register (address = 0x201) [reset = 0x02]
            1. Table 115. JMODE Field Descriptions
          3. 7.6.2.8.3  JESD204B K Parameter Register (address = 0x202) [reset = 0x1F]
            1. Table 116. KM1 Field Descriptions
          4. 7.6.2.8.4  JESD204B Manual SYNC Request Register (address = 0x203) [reset = 0x01]
            1. Table 117. JSYNC_N Field Descriptions
          5. 7.6.2.8.5  JESD204B Control Register (address = 0x204) [reset = 0x02]
            1. Table 118. JCTRL Field Descriptions
          6. 7.6.2.8.6  JESD204B Test Pattern Control Register (address = 0x205) [reset = 0x00]
            1. Table 119. JTEST Field Descriptions
          7. 7.6.2.8.7  JESD204B DID Parameter Register (address = 0x206) [reset = 0x00]
            1. Table 120. DID Field Descriptions
          8. 7.6.2.8.8  JESD204B Frame Character Register (address = 0x207) [reset = 0x00]
            1. Table 121. FCHAR Field Descriptions
          9. 7.6.2.8.9  JESD204B, System Status Register (address = 0x208) [reset = Undefined]
            1. Table 122. JESD_STATUS Field Descriptions
          10. 7.6.2.8.10 JESD204B Channel Power-Down Register (address = 0x209) [reset = 0x00]
            1. Table 123. PD_CH Field Descriptions
          11. 7.6.2.8.11 JESD204B Extra Lane Enable (Link A) Register (address = 0x20A) [reset = 0x00]
            1. Table 124. JESD204B Extra Lane Enable (Link A) Field Descriptions
          12. 7.6.2.8.12 JESD204B Extra Lane Enable (Link B) Register (address = 0x20B) [reset = 0x00]
            1. Table 125. JESD204B Extra Lane Enable (Link B) Field Descriptions
        9. 7.6.2.9  Digital Down Converter Registers (0x210-0x2AF)
          1. 7.6.2.9.1  DDC Configuration Register (address = 0x210) [reset = 0x00]
            1. Table 127. DDC_CFG Field Descriptions
          2. 7.6.2.9.2  Overrange Threshold 0 Register (address = 0x211) [reset = 0xF2]
            1. Table 128. OVR_T0 Field Descriptions
          3. 7.6.2.9.3  Overrange Threshold 1 Register (address = 0x212) [reset = 0xAB]
            1. Table 129. OVR_T1 Field Descriptions
          4. 7.6.2.9.4  Overrange Configuration Register (address = 0x213) [reset = 0x07]
            1. Table 130. OVR_CFG Field Descriptions
          5. 7.6.2.9.5  DDC Configuration Preset Mode Register (address = 0x214) [reset = 0x00]
            1. Table 131. CMODE Field Descriptions
          6. 7.6.2.9.6  DDC Configuration Preset Select Register (address = 0x215) [reset = 0x00]
            1. Table 132. CSEL Field Descriptions
          7. 7.6.2.9.7  Digital Channel Binding Register (address = 0x216) [reset = 0x02]
            1. Table 133. DIG_BIND Field Descriptions
          8. 7.6.2.9.8  Rational NCO Reference Divisor Register (address = 0x217 to 0x218) [reset = 0x0000]
            1. Table 134. NCO_RDIV Field Descriptions
          9. 7.6.2.9.9  NCO Synchronization Register (address = 0x219) [reset = 0x02]
            1. Table 135. NCO_SYNC Field Descriptions
          10. 7.6.2.9.10 NCO Frequency (DDC A or DDC B and Preset x) Register (address = see ) [reset = see ]
            1. Table 136. FREQAx or FREQBx Field Descriptions
          11. 7.6.2.9.11 NCO Phase (DDC A or DDC B and Preset x) Register (address = see ) [reset = see ]
            1. Table 137. PHASEAx or PHASEBx Field Descriptions
        10. 7.6.2.10 Spin Identification Register (address = 0x297) [reset = Undefined]
          1. Table 138. SPIN_ID Field Descriptions
      3. 7.6.3 SYSREF Calibration Registers (0x2B0 to 0x2BF)
        1. 7.6.3.1 SYSREF Calibration Enable Register (address = 0x2B0) [reset = 0x00]
          1. Table 140. SRC_EN Field Descriptions
        2. 7.6.3.2 SYSREF Calibration Configuration Register (address = 0x2B1) [reset = 0x05]
          1. Table 141. SRC_CFG Field Descriptions
        3. 7.6.3.3 SYSREF Calibration Status Register (address = 0x2B2 to 0x2B4) [reset = Undefined]
          1. Table 142. SRC_STATUS Field Descriptions
        4. 7.6.3.4 DEVCLK Aperture Delay Adjustment Register (address = 0x2B5 to 0x2B7) [reset = 0x000000]
          1. Table 143. TAD Field Descriptions
        5. 7.6.3.5 DEVCLK Timing Adjust Ramp Control Register (address = 0x2B8) [reset = 0x00]
          1. Table 144. TAD_RAMP Field Descriptions
      4. 7.6.4 Alarm Registers (0x2C0 to 0x2C2)
        1. 7.6.4.1 Alarm Interrupt Register (address = 0x2C0) [reset = Undefined]
          1. Table 146. ALARM Field Descriptions
        2. 7.6.4.2 Alarm Status Register (address = 0x2C1) [reset = 0x1F]
          1. Table 147. ALM_STATUS Field Descriptions
        3. 7.6.4.3 Alarm Mask Register (address = 0x2C2) [reset = 0x1F]
          1. Table 148. ALM_MASK Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
    2. 8.2 Typical Applications
      1. 8.2.1 Wideband RF Sampling Receiver
        1. 8.2.1.1 Design Requirements
          1. 8.2.1.1.1 Input Signal Path
          2. 8.2.1.1.2 Clocking
        2. 8.2.1.2 Detailed Design Procedure
          1. 8.2.1.2.1 Calculating Values of AC-Coupling Capacitors
        3. 8.2.1.3 Application Curves
      2. 8.2.2 Reconfigurable Dual-Channel 2.5-GSPS or Single-Channel 5.0-Gsps Oscilloscope
        1. 8.2.2.1 Design Requirements
          1. 8.2.2.1.1 Input Signal Path
          2. 8.2.2.1.2 Clocking
          3. 8.2.2.1.3 ADC12DJ2700
        2. 8.2.2.2 Application Curves
    3. 8.3 Initialization Set Up
  9. 9 Power Supply Recommendations
    1. 9.1 Power Sequencing
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方产品免责声明
      2. 11.1.2 开发支持
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 支持资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 Glossary
  12. 12机械、封装和可订购信息
  13. 重要声明
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DATA SHEET

ADC12DJ2700 5.4GSPS 单通道或 2.7GSPS 双通道 12 位射频采样模数转换器 (ADC)

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • ADC 内核：
    • 12 位分辨率
    • 单通道模式下采样率高达 5.4GSPS
    • 双通道模式下采样率高达 2.7GSPS
  • 性能规格：
    • 本底噪声（无信号，VFS = 1.0VPP-DIFF）：
      • 双通道模式：–151.6dBFS/Hz
      • 单通道模式：–153.8dBFS/Hz
    • HD2、HD3：–65dBc，高达 3GHz
  • VCMI 为 0V 时的缓冲模拟输入：
    • 模拟输入带宽 (-3dB)：8.0GHz
    • 可用输入频率范围：>10GHz
    • 满量程输入电压（VFS，默认值）：0.8VPP
    • 模拟输入共模电压 (VICM)：0V
  • 无噪声孔径延迟 (TAD) 调节：
    • 采样精度控制：19fs 步长
    • 简化同步和交错
    • 温度和电压不变延迟
  • 简便易用的同步 特性：
    • 自动 SYSREF 计时校准
    • 样片标记时间戳
  • JESD204B 串行数据接口：
    • 支持子类 0 和 1
    • 最大通道速率：12.8Gbps
    • 多达 16 个通道可降低通道速率
  • 双通道模式下的数字下变频器：
    • 实际输出：DDC 旁路或双倍抽取
    • 复杂输出：4 倍、8 倍或 16 倍抽取
    • 每个 DDC 均具有四个独立的 32 位 NCO
  • 功耗：2.7W
  • 电源电压：1.1V、1.9V

    • ADC12DJ2700 测量的输入带宽

    ADC12DJ2700 D_BW_1stPage_SLVSD97.gif

2 应用

  • 通信测试仪（802.11ad，5G）
  • 卫星通信 (SATCOM)
  • 相控阵雷达、信号情报和电子情报
  • 合成孔径雷达 (SAR)
  • 飞行时间和激光雷达测距
  • 示波器和宽带数字转换器
  • 微波回程连线
  • 射频采样软件定义无线电 (SDR)
  • 光谱测量

3 说明

ADC12DJ2700 器件是一款射频采样千兆采样模数转换器 (ADC)，可对从直流到 10GHz 以上的输入频率进行直接采样。在双通道下，ADC12DJ2700 的最大采样率为 2700MSPS，单通道模式下的最大采样率为 5400MSPS。通道数（双通道模式）和奎斯特带宽（单通道模式）的可编程交换功能可用于开发灵活的硬件，以满足高通道数或宽瞬时信号带宽 应用的需求。8.0GHz 的全功率输入带宽 (-3dB)，可用频率在双通道和单通道模式下均超过 -3dB，可对频率捷变系统的 L、S、C 和 X 频带进行直接射频采样。

ADC12DJ2700 采用具有多达 16 个串行通道和子类 1 兼容性的高速 JESD204B 输出接口，可实现确定性延迟和多器件同步。串行输出通道支持高达 12.8Gbps 的速率，并可配置交换位速率和通道数。 创新同步 具有无噪声孔径延迟 (TAD) 调节和 SYSREF 窗口等创新的同步特性，简化了相控阵雷达和 MIMO 通信的系统设计。 采用双通道模式的可选数字下变频器 (DDC) 可以降低接口速率（实际和复杂抽取模式），支持数字化信号混合（仅复杂抽取模式）。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
ADC12DJ2700 FCBGA (144) 10.00mm × 10.00mm
  1. 如需了解所有可用封装，请参见数据表末尾的封装选项附录。

4 修订历史记录

Changes from * Revision (January 2018) to A Revision

  • Changed Pin Functions table listed in alphanumeric order by pin name.Go
  • Deleted reference to footnote below the Pin Functions table and moved the information to the Power-Down Mode section.Go
  • Added Operating free-air temperature parameter to Absolute Maximum Ratings tableGo
  • Added Storage temperature parameter to Recommended Operating Conditions tableGo
  • Changed FFT plots in Typical Characteristics section to show improved look Go
  • Changed product description in Overview section Go
  • Changed Device Comparison section to include all devices in the family.Go
  • Changed location of Analog Reference Voltage section. Go
  • Changed location of Temperature Monitoring Diode section. Go
  • Added requirement for at least 3 rising edges of SYSREF before SYSREF_POS output is valid.Go
  • Added clarification of NCO synchronization using DC-coupled SYSREF.Go
  • Added clarification of NCO synchronization using AC-coupled SYSREF.Go
  • Changed note in Power-Down Modes section to caution note explaining reliable serializer operation instead of the information being presented under the Pin Functions table.Go
  • Changed the Low-Power Background Calibration (LPBG) Mode section to provide additional detail of how to operate the device in low-power background calibration mode.Go
  • Added clarity about offset calibration when both CAL_OS and CAL_BG are enabled. Go
  • Changed Trimming section to limit trimming to foreground (FG) calibration mode only to better reflect customer use cases and simplify the explanation..Go
  • Changed additional clarity to Offset Filtering section to explain the frequency domain impact of the feature.Go
  • Added ADC12DJ2700 Access Type Codes tableGo
  • Added Reconfigurable Dual-Channel 2.5-GSPS or Single-Channel 5.0-Gsps Oscilloscope sectionGo
  • Changed Top Layer Routing: Analog Inputs, CLK and SYSREF, DA0-3, DB0-3 to Bottom Layer Routing: Additional CLK Routing, DA4-7, DB4-7 figures Go

5 Pin Configuration and Functions

AAV Package
144-Ball Flip Chip BGA
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
AGND A1, A2, A3, A6, A7, B2, B3, B4, B5, B6, B7, C6, D1, D6, E1, E6, F2, F3, F6, G2, G3, G6, H1, H6, J1, J6, L2, L3, L4, L5, L6, L7, M1, M2, M3, M6, M7 — Analog supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
BG C3 O Band-gap voltage output. This pin is capable of sourcing only small currents and driving limited capacitive loads, as specified in the Recommended Operating Conditions table. This pin can be left disconnected if not used.
CALSTAT F7 O Foreground calibration status output or device alarm output. Functionality is programmed through CAL_STATUS_SEL. This pin can be left disconnected if not used.
CALTRIG E7 I Foreground calibration trigger input. This pin is only used if hardware calibration triggering is selected in CAL_TRIG_EN, otherwise software triggering is performed using CAL_SOFT_TRIG. Tie this pin to GND if not used.
CLK+ F1 I Device (sampling) clock positive input. The clock signal is strongly recommended to be AC-coupled to this input for best performance. In single-channel mode, the analog input signal is sampled on both the rising and falling edges. In dual-channel mode, the analog signal is sampled on the rising edge. This differential input has an internal untrimmed 100-Ω differential termination and is self-biased to the optimal input common-mode voltage as long as DEVCLK_LVPECL_EN is set to 0.
CLK– G1 I Device (sampling) clock negative input. TI strongly recommends using AC-coupling for best performance.
DA0+ E12 O High-speed serialized data output for channel A, lane 0, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA0– F12 O High-speed serialized data output for channel A, lane 0, negative connection. This pin can be left disconnected if not used.
DA1+ C12 O High-speed serialized data output for channel A, lane 1, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA1– D12 O High-speed serialized data output for channel A, lane 1, negative connection. This pin can be left disconnected if not used.
DA2+ A10 O High-speed serialized-data output for channel A, lane 2, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA2– A11 O High-speed serialized-data output for channel A, lane 2, negative connection. This pin can be left disconnected if not used.
DA3+ A8 O High-speed serialized-data output for channel A, lane 3, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA3– A9 O High-speed serialized-data output for channel A, lane 3, negative connection. This pin can be left disconnected if not used.
DA4+ E11 O High-speed serialized data output for channel A, lane 4, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA4– F11 O High-speed serialized data output for channel A, lane 4, negative connection. This pin can be left disconnected if not used.
DA5+ C11 O High-speed serialized data output for channel A, lane 5, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA5– D11 O High-speed serialized data output for channel A, lane 5, negative connection. This pin can be left disconnected if not used.
DA6+ B10 O High-speed serialized data output for channel A, lane 6, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA6– B11 O High-speed serialized data output for channel A, lane 6, negative connection. This pin can be left disconnected if not used.
DA7+ B8 O High-speed serialized data output for channel A, lane 7, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DA7– B9 O High-speed serialized data output for channel A, lane 7, negative connection. This pin can be left disconnected if not used.
DB0+ H12 O High-speed serialized data output for channel B, lane 0, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB0– G12 O High-speed serialized data output for channel B, lane 0, negative connection. This pin can be left disconnected if not used.
DB1+ K12 O High-speed serialized data output for channel B, lane 1, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB1– J12 O High-speed serialized data output for channel B, lane 1, negative connection. This pin can be left disconnected if not used.
DB2+ M10 O High-speed serialized data output for channel B, lane 2, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB2– M11 O High-speed serialized data output for channel B, lane 2, negative connection. This pin can be left disconnected if not used.
DB3+ M8 O High-speed serialized data output for channel B, lane 3, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB3– M9 O High-speed serialized data output for channel B, lane 3, negative connection. This pin can be left disconnected if not used.
DB4+ H11 O High-speed serialized data output for channel B, lane 4, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB4– G11 O High-speed serialized data output for channel B, lane 4, negative connection. This pin can be left disconnected if not used.
DB5+ K11 O High-speed serialized data output for channel B, lane 5, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB5– J11 O High-speed serialized data output for channel B, lane 5, negative connection. This pin can be left disconnected if not used.
DB6+ L10 O High-speed serialized data output for channel B, lane 6, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB6– L11 O High-speed serialized data output for channel B, lane 6, negative connection. This pin can be left disconnected if not used.
DB7+ L8 O High-speed serialized data output for channel B, lane 7, positive connection. This differential output must be AC-coupled and must always be terminated with a 100-Ω differential termination at the receiver. This pin can be left disconnected if not used.
DB7– L9 O High-speed serialized data output for channel B, lane 7, negative connection. This pin can be left disconnected if not used.
DGND A12, B12, D9, D10, F9, F10, G9, G10, J9, J10, L12, M12 — Digital supply ground. Tie AGND and DGND to a common ground plane (GND) on the circuit board.
INA+ A4 I Channel A analog input positive connection. INA± is recommended for use in single channel mode for optimal performance. The differential full-scale input voltage is determined by the FS_RANGE_A register (see the Full-Scale Voltage (VFS) Adjustment section). This input is terminated to ground through a 50-Ω termination resistor. The input common-mode voltage is typically be set to 0 V (GND) and must follow the recommendations in the Recommended Operating Conditions table. This pin can be left disconnected if not used.
INA– A5 I Channel A analog input negative connection. INA± is recommended for use in single channel mode for optimal performance. See INA+ (pin A4) for detailed description. This input is terminated to ground through a 50-Ω termination resistor. This pin can be left disconnected if not used.
INB+ M4 I Channel B analog input positive connection. INA± is recommended for use in single channel mode for optimal performance. The differential full-scale input voltage is determined by the FS_RANGE_B register (see the Full-Scale Voltage (VFS) Adjustment section). This input is terminated to ground through a 50-Ω termination resistor. The input common-mode voltage is typically be set to 0 V (GND) and must follow the recommendations in the Recommended Operating Conditions table. This pin can be left disconnected if not used.
INB– M5 I Channel B analog input negative connection. INA± is recommended for use in single channel mode for optimal performance. See INA+ (pin A4) for detailed description. This input is terminated to ground through a 50-Ω termination resistor. This pin can be left disconnected if not used.
NCOA0 C7 I LSB of NCO selection control for DDC A. NCOA0 and NCOA1 select which NCO, of a possible four NCOs, is used for digital mixing when using a complex output JMODE. The remaining unselected NCOs continue to run to maintain phase coherency and can be swapped in by changing the values of NCOA0 and NCOA1 (when CMODE = 1). This pin is an asynchronous input. See the NCO Fast Frequency Hopping (FFH) and NCO Selection sections for more information. Tie this pin to GND if not used.
NCOA1 D7 I MSB of NCO selection control for DDC A. Tie this pin to GND if not used.
NCOB0 K7 I LSB of NCO selection control for DDC B. NCOB0 and NCOB1 select which NCO, of a possible four NCOs, is used for digital mixing when using a complex output JMODE. The remaining unselected NCOs continue to run to maintain phase coherency and can be swapped in by changing the values of NCOB0 and NCOB1 (when CMODE = 1). This pin is an asynchronous input. See the NCO Fast Frequency Hopping (FFH) and NCO Selection sections for more information. Tie this pin to GND if not used.
NCOB1 J7 I MSB of NCO selection control for DDC B. Tie this pin to GND if not used.
ORA0 C8 O Fast overrange detection status for channel A for the OVR_T0 threshold. When the analog input exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can be left disconnected if not used.
ORA1 D8 O Fast overrange detection status for channel A for the OVR_T1 threshold. When the analog input exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can be left disconnected if not used.
ORB0 K8 O Fast overrange detection status for channel B for the OVR_T0 threshold. When the analog input exceeds the threshold programmed into OVR_T0, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can be left disconnected if not used.
ORB1 J8 O Fast overrange detection status for channel B for the OVR_T1 threshold. When the analog input exceeds the threshold programmed into OVR_T1, this status indicator goes high. The minimum pulse duration is set by OVR_N. See the ADC Overrange Detection section for more information. This pin can be left disconnected if not used.
PD K6 I This pin disables all analog circuits and serializer outputs when set high for temperature diode calibration only. Do not use this pin to power down the device for power savings. Tie this pin to GND during normal operation. For information regarding reliable serializer operation, see the Power-Down Modes section.
SCLK F8 I Serial interface clock. This pin functions as the serial-interface clock input that clocks the serial programming data in and out. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1-V to 1.9-V CMOS levels.
SCS E8 I Serial interface chip select active low input. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1-V to 1.9-V CMOS levels. This pin has a 82-kΩ pullup resistor to VD11.
SDI G8 I Serial interface data input. The Using the Serial Interface section describes the serial interface in more detail. Supports 1.1-V to 1.9-V CMOS levels.
SDO H8 O Serial interface data output. The Using the Serial Interface section describes the serial interface in more detail. This pin is high impedance during normal device operation. This pin outputs 1.9-V CMOS levels during serial interface read operations. This pin can be left disconnected if not used.
SYNCSE C2 I Single-ended JESD204B SYNC signal. This input is an active low input that is used to initialize the JESD204C serial link in 8B/10B modes when SYNC_SEL is set to 0. When toggled low this input initiates code group synchronization (see the Code Group Synchronization (CGS) section). After code group synchronization, this input must be toggled high to start the initial lane alignment sequence (see the Initial Lane Alignment Sequence (ILAS) section). A differential SYNC signal can be used instead by setting SYNC_SEL to 1 and using TMSTP± as a differential SYNC input. Tie this pin to GND if differential SYNC (TMSTP±) is used as the JESD204B SYNC signal.
SYSREF+ K1 I The SYSREF positive input is used to achieve synchronization and deterministic latency across the JESD204B interface. This differential input (SYSREF+ to SYSREF–) has an internal untrimmed 100-Ω differential termination and can be AC-coupled when SYSREF_LVPECL_EN is set to 0. This input is self-biased when SYSREF_LVPECL_EN is set to 0. The termination changes to 50 Ω to ground on each input pin (SYSREF+ and SYSREF–) and can be DC-coupled when SYSREF_LVPECL_EN is set to 1. This input is not self-biased when SYSREF_LVPECL_EN is set to 1 and must be biased externally to the input common-mode voltage range provided in the Recommended Operating Conditions table.
SYSREF– L1 I SYSREF negative input
TDIODE+ K2 I Temperature diode positive (anode) connection. An external temperature sensor can be connected to TDIODE+ and TDIODE– to monitor the junction temperature of the device. This pin can be left disconnected if not used.
TDIODE– K3 I Temperature diode negative (cathode) connection. This pin can be left disconnected if not used.
TMSTP+ B1 I Timestamp input positive connection or differential JESD204B SYNC positive connection. This input is a timestamp input, used to mark a specific sample, when TIMESTAMP_EN is set to 1. This differential input is used as the JESD204B SYNC signal input when SYNC_SEL is set 1. This input can be used as both a timestamp and differential SYNC input at the same time, allowing feedback of the SYNC signal using the timestamp mechanism. TMSTP± uses active low signaling when used as a JESD204B SYNC. For additional usage information, see theTimestamp section.
TMSTP_RECV_EN must be set to 1 to use this input. This differential input (TMSTP+ to TMSTP–) has an internal untrimmed 100-Ω differential termination and can be AC-coupled when TMSTP_LVPECL_EN is set to 0. The termination changes to 50 Ω to ground on each input pin (TMSTP+ and TMSTP–) and can be DC coupled when TMSTP_LVPECL_EN is set to 1. This pin is not self-biased and therefore must be externally biased for both AC- and DC-coupled configurations. The common-mode voltage must be within the range provided in the Recommended Operating Conditions table when both AC and DC coupled. This pin can be left disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for JESD204B SYNC and timestamp is not required.
TMSTP– C1 I Timestamp input positive connection or differential JESD204B SYNC negative connection. This pin can be left disconnected and disabled (TMSTP_RECV_EN = 0) if SYNCSE is used for JESD204B SYNC and timestamp is not required.
VA11 C5, D2, D3, D5, E5, F5, G5, H5, J2, J3, J5, K5 I 1.1-V analog supply
VA19 C4, D4, E2, E3, E4, F4, G4, H2, H3, H4, J4, K4 I 1.9-V analog supply
VD11 C9, C10, E9, E10, G7, H7, H9, H10, K9, K10 I 1.1-V digital supply

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
Supply voltage range VA19(2) –0.3 2.35 V
VA11(2) –0.3 1.32
VD11(3) –0.3 1.32
Voltage between VD11 and VA11 –1.32 1.32
Voltage between AGND and DGND –0.1 0.1 V
Pin voltage range DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–, TMSTP+, TMSTP–(3) –0.5 min(1.32, VD11+0.5) V
CLK+, CLK–, SYSREF+, SYSREF–(2) –0.5 min(1.32, VA11+0.5)
BG, TDIODE+, TDIODE–(2) –0.5 min(2.35, VA19+0.5)
INA+, INA–, INB+, INB–(2) –1 1
CALSTAT, CALTRIG, NCOA0, NCOA1, NCOB0, NCOB1, ORA0, ORA1, ORB0, ORB1, PD, SCLK, SCS, SDI, SDO, SYNCSE(2) –0.5 VA19+0.5
Peak input current (any input except INA+, INA–, INB+, INB–) –25 25 mA
Peak input current (INA+, INA–, INB+, INB–) –50 50 mA
Peak RF input power (INA+, INA–, INB+, INB–) Single-ended with ZS-SE = 50 Ω or differential with ZS-DIFF = 100 Ω 16.4 dBm
Peak total input current (sum of absolute value of all currents forced in or out, not including power-supply current) 100 mA
Operating free-air temperature, TA –40 85 °C
Operating junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Measured to AGND.
(3) Measured to DGND.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2500 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±1000
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Supply voltage range VA19, analog 1.9-V supply(2) 1.8 1.9 2.0 V
VA11, analog 1.1-V supply(2) 1.05 1.1 1.15
VD11, digital 1.1-V supply(3) 1.05 1.1 1.15
VCMI Input common-mode voltage INA+, INA–, INB+, INB–(2) –50 0 100 mV
CLK+, CLK–, SYSREF+, SYSREF–(2)(4) 0 0.3 0.55 V
TMSTP+, TMSTP–(2)(5) 0 0.3 0.55
VID Input voltage, peak-to-peak differential CLK+ to CLK–, SYSREF+ to SYSREF–, TMSTP+ to TMSTP– 0.4 1.0 2.0 VPP-DIFF
INA+ to INA–, INB+ to INB– 1.0(6)
VIH High-level input voltage CALTRIG, NCOA0, NCOA1, NCOB0, NCOB1, PD, SCLK, SCS, SDI, SYNCSE(2) 0.7 V
VIL Low-level input voltage CALTRIG, NCOA0, NCOA1, NCOB0, NCOB1, PD, SCLK, SCS, SDI, SYNCSE(2) 0.45 V
IC_TD Temperature diode input current TDIODE+ to TDIODE– 100 µA
CL BG maximum load capacitance 50 pF
IO BG maximum output current 100 µA
DC Input clock duty cycle 30% 50% 70%
TA Operating free-air temperature –40 85 °C
TJ Operating junction temperature 105(1)(7) °C
Tstg Storage temperature –65 150 °C
(1) Prolonged use above this junction temperature may increase the device failure-in-time (FIT) rate.
(2) Measured to AGND.
(3) Measured to DGND.
(4) TI strongly recommends that CLK± be AC-coupled with DEVCLK_LVPECL_EN set to 0 to allow CLK± to self-bias to the optimal input common-mode voltage for best performance. TI recommends AC-coupling for SYSREF± unless DC-coupling is required, in which case, the LVPECL input mode must be used (SYSREF_LVPECL_EN = 1).
(5) TMSTP± does not have internal biasing that requires TMSTP± to be biased externally whether AC-coupled with TMSTP_LVPECL_EN = 0 or DC-coupled with TMSTP_LVPECL_EN = 1.
(6) The ADC output code saturates when VID for INA± or INB± exceeds the programmed full-scale voltage (VFS) set by FS_RANGE_A for INA± or FS_RANGE_B for INB±.
(7) Tested up to 1000 hours continuous operation at Tj = 125°C. See the Absolute Maximum Ratings table for the absolute maximum operational temperature.

6.4 Thermal Information

THERMAL METRIC(1) ADC12DJ2700 UNIT
AAV (FCBGA)
144 PINS
RθJA Junction-to-ambient thermal resistance 25.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 1.1 °C/W
RθJB Junction-to-board thermal resistance 8.2 °C/W
ψJT Junction-to-top characterization parameter 0.1 °C/W
ψJB Junction-to-board characterization parameter 8.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics: DC Specifications

typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), input signal applied to INA± in single-channel modes, fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP sine-wave clock, JMODE = 1, and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DC ACCURACY
Resolution Resolution with no missing codes 12 Bits
DNL Differential nonlinearity Maximum positive excursion from ideal step size 0.7 LSB
Maximum negative excursion from ideal step size –0.3
INL Integral nonlinearity ±2.0 LSB
ANALOG INPUTS (INA+, INA–, INB+, INB–)
VOFF Offset error Default full-scale voltage, OS_CAL disabled ±0.6 mV
VOFF_ADJ Input offset voltage adjustment range Available offset correction range (see OS_CAL or OADJ_x_INx) ±55 mV
VOFF_DRIFT Offset drift Foreground calibration at nominal temperature only 23 µV/°C
Foreground calibration at each temperature 0
VIN_FSR Analog differential input full-scale range Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) 750 800 850 mVPP
Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) 1000 1040
Minimum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0x2000) 480 500
VIN_FSR_DRIFT Analog differential input full-scale range drift Default FS_RANGE_A and FS_RANGE_B setting, foreground calibration at nominal temperature only, inputs driven by a 50-Ω source, includes effect of RIN drift –0.01 %/°C
Default FS_RANGE_A and FS_RANGE_B setting, foreground calibration at each temperature, inputs driven by a 50-Ω source, includes effect of RIN drift 0.03
VIN_FSR_MATCH Analog differential input full-scale range matching Matching between INA+, INA– and INB+, INB–, default setting, dual-channel mode 0.625%
RIN Single-ended input resistance to AGND Each input pin is terminated to AGND, measured at TA = 25°C 48 50 52 Ω
RIN_TEMPCO Input termination linear temperature coefficient 17.6 mΩ/°C
CIN Single-ended input capacitance Single-channel mode at DC 0.4 pF
Dual-channel mode at DC 0.4
TEMPERATURE DIODE CHARACTERISTICS (TDIODE+, TDIODE–)
ΔVBE Temperature diode voltage slope Forced forward current of 100 µA. Offset voltage (approximately 0.792 V at 0°C) varies with process and must be measured for each part. Offset measurement must be done with the device unpowered or with the PD pin asserted to minimize device self-heating. The PD pin must be asserted only long enough to take the offset measurement. –1.6 mV/°C
BAND-GAP VOLTAGE OUTPUT (BG)
VBG Reference output voltage IL ≤ 100 µA 1.1 V
VBG_DRIFT Reference output temperature drift IL ≤ 100 µA –64 µV/°C
CLOCK INPUTS (CLK+, CLK–, SYSREF+, SYSREF–, TMSTP+, TMSTP–)
ZT Internal termination Differential termination with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0, and TMSTP_LVPECL_EN = 0 110 Ω
Single-ended termination to GND (per pin) with DEVCLK_LVPECL_EN = 0, SYSREF_LVPECL_EN = 0, and TMSTP_LVPECL_EN = 0 55
VCM Input common-mode voltage, self-biased Self-biasing common-mode voltage for CLK± when AC-coupled (DEVCLK_LVPECL_EN must be set to 0) 0.26 V
Self-biasing common-mode voltage for SYSREF± when AC-coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver enabled (SYSREF_RECV_EN = 1) 0.29
Self-biasing common-mode voltage for SYSREF± when AC-coupled (SYSREF_LVPECL_EN must be set to 0) and with receiver disabled (SYSREF_RECV_EN = 0) VA11
CL_DIFF Differential input capacitance Between positive and negative differential input pins 0.1 pF
CL_SE Single-ended input capacitance Each input to ground 0.5 pF
SERDES OUTPUTS (DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)
VOD Differential output voltage, peak-to-peak 100-Ω load 550 600 650 mVPP-DIFF
VCM Output common-mode voltage AC coupled VD11 / 2 V
ZDIFF Differential output impedance 100 Ω
CMOS INTERFACE: SCLK, SDI, SDO, SCS, PD, NCOA0, NCOA1, NCOB0, NCOB1, CALSTAT, CALTRIG, ORA0, ORA1, ORB0, ORB1, SYNCSE
IIH High-level input current –40 40 µA
IIL Low-level input current –40 40 µA
CI Input capacitance 2 pF
VOH High-level output voltage ILOAD = –400 µA 1.65 V
VOL Low-level output voltage ILOAD = 400 µA 150 mV

6.6 Electrical Characteristics: Power Consumption

typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), input signal applied to INA± in single-channel modes, fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP sine-wave clock, JMODE = 1, and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
IVA19 1.9-V analog supply current Power mode 1: single-channel mode, JMODE 1 (16 lanes, DDC bypassed), foreground calibration 884 mA
IVA11 1.1-V analog supply current 440 mA
IVD11 1.1-V digital supply current 529 mA
PDIS Power dissipation 2.7 W
IVA19 1.9-V analog supply current Power mode 2: single-channel mode, JMODE 0 (8 lanes, DDC bypassed), foreground calibration 884 950 mA
IVA11 1.1-V analog supply current 439 600 mA
IVD11 1.1-V digital supply current 569 750 mA
PDIS Power dissipation 2.8 3.5 W
IVA19 1.9-V analog supply current Power mode 3: single-channel mode, JMODE 1 (16 lanes, DDC bypassed), background calibration 1161 mA
IVA11 1.1-V analog supply current 525 mA
IVD11 1.1-V digital supply current 544 mA
PDIS Power dissipation 3.4 W
IVA19 1.9-V analog supply current Power mode 4: dual-channel mode, JMODE 3 (16 lanes, DDC bypassed), background calibration 1242 mA
IVA11 1.1-V analog supply current 524 mA
IVD11 1.1-V digital supply current 524 mA
PDIS Power dissipation 3.5 W
IVA19 1.9-V analog supply current Power mode 5: dual-channel mode, JMODE 11 (8 lanes, 4x decimation), foreground calibration 965 mA
IVA11 1.1-V analog supply current 439 mA
IVD11 1.1-V digital supply current 763 mA
PDIS Power dissipation 3.2 W

6.7 Electrical Characteristics: AC Specifications (Dual-Channel Mode)

typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP sine-wave clock, JMODE = 3, and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FPBW Full-power input bandwidth(1)
(–3 dB)		 Foreground calibration 8.1 GHz
Background calibration 8.1
XTALK Channel-to-channel crosstalk Aggressor = 400 MHz, –1 dBFS –93 dB
Aggressor = 3 GHz, –1 dBFS –70
Aggressor = 6 GHz, –1 dBFS –63
CER Code error rate 10–18 Errors/ sample
NOISEDC DC input noise standard deviation No input, foreground calibration, excludes DC offset, includes fixed interleaving spur (fS / 2 spur) 1.88 LSB
NSD Noise spectral density, no input signal, excludes fixed interleaving spur (fS / 2 spur) Maximum full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xFFFF) setting, foreground calibration –151.6 dBFS/Hz
Default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000) setting, foreground calibration –149.1
NF Noise figure, no input, ZS = 100 Ω Maximum full-scale voltage (FS_RANGE_A = 0xFFFF) setting, foreground calibration 23.7 dB
Default full-scale voltage (FS_RANGE_A = 0xA000) setting, foreground calibration 23.9
SNR Signal-to-noise ratio, large signal, excluding DC, HD2 to HD9 and interleaving spurs fIN = 347 MHz, AIN = –1 dBFS 56.8 dBFS
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration 57.7
fIN = 997 MHz, AIN = –1 dBFS 56.7
fIN = 2482 MHz, AIN = –1 dBFS 52 55.8
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration 56.6
fIN = 4997 MHz, AIN = –1 dBFS 53.5
fIN = 6397 MHz, AIN = –1 dBFS 52.3
fIN = 8197 MHz, AIN = –1 dBFS 50.8
SNR Signal-to-noise ratio, small signal, excluding DC, HD2 to HD9 and interleaving spurs fIN = 347 MHz, AIN = –16 dBFS 57.6 dBFS
fIN = 997 MHz, AIN = –16 dBFS 57.7
fIN = 2482 MHz, AIN = –16 dBFS 57.6
fIN = 4997 MHz, AIN = –16 dBFS 57.5
fIN = 6397 MHz, AIN = –16 dBFS 57.4
fIN = 8197 MHz, AIN = –16 dBFS 57.2
SINAD Signal-to-noise and distortion ratio, large signal, excluding DC and fS / 2 fixed spurs fIN = 347 MHz, AIN = –1 dBFS 56.0 dBFS
fIN = 997 MHz, AIN = –1 dBFS 56.0
fIN = 2482 MHz, AIN = –1 dBFS 51 55.1
fIN = 4997 MHz, AIN = –1 dBFS 51.1
fIN = 6397 MHz, AIN = –1 dBFS 49.3
fIN = 8197 MHz, AIN = –1 dBFS 47.0
ENOB Effective number of bits, large signal, excluding DC and fS / 2 fixed spurs fIN = 347 MHz, AIN = –1 dBFS 9.0 bits
fIN = 997 MHz, AIN = –1 dBFS 9.0
fIN = 2482 MHz, AIN = –1 dBFS 8.2 8.9
fIN = 4997 MHz, AIN = –1 dBFS 8.2
fIN = 6397 MHz, AIN = –1 dBFS 7.9
fIN = 8197 MHz, AIN = –1 dBFS 7.5
SFDR Spurious-free dynamic range, large signal, excluding DC and fS / 2 fixed spurs fIN = 347 MHz, AIN = –1 dBFS 70 dBFS
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration 70
fIN = 997 MHz, AIN = –1 dBFS 71
fIN = 2482 MHz, AIN = –1 dBFS 60 68
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration 63
fIN = 4997 MHz, AIN = –1 dBFS 59
fIN = 6397 MHz, AIN = –1 dBFS 56
fIN = 8197 MHz, AIN = –1 dBFS 54
SFDR Spurious-free dynamic range, small signal, excluding DC and fS / 2 fixed spurs fIN = 347 MHz, AIN = –16 dBFS 73 dBFS
fIN = 997 MHz, AIN = –16 dBFS 73
fIN = 2482 MHz, AIN = –16 dBFS 74
fIN = 4997 MHz, AIN = –16 dBFS 74
fIN = 6397 MHz, AIN = –16 dBFS 73
fIN = 8197 MHz, AIN = –16 dBFS 72
fS / 2 fS / 2 fixed interleaving spur, independent of input signal No input –70 –55 dBFS
HD2 2nd-order harmonic distortion fIN = 347 MHz, AIN = –1 dBFS –78 dBFS
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration –80
fIN = 997 MHz, AIN = –1 dBFS –77
fIN = 2482 MHz, AIN = –1 dBFS –72 –60
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration –73
fIN = 4997 MHz, AIN = –1 dBFS –67
fIN = 6397 MHz, AIN = –1 dBFS –63
fIN = 8197 MHz, AIN = –1 dBFS –59
HD3 3rd-order harmonic distortion fIN = 347 MHz, AIN = –1 dBFS –74 dBFS
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration –71
fIN = 997 MHz, AIN = –1 dBFS –76
fIN = 2482 MHz, AIN = –1 dBFS –68 –60
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A and FS_RANGE_B setting, foreground calibration –63
fIN = 4997 MHz, AIN = –1 dBFS –59
fIN = 6397 MHz, AIN = –1 dBFS –56
fIN = 8197 MHz, AIN = –1 dBFS –54
fS / 2-fIN fS / 2-fIN interleaving spur, signal dependent fIN = 347 MHz, AIN = –1 dBFS –72 dBFS
fIN = 997 MHz, AIN = –1 dBFS –74
fIN = 2482 MHz, AIN = –1 dBFS –75 –60
fIN = 4997 MHz, AIN = –1 dBFS –70
fIN = 6397 MHz, AIN = –1 dBFS –69
fIN = 8197 MHz, AIN = –1 dBFS –64
SPUR Worst-harmonic, 4th-order distortion or higher fIN = 347 MHz, AIN = –1 dBFS –77 dBFS
fIN = 997 MHz, AIN = –1 dBFS –78
fIN = 2482 MHz, AIN = –1 dBFS –78 –65
fIN = 4997 MHz, AIN = –1 dBFS –75
fIN = 6397 MHz, AIN = –1 dBFS –75
fIN = 8197 MHz, AIN = –1 dBFS –81
IMD3 3rd-order intermodulation distortion fIN = 347 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone		 –83 dBFS
fIN = 997 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone		 –84
fIN = 2497 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone		 –73
fIN = 4997 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone		 –63
fIN = 6397 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone		 –57
fIN = 7997 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone		 –49
(1) Full-power input bandwidth (FPBW) is defined as the input frequency where the reconstructed output of the ADC has dropped 3 dB below the power of a full-scale input signal at a low input frequency. Useable bandwidth may exceed the –3-dB, full-power input bandwidth.

6.8 Electrical Characteristics: AC Specifications (Single-Channel Mode)

typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = 0xA000), input signal applied to INA±, fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP sine-wave clock, JMODE = 1, and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
FPBW Full-power input bandwidth(1)
(–3 dB)		 Foreground calibration 7.9 GHz
Background calibration 7.9
CER Code error rate 10–18 Errors/ sample
NOISEDC DC input noise standard deviation No input, foreground calibration, excludes DC offset, includes fixed interleaving spurs (fS / 2 and fS / 4 spurs), OS_CAL enabled 1.95 LSB
NSD Noise spectral density, no input signal, excludes fixed interleaving spurs (fS / 2 and fS / 4 spur) Maximum full-scale voltage (FS_RANGE_A = 0xFFFF) setting, foreground calibration –153.8 dBFS/Hz
Default full-scale voltage (FS_RANGE_A = 0xA000) setting, foreground calibration –152.7
NF Noise figure, no input, ZS = 100 Ω Maximum full-scale voltage (FS_RANGE_A = 0xFFFF) setting, foreground calibration 21.5 dB
Default full-scale voltage (FS_RANGE_A = 0xA000) setting, foreground calibration 20.3
SNR Signal-to-noise ratio, large signal, excluding DC, HD2 to HD9 and interleaving spurs fIN = 347 MHz, AIN = –1 dBFS 56.8 dBFS
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration 57.6
fIN = 997 MHz, AIN = –1 dBFS 56.6
fIN = 2482 MHz, AIN = –1 dBFS 52 55.8
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration 56.6
fIN = 4997 MHz, AIN = –1 dBFS 53.6
fIN = 6397 MHz, AIN = –1 dBFS 52.4
fIN = 8197 MHz, AIN = –1 dBFS 50.9
SNR Signal-to-noise ratio, small signal, excluding DC, HD2 to HD9 and interleaving spurs fIN = 347 MHz, AIN = –16 dBFS 57.6 dBFS
fIN = 997 MHz, AIN = –16 dBFS 57.4
fIN = 2482 MHz, AIN = –16 dBFS 57.4
fIN = 4997 MHz, AIN = –16 dBFS 57.4
fIN = 6397 MHz, AIN = –16 dBFS 57.4
fIN = 8197 MHz, AIN = –16 dBFS 57.2
SINAD Signal-to-noise and distortion ratio, large signal, excluding DC and fS / 2 fixed spurs fIN = 347 MHz, AIN = –1 dBFS 55.2 dBFS
fIN = 997 MHz, AIN = –1 dBFS 54.3
fIN = 2482 MHz, AIN = –1 dBFS 48 53.6
fIN = 4997 MHz, AIN = –1 dBFS 50.4
fIN = 6397 MHz, AIN = –1 dBFS 48.2
fIN = 8197 MHz, AIN = –1 dBFS 45.7
ENOB Effective number of bits, large signal, excluding DC and fS / 2 fixed spurs fIN = 347 MHz, AIN = –1 dBFS 8.9 Bits
fIN = 997 MHz, AIN = –1 dBFS 8.7
fIN = 2482 MHz, AIN = –1 dBFS 7.7 8.6
fIN = 4997 MHz, AIN = –1 dBFS 8.1
fIN = 6397 MHz, AIN = –1 dBFS 7.7
fIN = 8197 MHz, AIN = –1 dBFS 7.3
SFDR Spurious free dynamic range, large signal, excluding DC, fS / 4 and fS / 2 fixed spurs fIN = 347 MHz, AIN = –1 dBFS 65 dBFS
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration 67
fIN = 997 MHz, AIN = –1 dBFS 61
fIN = 2482 MHz, AIN = –1 dBFS 50 59
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration 61
fIN = 4997 MHz, AIN = –1 dBFS 56
fIN = 6397 MHz, AIN = –1 dBFS 53
fIN = 8197 MHz, AIN = –1 dBFS 49
SFDR Spurious free dynamic range, small signal, excluding DC, fS / 4 and fS / 2 fixed spurs fIN = 347 MHz, AIN = –16 dBFS 75 dBFS
fIN = 997 MHz, AIN = –16 dBFS 74
fIN = 2482 MHz, AIN = –16 dBFS 74
fIN = 4997 MHz, AIN = –16 dBFS 71
fIN = 6397 MHz, AIN = –16 dBFS 67
fIN = 8197 MHz, AIN = –16 dBFS 64
fS / 2 fS / 2 fixed interleaving spur, independent of input signal No input, foreground calibration, OS_CAL disabled. Spur can be improved by running OS_CAL. –66 dBFS
fS / 4 fS / 4 fixed interleaving spur, independent of input signal No input –70 –55 dBFS
HD2 2nd-order harmonic distortion fIN = 347 MHz, AIN = –1 dBFS –74 dBFS
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration –73
fIN = 997 MHz, AIN = –1 dBFS –78
fIN = 2482 MHz, AIN = –1 dBFS –79 –60
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration –78
fIN = 4997 MHz, AIN = –1 dBFS –72
fIN = 6397 MHz, AIN = –1 dBFS –61
fIN = 8197 MHz, AIN = –1 dBFS –65
HD3 3rd-order harmonic distortion fIN = 347 MHz, AIN = –1 dBFS –71 dBFS
fIN = 347 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration –69
fIN = 997 MHz, AIN = –1 dBFS –72
fIN = 2482 MHz, AIN = –1 dBFS –68 –60
fIN = 2482 MHz, AIN = –1 dBFS, maximum FS_RANGE_A setting, foreground calibration –62
fIN = 4997 MHz, AIN = –1 dBFS –61
fIN = 6397 MHz, AIN = –1 dBFS –59
fIN = 8197 MHz, AIN = –1 dBFS –56
fS / 2 – fIN fS / 2 – fIN interleaving spur, signal dependent fIN = 347 MHz, AIN = –1 dBFS –65 dBFS
fIN = 997 MHz, AIN = –1 dBFS –61
fIN = 2482 MHz, AIN = –1 dBFS –59 –50
fIN = 4997 MHz, AIN = –1 dBFS –56
fIN = 6397 MHz, AIN = –1 dBFS –53
fIN = 8197 MHz, AIN = –1 dBFS –49
fS / 4 ± fIN fS / 4 ± fIN interleaving spurs, signal dependent fIN = 347 MHz, AIN = –1 dBFS –75 dBFS
fIN = 997 MHz, AIN = –1 dBFS –72
fIN = 2482 MHz, AIN = –1 dBFS –75 –60
fIN = 4997 MHz, AIN = –1 dBFS –69
fIN = 6397 MHz, AIN = –1 dBFS –69
fIN = 8197 MHz, AIN = –1 dBFS –65
SPUR Worst-harmonic, 4th-order distortion or higher fIN = 347 MHz, AIN = –1 dBFS –75 dBFS
fIN = 997 MHz, AIN = –1 dBFS –78
fIN = 2482 MHz, AIN = –1 dBFS –78 –65
fIN = 4997 MHz, AIN = –1 dBFS –72
fIN = 6397 MHz, AIN = –1 dBFS –72
fIN = 8197 MHz, AIN = –1 dBFS –79
IMD3 3rd-order intermodulation distortion fIN = 347 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone		 –90 dBFS
fIN = 997 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone		 –79
fIN = 2497 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone		 –73
fIN = 4997 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone		 –63
fIN = 6397 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone		 –58
fIN = 7997 MHz ± 2.5 MHz,
AIN = –7 dBFS per tone		 –51
(1) Full-power input bandwidth (FPBW) is defined as the input frequency where the reconstructed output of the ADC has dropped 3 dB below the power of a full-scale input signal at a low input frequency. Useable bandwidth may exceed the –3-dB, full-power input bandwidth.

6.9 Timing Requirements

MIN NOM MAX UNIT
DEVICE (SAMPLING) CLOCK (CLK+, CLK–)
fCLK Input clock frequency (CLK+, CLK–), both single-channel and dual-channel modes(1) 800 2700 MHz
SYSREF (SYSREF+, SYSREF–)
tINV(SYSREF) Width of invalid SYSREF capture region of CLK± period, indicating setup or hold time violation, as measured by SYSREF_POS status register(2) 48 ps
tINV(TEMP) Drift of invalid SYSREF capture region over temperature, positive number indicates a shift toward MSB of SYSREF_POS register 0 ps/°C
tINV(VA11) Drift of invalid SYSREF capture region over VA11 supply voltage, positive number indicates a shift toward MSB of SYSREF_POS register 0.36 ps/mV
tSTEP(SP) Delay of SYSREF_POS LSB SYSREF_ZOOM = 0 77 ps
SYSREF_ZOOM = 1 24
t(PH_SYS) Minimum SYSREF± assertion duration after SYSREF± rising edge event 4 ns
t(PL_SYS) Minimum SYSREF± de-assertion duration after SYSREF± falling edge event 1 ns
JESD204B SYNC TIMING (SYNCSE OR TMSTP±)
tH(SYNCSE) Minimum hold time from multiframe boundary (SYSREF rising edge captured high) to de-assertion of JESD204B SYNC signal (SYNCSE if SYNC_SEL = 0 or TMSTP± if SYNC_SEL = 1) for NCO synchronization (NCO_SYNC_ILA = 1) JMODE = 0, 2, 4, 6, 10, 13, or 15 21 tCLK cycles
JMODE = 1, 3, 5, 7, 9, 11, 14, or 16 17
JMODE = 12, 17, or 18 9
tSU(SYNCSE) Minimum setup time from de-assertion of JESD204B SYNC signal (SYNCSE if SYNC_SEL = 0 or TMSTP± if SYNC_SEL = 1) to multiframe boundary (SYSREF rising edge captured high) for NCO synchronization (NCO_SYNC_ILA = 1) JMODE = 0, 2, 4, 6, 10, 13, or 15 –2 tCLK cycles
JMODE = 1, 3, 5, 7, 9, 11, 14, or 16 2
JMODE = 12, 17, or 18 10
t(SYNCSE) SYNCSE minimum assertion time to trigger link resynchronization 4 Frames
SERIAL PROGRAMMING INTERFACE (SCLK, SDI, SCS)
fCLK(SCLK) Maximum serial clock frequency 15.625 MHz
t(PH) Minimum serial clock high value pulse duration 32 ns
t(PL) Minimum serial clock low value pulse duration 32 ns
tSU(SCS) Minimum setup time from SCS to rising edge of SCLK 30 ns
tH(SCS) Minimum hold time from rising edge of SCLK to SCS 3 ns
tSU(SDI) Minimum setup time from SDI to rising edge of SCLK 30 ns
tH(SDI) Minimum hold time from rising edge of SCLK to SDI 3 ns
(1) Unless functionally limited to a smaller range in Table 19 based on programmed JMODE.
(2) Use SYSREF_POS to select an optimal SYSREF_SEL value for the SYSREF capture, see the SYSREF Position Detector and Sampling Position Selection (SYSREF Windowing) section for more information on SYSREF windowing. The invalid region, specified by tINV(SYSREF), indicates the portion of the CLK± period (tCLK), as measured by SYSREF_SEL, that may result in a setup and hold violation. Verify that the timing skew between SYSREF± and CLK± over system operating conditions from the nominal conditions (that used to find optimal SYSREF_SEL) does not result in the invalid region occurring at the selected SYSREF_SEL position in SYSREF_POS, otherwise a temperature dependent SYSREF_SEL selection may be needed to track the skew between CLK± and SYSREF±.

6.10 Switching Characteristics

typical values at TA = 25°C, VA19 = 1.9 V, VA11 = 1.1 V, VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), input signal applied to INA± in single-channel modes, fIN = 248 MHz, AIN = –1 dBFS, fCLK = maximum rated clock frequency, filtered 1-VPP sine-wave clock, JMODE = 1, and background calibration (unless otherwise noted); minimum and maximum values are at nominal supply voltages and over the operating free-air temperature range provided in the Recommended Operating Conditions table
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
DEVICE (SAMPLING) CLOCK (CLK+, CLK–)
tAD Sampling (aperture) delay from the CLK± rising edge (dual-channel mode) or rising and falling edge (single-channel mode) to sampling instant TAD_COARSE = 0x00, TAD_FINE = 0x00, and TAD_INV = 0 360 ps
tTAD(MAX) Maximum tAD adjust programmable delay, not including clock inversion (TAD_INV = 0) Coarse adjustment (TAD_COARSE = 0xFF) 289 ps
Fine adjustment (TAD_FINE = 0xFF) 4.9 ps
tTAD(STEP) tAD adjust programmable delay step size Coarse adjustment (TAD_COARSE) 1.13 ps
Fine adjustment (TAD_FINE) 19 fs
tAJ Aperture jitter, rms Minimum tAD adjust coarse setting (TAD_COARSE = 0x00, TAD_INV = 0) 50 fs
Maximum tAD adjust coarse setting (TAD_COARSE = 0xFF) excluding TAD_INV (TAD_INV = 0) 70(3)
SERIAL DATA OUTPUTS (DA[7:0]+, DA[7:0]–, DB[7:0]+, DB[7:0]–)
fSERDES Serialized output bit rate 1 12.8 Gbps
UI Serialized output unit interval 78.125 1000 ps
tTLH Low-to-high transition time (differential) 20% to 80%, PRBS-7 test pattern, 12.8 Gbps, SER_PE = 0x04 37 ps
tTHL High-to-low transition time (differential) 20% to 80%, PRBS-7 test pattern, 12.8 Gbps, SER_PE = 0x04 37 ps
DDJ Data dependent jitter, peak-to-peak PRBS-7 test pattern, 12.8 Gbps, SER_PE = 0x04, JMODE = 2 7.8 ps
RJ Random jitter, RMS PRBS-7 test pattern, 12.8 Gbps, SER_PE = 0x04, JMODE = 2 1.1 ps
TJ Total jitter, peak-to-peak, with gaussian portion defined with respect to a BER = 1e-15 (Q = 7.94) PRBS-7 test pattern, 12.8 Gbps, SER_PE = 0x04, JMODE = 0, 2 25 ps
PRBS-7 test pattern, 6.4 Gbps, SER_PE = 0x04, JMODE = 1, 3 21
PRBS-7 test pattern, 8 Gbps, SER_PE = 0x04, JMODE = 4, 5, 6, 7 28
PRBS-7 test pattern, 8 Gbps, SER_PE = 0x04, JMODE = 9 35
PRBS-7 test pattern, 8 Gbps, SER_PE = 0x04, JMODE = 10, 11 40
PRBS-7 test pattern, 3.2 Gbps, SER_PE = 0x04, JMODE = 12 26
PRBS-7 test pattern, 8 Gbps, SER_PE = 0x04, JMODE = 13, 14 39
PRBS-7 test pattern, 8 Gbps, SER_PE = 0x04, JMODE = 15, 16 34
ADC CORE LATENCY
tADC Deterministic delay from the CLK± edge that samples the reference sample to the CLK± edge that samples SYSREF going high(1) JMODE = 0 –8.5 tCLK cycles
JMODE = 1 –20.5
JMODE = 2 –9
JMODE = 3 –21
JMODE = 4 –4.5
JMODE = 5 –24.5
JMODE = 6 –5
JMODE = 7 –25
JMODE = 9 60
JMODE = 10 140
JMODE = 11 136
JMODE = 12 120
JMODE = 13 232
JMODE = 14 232
JMODE = 15 446
JMODE = 16 430
JMODE = 17 –48.5
JMODE = 18 -49
JESD204B AND SERIALIZER LATENCY
tTX Delay from the CLK± rising edge that samples SYSREF high to the first bit of the multiframe on the JESD204B serial output lane corresponding to the reference sample of tADC(2) JMODE = 0 72 84 tCLK cycles
JMODE = 1 119 132
JMODE = 2 72 84
JMODE = 3 119 132
JMODE = 4 67 80
JMODE = 5 106 119
JMODE = 6 67 80
JMODE = 7 106 119
JMODE = 9 106 119
JMODE = 10 67 80
JMODE = 11 106 119
JMODE = 12 213 225
JMODE = 13 67 80
JMODE = 14 106 119
JMODE = 15 67 80
JMODE = 16 106 119
JMODE = 17 195 208
JMODE = 18 195 208
SERIAL PROGRAMMING INTERFACE (SDO)
t(OZD) Maximum delay from the falling edge of the 16th SCLK cycle during read operation for SDO transition from tri-state to valid data 7 ns
t(ODZ) Maximum delay from the SCS rising edge for SDO transition from valid data to tri-state 7 ns
t(OD) Maximum delay from the falling edge of the 16th SCLK cycle during read operation to SDO valid 12 ns
(1) tADC is an exact, unrounded, deterministic delay. The delay can be negative if the reference sample is sampled after the SYSREF high capture point, in which case the total latency is smaller than the delay given by tTX.
(2) The values given for tTX include deterministic and non-deterministic delays. Over process, temperature, and voltage, the delay will vary. JESD204B accounts for these variations when operating in subclass-1 mode in order to achieve deterministic latency. Proper receiver RBD values must be chosen such that the elastic buffer release point does not occur within the invalid region of the local multiframe clock (LMFC) cycle.
(3) tAJ increases because of additional attenuation on the internal clock path.
ADC12DJ2700 Timing_Diagram.gif
1. Only the SerDes lane DA0± is shown, but DA0± is representative of all lanes. The number of output lanes used and bit-packing format is dependent on the programmed JMODE value.
Figure 1. ADC Timing Diagram
ADC12DJ2700 SYNC_Timing.gif
1. The internal LMFC is assumed to be aligned with the CLK± rising edge that captures the SYSREF± high value.
2. Only SerDes lane DA0± is shown, but DA0± is representative of all lanes. All lanes output /R at approximately the same point in time. The number of lanes is dependent on the programmed JMODE value.
Figure 2. SYNCSE and TMSTP± Timing Diagram for NCO Synchronization
ADC12DJ2700 SPI_Timing.gifFigure 3. Serial Interface Timing

6.11 Typical Characteristics

typical values at TA = 25°C, VA19 = 1.9 V, VA11 = VD11 = 1.1 V, default full-scale voltage (FS_RANGE_A = FS_RANGE_B = 0xA000), input signal applied to INA± in single-channel modes, fIN = 347 MHz, AIN = –1 dBFS, fCLK = maximum-rated clock frequency, filtered, 1-VPP sine-wave clock, JMODE = 1, and background calibration (unless otherwise noted); SNR results exclude DC, HD2 to HD9 and interleaving spurs; SINAD, ENOB, and SFDR results exclude DC and fixed-frequency interleaving spurs
ADC12DJ2700 D010_SLVSEH9.gif
JMODE3, fS = 2700 MSPS, foreground (FG) and background (BG) calibration
Figure 4. ENOB vs Input Frequency
ADC12DJ2700 D131_SLVSEH9.gif
JMODE3, fS = 2700 MSPS, FG calibration
Figure 6. SNR, SINAD, SFDR vs Input Frequency
ADC12DJ2700 D132_SLVSEH9.gif
JMODE3, fS = 2700 MSPS, FG calibration
Figure 8. HD2, HD3, THD vs Input Frequency
ADC12DJ2700 D009_SLVSEH9.gif
JMODE3, fS = 2700 MSPS, BG calibration
Figure 10. SNR, SINAD, SFDR vs Input Frequency
ADC12DJ2700 D011_SLVSEH9.gif
JMODE3, fS = 2700 MSPS, BG calibration
Figure 12. HD2, HD3, THD vs Input Frequency
ADC12DJ2700 D013_SLVSEH9.gif
JMODE3, fIN = 347 MHz, BG calibration
Figure 14. ENOB vs Sampling Rate
ADC12DJ2700 D012_SLVSEH9.gif
JMODE3, fIN = 347 MHz, BG calibration
Figure 16. SNR, SINAD, SFDR vs Sampling Rate
ADC12DJ2700 D014_SLVSEH9.gif
JMODE3, fIN = 347 MHz, BG calibration
Figure 18. HD2, HD3, THD vs Sampling Rate
ADC12DJ2700 D139_SLVSEH9.gif
JMODE3, fIN = 350 MHz, FG calibration, SNR = 56.7 dBFS, SFDR = 68.0 dBFS, ENOB = 9.00 bits
Figure 20. Single-Tone FFT at AIN = –1 dBFS
ADC12DJ2700 D140_SLVSEH9.gif
JMODE3, fIN = 2400 MHz, FG calibration, SNR = 55.7 dBFS, SFDR = 71.7 dBFS, ENOB = 8.87 bits
Figure 22. Single-Tone FFT at AIN = –1 dBFS
ADC12DJ2700 D141_SLVSEH9.gif
JMODE3, fIN = 5000 MHz, FG calibration, SNR = 53.8 dBFS, SFDR = 59.3 dBFS, ENOB = 8.26 bits
Figure 24. Single-Tone FFT at AIN = –1 dBFS
ADC12DJ2700 D145_SLVSEH9.gif
JMODE3, fIN = 8200 MHz, FG calibration, SNR = 51.4 dBFS, SFDR = 54.0 dBFS, ENOB = 7.62 bits
Figure 26. Single-Tone FFT at AIN = –1 dBFS
ADC12DJ2700 D142_SLVSEH9.gif
JMODE3, fIN = 8200 MHz, FG calibration, SNR = 57.1 dBFS, SFDR = 74.5 dBFS, ENOB = 9.12 bits
Figure 28. Single-Tone FFT at AIN = –16 dBFS
ADC12DJ2700 D048_SLVSEH9.gif
JMODE1, fS = 5400 MSPS, FG calibration
Figure 30. DNL vs Code
ADC12DJ2700 D039_SLVSEH9.gif
JMODE1, fS = 5400 MSPS, fIN = 2400 MHz, BG calibration
Figure 32. SNR, SINAD, SFDR vs Temperature
ADC12DJ2700 D040_SLVSEH9.gif
JMODE1, fIN = 2400 MHz, fS = 5400 MSPS
Figure 34. ENOB vs Temperature and Calibration Type
ADC12DJ2700 D063_SLVSEH9.gif
JMODE1, fIN = 600 MHz, fS = 5400 MSPS
Figure 36. SNR vs Temperature and Calibration Type
ADC12DJ2700 D119_SLVSEH9.gif
JMODE1, fIN = 600 MHz, fS = 5400 MSPS
Figure 38. HD2 vs Temperature and Calibration Type
ADC12DJ2700 D036_SLVSEH9.gif
JMODE1, fS = 5400 MSPS, fIN = 600 MHz, FG calibration
Figure 40. SNR, SINAD, SFDR vs Supply Voltage
ADC12DJ2700 D038_SLVSEH9.gif
JMODE1, fS = 5400 MSPS, fIN = 600 MHz, FG calibration
Figure 42. HD2, HD3, THD vs Supply Voltage
ADC12DJ2700 D133_SLVSEH9.gif
fS = 2700 MSPS, FG calibration
Figure 44. ENOB vs Decimation Factor
ADC12DJ2700 D008_SLVSEH9.gif
JMODE1, fIN = 347 MHz, FG calibration
Figure 46. Power Consumption vs Sampling Rate
ADC12DJ2700 D016_SLVSEH9.gif
JMODE3, fIN = 347 MHz, FG calibration
Figure 48. Power Consumption vs Sampling Rate
ADC12DJ2700 D046_SLVSEH9.gif
JMODE1, fS = 5400 MSPS, fIN = 2400 MHz, BG calibration
Figure 50. Power Consumption vs Temperature
ADC12DJ2700 D044_SLVSEH9.gif
JMODE1, fS = 5400 MSPS, FG calibration
Figure 52. Power Consumption vs Supply Voltage
ADC12DJ2700 D124_SLVSEH9.gif
JMODE0, fIN = 607 MHz
Figure 54. IA11 Supply Current vs Clock Frequency
ADC12DJ2700 D118_SLVSEH9.gif
JMODE0, fIN = 607 MHz
Figure 56. Power Consumption vs Clock Frequency
ADC12DJ2700 D122_SLVSEH9.gif
fIN = 2400 MHz, fCLK = 2700 MHz, BG calibration
Figure 58. Supply Current vs JMODE
ADC12DJ2700 D125_SLVSD97.gif
JMODE0, fCLK = 3200 MHz, fIN = 3199.9 MHz
Figure 60. Background Calibration Core Transition
(AC Signal) (1)
1. These curves are taken at a clock frequency higher than the rated maximum clock frequency but are representative of results at the rated maximum clock frequency.
ADC12DJ2700 D127_SLVSD97.gif
JMODE0, fCLK = 3200 MHz, DC input
Figure 62. Background Calibration Core Transition
(DC Signal)(1)
ADC12DJ2700 D002_SLVSEH9.gif
JMODE1, fS = 5400 MSPS, FG and BG calibration
Figure 5. ENOB vs Input Frequency
ADC12DJ2700 D129_SLVSEH9.gif
JMODE1, fS = 5400 MSPS, FG calibration
Figure 7. SNR, SINAD, SFDR vs Input Frequency
ADC12DJ2700 D130_SLVSEH9.gif
JMODE1, fS = 5400 MSPS, FG calibration
Figure 9. HD2, HD3, THD vs Input Frequency
ADC12DJ2700 D001_SLVSEH9.gif
JMODE1, fS = 5400 MSPS, BG calibration
Figure 11. SNR, SINAD, SFDR vs Input Frequency
ADC12DJ2700 D003_SLVSEH9.gif
JMODE1, fS = 5400 MSPS, BG calibration
Figure 13. HD2, HD3, THD vs Input Frequency
ADC12DJ2700 D005_SLVSEH9.gif
JMODE1, fIN = 347 MHz, BG calibration
Figure 15. ENOB vs Sampling Rate
ADC12DJ2700 D004_SLVSEH9.gif
JMODE1, fIN = 347 MHz, BG calibration
Figure 17. SNR, SINAD, SFDR vs Sampling Rate
ADC12DJ2700 D006_SLVSEH9.gif
JMODE1, fIN = 347 MHz, BG calibration
Figure 19. HD2, HD3, THD vs Sampling Rate
ADC12DJ2700 D134_SLVSEH9.gif
JMODE1, fIN = 350 MHz, FG calibration, SNR = 56.6 dBFS, SFDR = 70.0 dBFS, ENOB = 8.98 bits
Figure 21. Single-Tone FFT at AIN = –1 dBFS
ADC12DJ2700 D135_SLVSEH9.gif
JMODE1, fIN = 2400 MHz, FG calibration, SNR = 55.8 dBFS, SFDR = 69.3 dBFS, ENOB = 8.90 bits
Figure 23. Single-Tone FFT at AIN = –1 dBFS
ADC12DJ2700 D136_SLVSEH9.gif
JMODE1, fIN = 5000 MHz, FG calibration, SNR = 54 dBFS, SFDR = 55.0 dBFS, ENOB = 8.09 bits
Figure 25. Single-Tone FFT at AIN = –1 dBFS
ADC12DJ2700 D144_SLVSEH9.gif
JMODE1, fIN = 8200 MHz, FG calibration, SNR = 51.5 dBFS, SFDR = 47.2 dBFS, ENOB = 7.16 bits
Figure 27. Single-Tone FFT at AIN = –1 dBFS
ADC12DJ2700 D137_SLVSEH9.gif
JMODE1, fIN = 8200 MHz, FG calibration, SNR = 57.0 dBFS, SFDR = 61.5 dBFS, ENOB = 8.89 bits
Figure 29. Single-Tone FFT at AIN = –16 dBFS
ADC12DJ2700 D049_SLVSEH9.gif
JMODE1, fS = 5400 MSPS, FG calibration
Figure 31. INL vs Code
ADC12DJ2700 D041_SLVSEH9.gif
JMODE1, fS = 5400 MSPS, fIN = 2400 MHz, BG calibration
Figure 33. HD2, HD3, THD vs Temperature
ADC12DJ2700 D121_SLVSEH9.gif
JMODE1, fIN = 600 MHz, fS = 5400 MSPS
Figure 35. ENOB vs Temperature and Calibration Type
ADC12DJ2700 D064_SLVSEH9.gif
JMODE1, fIN = 600 MHz, fS = 5400 MSPS
Figure 37. SFDR vs Temperature and Calibration Type
ADC12DJ2700 D120_SLVSEH9.gif
JMODE1, fIN = 600 MHz, fS = 5400 MSPS
Figure 39. HD3 vs Temperature and Calibration Type
ADC12DJ2700 D037_SLVSEH9.gif
JMODE1, fS = 5400 MSPS, fIN = 600 MHz, FG calibration
Figure 41. ENOB vs Supply Voltage
ADC12DJ2700 D035_SLVSEH9.gif
fS = 2700 MSPS, fIN = 2400 MHz, FG calibration
Figure 43. SNR, SINAD, SFDR vs Decimation Factor
ADC12DJ2700 D007_SLVSEH9.gif
JMODE1, fIN = 347 MHz, FG calibration
Figure 45. Supply Current vs Sampling Rate
ADC12DJ2700 D015_SLVSEH9.gif
JMODE3, fIN = 347 MHz, FG calibration
Figure 47. Supply Current vs Sampling Rate
ADC12DJ2700 D047_SLVSEH9.gif
JMODE1, fS = 5400 MSPS, fIN = 2400 MHz, BG calibration
Figure 49. Supply Current vs Temperature
ADC12DJ2700 D045_SLVSEH9.gif
JMODE1, fS = 5400 MSPS, FG calibration
Figure 51. Supply Current vs Supply Voltage
ADC12DJ2700 D123_SLVSEH9.gif
JMODE0, fIN = 607 MHz
Figure 53. IA19 Supply Current vs Clock Frequency
ADC12DJ2700 D117_SLVSEH9.gif
JMODE0, fIN = 607 MHz
Figure 55. ID11 Supply Current vs Clock Frequency
ADC12DJ2700 D034_SLVSEH9.gif
fIN = 2400 MHz, fCLK = 2700 MHz, FG calibration
Figure 57. Supply Current vs JMODE
ADC12DJ2700 D033_SLVSEH9.gif
fIN = 2400 MHz, fCLK = 2700 MHz
Figure 59. Power Consumption vs JMODE
ADC12DJ2700 D126_SLVSD97.gif
JMODE0, fCLK = 3200 MHz, fIN = 3199.9 MHz
Figure 61. Background Calibration Core Transition
(AC Signal Zoomed)(1)
ADC12DJ2700 D128_SLVSD97.gif
JMODE0, fCLK = 3200 MHz, DC input
Figure 63. Background Calibration Core Transition
(DC Signal Zoomed)(1)

7 Detailed Description

7.1 Overview

ADC12DJ2700 device is an RF-sampling, giga-sample, analog-to-digital converter (ADC) that can directly sample input frequencies from DC to above 10 GHz. In dual-channel mode, the ADC12DJ2700 can sample up to 2700 GSPS and up to 5400 GSPS in single-channel mode. Programmable tradeoffs in channel count (dual-channel mode) and Nyquist bandwidth (single-channel mode) allow development of flexible hardware that meets the needs of both high channel count or wide instantaneous signal bandwidth applications. Full-power input bandwidth (–3 dB) of 8.0 GHz, with usable frequencies exceeding the –3-dB point in both dual- and single-channel modes, allows direct RF sampling of L-band, S-band, C-band, and X-band for frequency agile systems.

ADC12DJ2700 uses a high-speed JESD204B output interface with up to 16 serialized lanes and subclass-1 compliance for deterministic latency and multi-device synchronization. The serial output lanes support up to 12.8 Gbps and can be configured to trade-off bit rate and number of lanes.

A number of synchronization features, including noiseless aperture delay (tAD) adjustment and SYSREF windowing, simplify system design for multi-channel systems. Aperture delay adjustment can be used to simplify SYSREF capture, to align the sampling instance between multiple ADCs or to sample an ideal location of a front-end track and hold (T&H) amplifier output. SYSREF windowing offers a simplistic way to measure invalid timing regions of SYSREF relative to the device clock and then choose an optimal sampling location. Dual-edge sampling (DES) is implemented in single-channel mode to reduce the maximum clock rate applied to the ADC to support a wide range of clock sources and relax setup and hold timing for SYSREF capture.

Optional digital down converters (DDCs) are available in dual-channel mode to allow a reduction in interface rate (decimation) and digital mixing of the signal to baseband. The DDC block supports data decimation of 4x, 8x or 16x and alias-free complex output bandwidths of 80% of the effective output data rate.

ADC12DJ2700 provides foreground and background calibration options for gain, offset and static linearity errors. Foreground calibration is run at system startup or at specified times during which the ADC is offline and not sending data to the logic device. Background calibration allows the ADC to run continually while the cores are calibrated in the background so that the system does not experience downtime. The calibration routine is also used to match the gain and offset between sub-ADC cores to minimize spurious artifacts from time interleaving.

 
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