TCAN1043xx-Q1 具有 CAN FD 和唤醒功能的汽车级低功耗故障保护 CAN 收发器
- ZHCSH19G November 2017 – December 2024 TCAN1043-Q1 , TCAN1043G-Q1 , TCAN1043H-Q1 , TCAN1043HG-Q1
  
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TCAN1043xx-Q1 具有 CAN FD 和唤醒功能的汽车级低功耗故障保护 CAN 收发器

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1 特性

AEC Q100：符合汽车应用要求
- 温度等级 1：T_A = -55°C 至 125°C
- 器件 HBM 分级等级：±16kV
- 器件 CDM 分级等级：±1500V
功能安全型
- 可提供用于功能安全系统设计的文档
符合 ISO 11898-2 (2016) 的要求
所有器件均支持经典 CAN 和 2Mbps CAN FD（灵活数据速率），而“G”选项支持 5Mbps
- 具有较短的对称传播延迟时间和快速循环次数，可增加时序裕量
- 在有负载 CAN 网络中实现更快的数据速率
V_IO 电平转换支持 2.8V 至 5.5V 的电压范围
工作模式
- 正常模式
- 具有 INH 输出以及本地和远程唤醒请求功能的待机模式
- 具有 INH 输出以及本地和远程唤醒请求的低功耗睡眠模式
未供电时具有无源行为
- 总线和逻辑终端处于高阻态（运行总线或应用上无负载）
- 支持热插拔：在总线和 RXD 输出上可实现上电和断电无干扰运行
符合或超出 EMC 标准要求
- 符合 IEC 62228-3 – 2007 标准
- 符合 SAE J2962-2 标准
保护特性
- 总线终端的 IEC ESD 保护：±8kV
- 总线故障保护：±58V（非 H 型号）和 ±70V（H 型号）
- 电源终端欠压保护
- 驱动器显性超时 (TXD DTO)：数据速率低至 9.2kbps
- 热关断保护 (TSD)
接收器共模输入电压：±30V
典型循环延迟：110ns
结温范围为 –55°C 至 150°C
采用 SOIC (14) 封装和无引线 VSON (14) 封装 (4.5mm x 3mm)，具有改进的自动光学检查 (AOI) 功能

2 应用

12V 或 24V 系统应用
汽车和运输

3 说明

TCAN1043xx-Q1 满足 ISO 11898–2 (2016) 高速控制器局域网 (CAN) 规范的物理层要求，提供 CAN 总线和 CAN 协议控制器之间的接口。这些器件支持传统 CAN 和 CAN FD 协议，具有最高 2Mbps 的数据速率。器件型号以“G”结尾的器件专为数据速率高达 5Mbps 的 CAN FD 应用而设计。TCAN1043xx-Q1 可以（通过 INH 输出引脚）选择性地启用节点上可能存在的各种电源，从而在整个系统级别减少电池电流消耗。这使得在超低电流睡眠状态中，功率传送到除 TCAN1043xx-Q1 以外的所有系统组件，而 TCAN1043xx-Q1 则仍然处于低功耗状态，并对 CAN 总线进行监控。

在总线上检测到唤醒模式或通过 WAKE 输入请求本地唤醒时，TCAN1043xx-Q1 会通过驱动 INH 高电平的方式发起节点启动。TCAN1043xx-Q1 包括通过 V_IO 端子实现的内部逻辑电平转换功能，允许直接连接到 3.3V 或 5V 控制器。该器件包含很多保护和诊断功能，包括 CAN 总线短路检测和电池连接检测。TCAN1043xx-Q1 满足 IEC 62228-3 和 J2962-2 的 ESD 和 EMC 要求，无需额外增加保护组件。

封装信息

器件型号	封装⁽¹⁾	封装尺寸⁽²⁾
TCAN1043xx-Q1	SOIC (14)	8.65mm × 6mm
TCAN1043xx-Q1	VSON (14)	4.5mm × 3mm

(1) 有关更多信息，请参阅节 12。

(2) 封装尺寸（长 × 宽）为标称值，并包括引脚（如适用）。

功能方框图

4 Device Comparison Table

DEVICE NUMBER	BUS FAULT PROTECTION	MAXIMUM DATA RATE
TCAN1043-Q1	±58V	2Mbps
TCAN1043H-Q1	±70V	2Mbps
TCAN1043G-Q1	±58V	5Mbps
TCAN1043HG-Q1	±70V	5Mbps

5 Pin Configuration and Functions

Figure 5-1 D Package, 14 Pin (SOIC)
(Top View)

Figure 5-2 DMT Package, 14 Pin (VSON)
(Top View)

Table 5-1 Pin Functions

PINS		TYPE	DESCRIPTION
NAME	NO	TYPE	DESCRIPTION
TXD	1	Digital Input	CAN transmit data input (low for dominant and high for recessive bus states)
GND	2	GND	Ground connection
V_CC	3	Supply	5V CAN bus supply voltage
RXD	4	Digital Output	CAN receive data output (low for dominant and high for recessive bus states), tri-state
V_IO	5	Supply	I/O supply voltage
EN	6	Digital Input	Enable input for mode control, integrated pull down
INH	7	High Voltage Output	Can be used to control system voltage regulators
nFAULT	8	Digital Output	Fault output, inverted logic
WAKE	9	High Voltage Input	Wake input terminal, high voltage input
V_SUP	10	Supply	Reverse-blocked battery supply input
NC	11	—	No connect (not internally connected)
CANL	12	Bus I/O	Low-level CAN bus input/output line
CANH	13	Bus I/O	High-level CAN bus input/output line
nSTB	14	Digital Input	Standby input for mode control, integrated pull down

6 Specifications

6.1 Absolute Maximum Ratings

See ⁽¹⁾⁽²⁾

			MIN	MAX	UNIT
V_SUP	Battery supply (reverse-blocked) voltage range – standard versions		–0.3	58	V
V_SUP	Battery supply (reverse blocked) voltage range – H versions		–0.3	70	V
V_CC	5-V bus supply voltage		–0.3	7	V
V_IO	I/O level shifting voltage		–0.3	7	V
V_BUS	CAN bus I/O voltage range (CANH, CANL)	Devices without the "H" suffix	–58	58	V
V_BUS	CAN bus I/O voltage range (CANH, CANL)	Devices with the "H" suffix	–70	70	V
V_(DIFF)	Max differential voltage between CANH and CANL	Devices without the "H" suffix	–58	58	V
V_(DIFF)	Max differential voltage between CANH and CANL	Devices with the "H" suffix	–70	70	V
V_{(Logic_Input)}	Logic input terminal voltage range		–0.3	7	V
V_{(Logic_Output)}	Logic output terminal voltage range		–0.3	7	V
V_INH	INH output pin voltage range	Devices without the "H" suffix	–0.3	58 and V_O ≤ V_SUP + 0.3	V
V_INH	INH output pin voltage range	H versions	–0.3	70 and V_O ≤ V_SUP + 0.3	V
V_(WAKE)	WAKE input pin voltage range	Devices without the "H" suffix	–0.3	58 and V_I ≤ V_SUP + 0.3	V
V_(WAKE)	WAKE input pin voltage range	H versions	–0.3	70 and V_I ≤ V_SUP + 0.3	V
I_O(LOGIC)	Logic output current	RXD, and nFAULT		8	mA
I_O(INH)	INH output current			4	mA
I_O(WAKE)	Wake current if due to ground shifts V_(WAKE) ≤ V_(GND) – 0.3 V, thus the current into WAKE must be limited via an external serial resistor			3	mA
T_J	Operating virtual junction temperature range		–55	150	°C

(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.

(2) All voltage values, except differential I/O bus voltages, are with respect to ground terminal.

6.2 ESD Ratings

				VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per AEC Q100-002	V_SUP, INH⁽¹⁾	±4000	V
			All pins, except V_SUP, INH⁽¹⁾	±6000	V
			CAN bus terminals (CANH, CANL)⁽²⁾	±16000	V
		Charged device model (CDM) - SOIC	All terminals⁽³⁾	±1500	V
		Charged device model (CDM) - DMT	All terminals⁽³⁾	±500	V
		Charged device model (CDM) - DMT	Corner terminals⁽³⁾	±750	V
		Machine model (MM)	All terminals⁽⁴⁾	±200	V

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

(2) Test method based upon AEC-Q100-002, CAN bus terminals stressed with respect to each other and to GND.

(3) Tested in accordance to AEC-Q100-011.

(4) Tested in accordance to JEDEC Standard 22, Test Method A115A.

6.3 ESD Ratings IEC Specification

				VALUE	UNIT
V_(ESD)	System level electrostatic discharge (ESD)	CAN bus terminals (CANH, CANL) to GND	ISO 10605 per SAE J2962-2: Powered Air Discharge⁽²⁾	±15000	V
			ISO 10605 per SAE J2962-2: Powered Contact Discharge⁽²⁾	±8000	V
			IEC 61000-4-2 (150 pF, 330 Ω): Unpowered contact discharge	±15000	V
		V_SUP and WAKE	IEC 61000-4-2 (150 pF, 330 Ω) Unpowered contact discharge	±6000	V
	ISO 7637-2 Transients according to GIFT - ICT CAN EMC test specification⁽¹⁾	CAN bus terminals (CANH, CANL) to GND, V_SUP, WAKE	Pulse 1	–100	V
			Pulse 2	+75	V
			Pulse 3a	–150	V
			Pulse 3b	+100	V
	ISO 7637-3 Transients	CAN bus terminals (CANH, CANL) to GND, V_SUP, WAKE	Direct coupling capacitor "slow transient pulse" with 100-nF coupling capacitor - powered	±85	V

(1) ISO 7637 is a system level transient test. Results given here are specific to the IBEE CAN EMC Test specification conditions. Different system level configurations leads to different results.

(2) Verified by external test facility on SOIC package

6.4 Recommended Operating Conditions

		MIN	MAX	UNIT
V_SUP	Battery supply (reverse-blocked) voltage range - standard version	4.5	45	V
V_SUP	Battery supply (reverse-blocked) voltage range - H version	4.5	60	V
V_CC	5 V Supply Voltage	4.5	5.5	V
V_IO	I/O supply voltage	2.8	5.5	V
I_OH(LOGIC)	Logic terminal high level output current – RXD and nFAULT	–2		mA
I_OL(LOGIC)	Logic terminal low level output current – RXD and nFAULT		2	mA
I_O(INH)	INH output current		1	mA
T_A	Operational free-air temperature	–55	125	°C

6.5 Thermal Information

THERMAL METRIC⁽¹⁾		TCAN1043x-Q1		UNIT
		D (SOIC)	DMT (VSON)
		14 PINS	14 PINS
R_θJA	Junction-to-ambient thermal resistance	78	33.1	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	33.6	30.5	°C/W
R_θJB	Junction-to-board thermal resistance	34.7	10.8	°C/W
Ψ_JT	Junction-to-top characterization parameter	5.7	0.4	°C/W
Ψ_JB	Junction-to-board characterization parameter	34.3	10.7	°C/W
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	n/a	1.3	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.6 Dissipation Ratings

PARAMETER		TEST CONDITIONS	POWER DISSIPATION	UNIT
P_D	Average power dissipation	V_SUP = 14 V, V_CC = 5 V, V_IO = 5 V, T_J = 27°C, R_L = 60 Ω, nSTB = 5 V, EN = 5 V, C_{L_RXD} = 15 pF. Typical CAN operating conditions at 500 kbps with 25% transmission (dominant) rate.	58	mW
P_D	Average power dissipation	V_SUP = 14 V, V_CC = 5.5 V, V_IO = 5.5 V, T_J = 150°C, R_L = 50 Ω, nSTB = 5.5 V, EN = 5.5 V, C_{L_RXD} = 15 pF. Typical high load CAN operating conditions at 1Mbps with 50% transmission (dominant) rate and loaded network.	126	mW
T_TSD	Thermal shutdown temperature		170	°C
T_{TSD_HYS}	Thermal shutdown hysteresis		10	°C

6.7 Electrical Characteristics

Over recommended operating conditions with T_A = –55°C to 125°C (unless otherwise noted).

PARAMETER			TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	UNIT
SUPPLY CHARACTERISTICS
I_SUP	Supply current V_SUP	Normal, Silent, Go-to-Sleep			40	70	µA
		Standby mode	Standby mode, V_CC > 4.5 V, V_IO > 2.8 V, V_INH = V_(WAKE) = V_SUP		15	45	µA
		Sleep mode	Sleep mode, V_CC = V_IO = V_INH = 0 V V_(WAKE) = V_SUP		15	30	µA
I_CC	Supply current Normal mode V_CC	Dominant	See Figure 7-2. TXD = 0 V, R_L = 60 Ω, C_L = open. Typical bus load.			70	mA
		Dominant	See Figure 7-2. TXD = 0 V, R_L = 50 Ω, C_L = open. High bus load.			80	mA
		Dominant with bus fault	See Figure 7-2. TXD = 0 V, CANH = -25 V, R_L = open, C_L = open			110	mA
		Recessive	See Figure 7-2. TXD = V_IO, R_L = 50 Ω, C_L = open, R_CM = open			5	mA
	Supply current Silent and Go-to-Sleep mode		See Figure 7-2. TXD = V_IO, R_L = 50 Ω, C_L = open			2.5	mA
	Supply current Standby mode		See Figure 7-2. EN = L, NSTB = L			5	µA
	Sleep mode		See Figure 7-2. EN = H or L, NSTB = L			5	µA
I_IO	I/O supply current	Normal mode	RXD floating, TXD = 0 V (dominant) nSTB = V_IO, EN = V_IO			450	µA
		Normal, Silent or Go-to-Sleep mode	RXD floating, TXD = V_IO recessive			5	µA
		Normal, Silent or Go-to-Sleep mode	RXD floating, TXD = V_IO recessive			5	µA
		Sleep mode	NSTB = L			5	µA
UV_SUP	Undervoltage detection on V_SUP for protected mode			3.0		4.2	V
V_HYS(UVSUP)	Hysteresis voltage on UV_SUP				50		mV
UV_VCC	Rising undervoltage detection on V_CC for protected mode				4.1	4.4	V
UV_VCC	Falling undervoltage detection on V_CC for protected mode			3.5	3.9		V
V_HYS(UVVCC)	Hysteresis voltage on UV_VCC				200		mV
UV_VIO	Undervoltage detection on V_IO for protected mode			1.3		2.75	V
V_HYS(UVIO)	Hysteresis voltage on UV_IO				80		mV
Driver Electrical Characteristics
V_O(D)	Bus output voltage dominant - normal mode	CANH	See Figure 7-2 and Figure 8-3, TXD = 0 V, Normal mode, 50 ≤ R_L ≤ 65 Ω, C_L = open, R_CM = open	2.75		4.5	V
V_O(D)	Bus output voltage dominant - normal mode	CANL		0.5		2.25	V
V_O(R)	Bus output voltage recessive	CANH and CANL	See Figure 7-2 and Figure 8-3, TXD = V_CC, V_IO = V_CC, Normal or Silent⁽²⁾, R_L = open, R_CM = open	2	0.5 × V_CC	3	V
V_OD(D)	Differential output voltage dominant	CANH - CANL	See Figure 7-2 and Figure 8-3, TXD = 0 V, Normal mode, 50 Ω ≤ R_L ≤ 65 Ω, C_L = open, R_CM = open	1.5		3	V
			See Figure 7-2 and Figure 8-3, TXD = 0 V, Normal mode, 45 Ω ≤ R_L ≤ 50 Ω, CL = open, R_CM = open	1.4		3	V
			See Figure 7-2 and Figure 8-3, TXD = 0 V, Normal mode, R_L = 2240 Ω, C_L = open, R_CM = open	1.5		5	V
			See Figure 7-2 and Figure 8-3, TXD = 0 V, Normal mode, 45 Ω ≤ R_L ≤ 70 Ω, C_L = open, R_CM = open	1.4		3.3	V
V_OD(R)	Differential output voltage recessive	CANH - CANL	See Figure 7-2 and Figure 8-3, TXD = V_CC, Normal or Silent mode⁽²⁾, R_L = 60 Ω, C_L = open, R_CM = open	–120		12	mV
V_OD(R)	Differential output voltage recessive	CANH - CANL	See Figure 7-2 and Figure 8-3, TXD = V_CC, Normal or Silent mode⁽²⁾, R_L = open, C_L = open, R_CM = open	–50		50	mV
V_SYM	Driver symmetry, dominant or recessive V_SYM = (V_O(CANH) + V_O(CANL))/V_CC		See Figure 7-2 and Figure 9-4, Normal mode, C_L = open, R_CM = open, TXD = 1MHz⁽³⁾	0.9		1.1	V / V
V_{SYM_DC}	Driver symmetry, dominant V_SYM(DC) = V_CC - V_O(CANH) - V_O(CANL)		See Figure 7-2 and Figure 8-3, Normal or Silent mode, R_L = 60 Ω, C_L = open, R_CM = open	–400		400	mV
I_OS(DOM)	Short circuit steady-state output current dominant		See Figure 7-10 and Figure 8-3, V_CANH = -5 V, CANL = open, TXD = 0 V	–100			mA
I_OS(DOM)	Short circuit steady-state output current dominant		See Figure 7-10 and Figure 8-3, V_CANL = 40 V, CANH = open, TXD = 0 V			100	mA
I_OS(REC)	Short circuit steady-state output current recessive		See Figure 7-10 and Figure 8-3 –27 V ≤ V_BUS ≤ 32 V, V_BUS = CANH = CANL, TXD = V_IO	–5		5	mA
V_O(STB)	Bus output voltage Standby mode	CANH	STB = V_CC or V_IO, R_L = open, R_CM = open	–0.1	0	0.1	V
		CANL		–0.1	0	0.1	V
		CANH - CANL		–0.2	0	0.2	V
Receiver Electrical Characteristics
V_CM	Common mode range Normal and Silent modes		See Figure 7-3 and Table 8-5	-30		30	V
V_IT	Input threshold voltage Normal and Silent modes		See Figure 7-3 and Table 8-5, V_CM ≤ ±20 V	500		900	mV
V_IT	Input threshold voltage Normal and Silent modes		See Figure 7-3 and Table 8-5, V_CM ≤ ±30 V	400		1000	mV
V_REC	Receiver recessive voltage		See Figure 7-3 and Table 8-5 Normal or Silent mode, V_CM = ±20 V	-3		0.5	V
V_DOM	Receiver dominant voltage			0.9		8	V
V_HYS	Hysteresis voltage for input threshold Normal and Silent modes		See Figure 7-3 and Table 8-5		120		mV
V_IT(Sleep)	Input threshold Sleep mode		See Figure 7-3 and Table 8-5; V_CM = ± 12 V	400		1150	mV
V_REC(Sleep)	Receiver recessive voltage Sleep mode			-3		0.4	V
V_DOM(Sleep)	Receiver dominant voltage Sleep mode			1.15		8	V
V_CM	Common mode range Standby, Go-to-Sleep and Sleep modes		See Figure 7-3 and Table 8-5	-12		12	V
I_IOFF(LKG)	Power-off (unpowered) bus input leakage current		CANH = CANL = 5 V, V_CC = GND, V_IO = GND, V_SUP = 0 V			4.8	µA
C_I	Input capacitance to ground (CANH or CANL)		TXD = V_CC, V_IO = V_CC⁽⁴⁾		24	30	pF
C_ID	Differential input capacitance (CANH or CANL)		TXD = V_CC, V_IO = V_CC⁽⁴⁾		12	15	pF
R_ID	Differential input resistance		TXD = V_CC = V_IO = 5 V, Normal mode; -30 ≤ V_CM ≤ +30V	30		80	kΩ
R_IN	Input resistance (CANH or CANL)		TXD = V_CC = V_IO = 5 V, Normal mode; -30 ≤ V_CM ≤ +30V	15		40	kΩ
R_IN(M)	Input resistance matching: [1 – R_IN(CANH) / R_IN(CANL)] × 100%		V_(CANH) = V_(CANL) = 5 V	–2%		2%
R_CBF	Valid differential load impedance range for bus fault circuitry		R_CM = R_L, C_L = open	45		70	Ω
TXD TERMINAL (CAN TRANSMIT DATA INPUT)
V_IH	High level input voltage			0.7 V_IO			V
V_IL	Low level input voltage					0.3 V_IO	V
I_IH	High level input leakage current		TXD = V_CC = V_IO = 5.5 V	–2.5	0	1	µA
I_IL	Low level input leakage current		TXD = 0 V, V_CC = V_IO = 5.5 V	–100		–2.5	µA
I_LKG(OFF)	Unpowered leakage current		TXD = 5.5 V, V_CC = V_IO = 0 V	–1	0	1	µA
C_I	Input capacitance		V_IN = 0.4 x sin(2 x π x 2 x 10⁶ x t) + 2.5 V		5		pF
RXD TERMINAL (CAN RECEIVE DATA OUTPUT)
V_OH	High level output voltage		See Figure 7-3, I_O = –2 mA.	0.8 V_IO			V
V_OL	Low level output voltage		See Figure 7-3, I_O = –2 mA.			0.2 V_IO	V
nFAULT TERMINAL (FAULT AND STATUS OUTPUT)
V_OH	High level output voltage		See Figure 7-1, I_O = –2 mA.	0.8 V_IO			V
V_OL	Low level output voltage		See Figure 7-1 I_O = 2 mA.			0.2 V_IO	V
nSTB TERMINAL (STANDBY MODE INPUT)
V_IH	High level input voltage			0.7 V_IO			V
V_IL	Low level input voltage					0.3 V_IO	V
I_IH	High level input leakage current		nSTB = V_CC = V_IO = 5.5 V	0.5		10	µA
I_IL	Low level input leakage current		nSTB = 0 V, V_CC = V_IO = 5.5 V	–1		1	µA
I_LKG(OFF)	Unpowered leakage current		nSTB = 5.5 V, V_CC = 0 V, V_IO = 0 V	–1	0	1	µA
EN TERMINAL (ENABLE MODE INPUT)
V_IH	High level input voltage			0.7 V_IO			V
V_IL	Low level input voltage					0.3 V_IO	V
I_IH	High level input leakage current		EN = V_CC = V_IO = 5.5 V	0.5		10	µA
I_IL	Low level input leakage current		EN = 0 V, V_CC = V_IO = 5.5 V	–1		1	µA
I_LKG(OFF)	Unpowered leakage current		EN = 5.5 V, V_CC = 0 V, V_IO = 0 V	–1	0	1	µA
INH TERMINAL (INHIBIT OUTPUT)
ΔV_H	High level voltage drop INH with respect to V_SUP		I_INH = –0.5 mA		0.5	1	V
I_LKG(INH)	Leakage current		INH = 0 V, Sleep Mode	-5		5	µA
Wake TERMINAL (WAKE INPUT)
V_IH	High level input voltage		Standby and Sleep Mode	V_SUP - 1.9			V
V_IL	Low level input voltage		Standby and Sleep Mode			V_SUP - 3.5	V
I_IH	High level input current⁽⁵⁾		WAKE = V_SUP – 1 V	–25	–15		µA
I_IL	Low level input current⁽⁵⁾		WAKE = 1 V		15	25	µA

(1) All typical values are at 25°C and supply voltages of V_CC = 5 V, V_IO = 3.3 V, and R_L = 60 Ω. Unless otherwise noted.

(2) The recessive bus voltage is the same if the device is in Normal mode with the nSTB and EN terminals high or if the device is in Silent mode with the nSTB terminal high and EN terminal low.

(3) The bus output voltage symmetry, V_SYM, is measured using R_TERM / 2 = 30 Ω and C_SPLIT = 4.7 nF as shown in Figure 9-4

(4) Specified by design and verified during product validation using the ISO 11898-2 method.

(5) To minimize system level current consumption, the WAKE automatically configures itself based on the applied voltage to have
either an internal pull-up or pull-down current source. A high level input results in an internal pull-up and a low level input results in an
internal pull-down. For more information, refer to Section 8.4.6.2.

6.8 Switching Characteristics

Over recommended operating conditions with T_A = -55°C to 125°C (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP⁽¹⁾	MAX	UNIT
DRIVER SWITCHING CHARACTERISTICS
t_pHR	Propagation delay time, high TXD to driver recessive	See Figure 7-2, Normal mode. R_L = 60 Ω, C_L = 100 pF, R_CM = open		50		ns
t_pLD	Propagation delay time, low TXD to driver dominant			40		ns
t_sk(p)	Pulse skew (\|t_pHR - t_pLD\|)			10		ns
t_R	Differential output signal rise time			45		ns
t_F	Differential output signal fall time			45		ns
t_{TXD_DTO}	Dominant time out	See Figure 7-9, R_L = 60 Ω, C_L = open	1.2		3.8	ms
RECEIVER SWITCHING CHARACTERISTICS
t_pRH	Propagation delay time, bus recessive input to high RXD	See Figure 7-3 C_L(RXD) = 15 pF		50		ns
t_pDL	Propagation delay time, bus dominant input to RXD low output			50		ns
t_R	Output signal rise time (RXD)			8		ns
t_F	Output signal fall time (RXD)			8		ns
t_{BUS_DOM}	Dominant time out	See Figure 17, R_L = 60 Ω, C_L = open	1.3		3.8	ms
t_CBF	Bus fault detection time	45 Ω ≤ R_CM ≤ 70 Ω, C_L = open	1.9			µs
Wake Terminal (Wake input)
t_{WAKE_HT}	WAKE hold time	See Figure 7-12 and Figure 7-13 Time required for LWU from a high to low or low to high on WAKE	5		50	µs
Device Switching Characteristics
t_PROP(LOOP1)	Total loop delay, driver input (TXD) to receiver output (RXD), recessive to dominant	See Figure 7-5, Normal mode, R_L = 60 Ω, C_L = 100 pF, C_L(RXD) = 15 pF		100	160	ns
t_PROP(LOOP2)	Total loop delay, driver input (TXD) to receiver output (RXD), dominant to recessive			110	175	ns
t_MODE1	Mode change time	See Figure 7-4 and Figure 7-5, Mode change time for leaving Sleep mode to entering normal and silent mode after V_CC and V_IO have crossed UV thresholds			20	µs
t_MODE2	Mode change time	Mode changes between Normal, Silent and Standby modes, and Sleep to Standby mode transition			10	µs
t_{UV_RE-ENABLE}	Re-enable time after under voltage event	Time for device to return to normal operation from UV_VCC or UV_VIO under voltage event			200	µs
t_{Power_Up}	Power up time on V_SUP	See Figure 7-11		250		µs
t_{WK_FILTER}	Bus time to meet filtered bus requirements for wake up request	See Figure 8-5	0.5		1.8	µs
t_{WK_TIMEOUT}	Bus Wake-up timeout value	See Figure 8-5	0.5		2	ms
t_UV	Undervoltage filter time for V_IO and V_CC	V_IO ≤ UV_VIO or V_CC < UV_VCC	159		340	ms
t_{Go_To_Sleep}	Minimum hold time for transition to sleep mode	EN = H and nSTB = L	5		50	µs
FD Timing Parameters
t_BIT(BUS)	Bit time on CAN bus output pins with t_BIT(TXD) = 500 ns, all devices	Normal mode, R_L = 60 Ω, C_L = 100 pF, C_L(RXD) = 15 pF, Δt_REC = t_BIT(RXD) - t_BIT(BUS)	435		530	ns
t_BIT(BUS)	Bit time on CAN bus output pins with t_BIT(TXD) = 200 ns, G device variants only		155		210	ns
t_BIT(RXD)	Bit time on RXD output pins with t_BIT(TXD) = 500 ns, all devices		400		550	ns
t_BIT(RXD)	Bit time on RXD output pins with t_BIT(TXD) = 200 ns, G device variants only		120		220	ns
Δt_REC	Receiver timing symmetry with t_BIT(TXD) = 500 ns, all devices		-65		40	ns
Δt_REC	Receiver timing symmetry with t_BIT(TXD) = 200 ns, G device variants only		-45		15	ns

6.9 Typical Characteristics

TCAN1043-Q1 TCAN1043H-Q1 TCAN1043HG-Q1 TCAN1043G-Q1 VOD(D) Over Temperature

V_CC = 5V	V_IO = 3.3V	R_L = 60Ω
C_L = Open	RCM = Open	STB = 0V

Figure 6-1 V_OD(D) Over Temperature

TCAN1043-Q1 TCAN1043H-Q1 TCAN1043HG-Q1 TCAN1043G-Q1 ICC Recessive Over Temperature

V_CC = 5V	V_IO = 3.3V	R_L = 60Ω
C_L = Open	RCM = Open	STB = 0V

Figure 6-3 I_CC Recessive Over Temperature

TCAN1043-Q1 TCAN1043H-Q1 TCAN1043HG-Q1 TCAN1043G-Q1 VOD(D) Over VCC

V_IO = 5V	STB = 0V	R_L = 60Ω
C_L = Open	RCM = Open	Temp = 25°C

Figure 6-2 V_OD(D) Over V_CC

TCAN1043-Q1 TCAN1043H-Q1 TCAN1043HG-Q1 TCAN1043G-Q1 Total Loop Delay Over Temperature

V_CC = 5V	V_IO = 3.3V	R_L = 60Ω
C_L = 100pF	C_{L_RXD} = 15pF	STB = 0V

Figure 6-4 Total Loop Delay Over Temperature

7 Parameter Measurement Information

TCAN1043-Q1 TCAN1043H-Q1 TCAN1043HG-Q1 TCAN1043G-Q1 Supply
Test Circuit

Figure 7-1 Supply Test Circuit

TCAN1043-Q1 TCAN1043H-Q1 TCAN1043HG-Q1 TCAN1043G-Q1 Driver
Test Circuit and Measurement

Figure 7-2 Driver Test Circuit and Measurement

TCAN1043-Q1 TCAN1043H-Q1 TCAN1043HG-Q1 TCAN1043G-Q1 Receiver
Test Circuit and Measurement

Figure 7-3 Receiver Test Circuit and Measurement

TCAN1043-Q1 TCAN1043H-Q1 TCAN1043HG-Q1 TCAN1043G-Q1 tMODE1 Test Circuit and Measurement, Silent Mode to Normal
Mode

Figure 7-4 t_MODE1 Test Circuit and Measurement, Silent Mode to Normal Mode

TCAN1043-Q1 TCAN1043H-Q1 TCAN1043HG-Q1 TCAN1043G-Q1 tMODE2 Test Circuit and Measurement, Normal Mode to Silent
Mode

Figure 7-5 t_MODE2 Test Circuit and Measurement, Normal Mode to Silent Mode

TCAN1043-Q1 TCAN1043H-Q1 TCAN1043HG-Q1 TCAN1043G-Q1 tPROP(LOOP) Test Circuit and Measurement

Figure 7-6 t_PROP(LOOP) Test Circuit and Measurement

TCAN1043-Q1 TCAN1043H-Q1 TCAN1043HG-Q1 TCAN1043G-Q1 tPROP(LOOP) Test Circuit and Measurement with CM Range

Figure 7-7 t_PROP(LOOP) Test Circuit and Measurement with CM Range

TCAN1043-Q1 TCAN1043H-Q1 TCAN1043HG-Q1 TCAN1043G-Q1 Loop
Delay Symmetry Test Circuit and Measurement

Figure 7-8 Loop Delay Symmetry Test Circuit and Measurement

TCAN1043-Q1 TCAN1043H-Q1 TCAN1043HG-Q1 TCAN1043G-Q1 TXD
Dominant Timeout Test Circuit and Measurement

Figure 7-9 TXD Dominant Timeout Test Circuit and Measurement

TCAN1043-Q1 TCAN1043H-Q1 TCAN1043HG-Q1 TCAN1043G-Q1 Driver
Short-Circuit Current Test and Measurement

Figure 7-10 Driver Short-Circuit Current Test and Measurement

TCAN1043-Q1 TCAN1043H-Q1 TCAN1043HG-Q1 TCAN1043G-Q1 tPower_Up Timing Measurement

Figure 7-11 t_{Power_Up} Timing Measurement

TCAN1043-Q1 TCAN1043H-Q1 TCAN1043HG-Q1 TCAN1043G-Q1 tWAKE_HT While Monitoring INH Output

Figure 7-12 t_{WAKE_HT} While Monitoring INH Output

TCAN1043-Q1 TCAN1043H-Q1 TCAN1043HG-Q1 TCAN1043G-Q1 tWAKE_HT While Monitoring RXD Output

Figure 7-13 t_{WAKE_HT} While Monitoring RXD Output

8 Detailed Description

8.1 Overview

The TCAN1043xx-Q1 meets or exceeds the specifications of the ISO 11898-2 (2016) High Speed CAN (Controller Area Network) physical layer standard. The device has been certified to the requirements of ISO11898-2/5 according to the GIFT/ICT High Speed CAN test specification.

This device provides CAN transceiver differential transmit capability to the bus and differential receive capability from the bus. The device includes many protection features providing device and CAN bus robustness. All of the devices are available to support CAN and CAN FD (Flexible Data Rate) up to 2Mbps while the G version of the device support CAN and CAN FD data rates up to 5Mbps.

8.2 Functional Block Diagram