ZHCSGR0 数据表 | 德州仪器 TI.com.cn

ZHCSGR0A February 2015 – August 2017 TPS2388

PRODUCTION DATA.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) ⁽¹⁾

		MIN	MAX	UNIT
Input voltage	VPWR	–0.3	70	V
	VDD	–0.3	4	V
	OSS, RESET, A1-A4	–0.3	4	V
	SEN1-8,⁽⁶⁾ KSENSA, KSENSB, KSENSC, KSENSD	–0.3	3	V
Output voltage	GATE1-8⁽²⁾ ⁽⁴⁾	–0.3	12	V
Voltage	SDAI, SDAO ⁽³⁾ , SCL, INT	–0.3	4	V
	DRAIN1-8 ⁽³⁾ ⁽⁵⁾	–0.3	70	V
	TEST0-3, ATST_DCPL0, DTST_DCPL1⁽³⁾	–0.3	4	V
	AGND	–0.3	0.3	V
Sink current	INT, SDAO		20	mA
Lead temperature 1.6 mm (1/16-inch) from case for 10 seconds			260	°C
T_stg	Storage temperature	–65	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Application of voltage is not implied; these are internally driven pins.

(3) Do not apply external voltage sources directly

(4) If the external MOSFET fails short between its drain and gate, the GATE pin may internally permanently disconnect to prevent cascade damage. The three other ports continue to operate.

(5) Short transients (µs range) up to 80 V are allowed

(6) SEN1-8 are tolerant to 15-V transients to avoid fault propagation when a MOSFET fails in short-circuit

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins⁽¹⁾	±2000	V
V_(ESD)	Electrostatic discharge	Charged device model (CDM), per JEDEC specification JESD22-C101, all pins⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

		MIN	NOM	MAX	UNIT
V_VDD		3	3.3	3.6	V
V_VPWR		44	48	57	V
	Voltage slew rate on VPWR			1	V/µs
T_J	Operating junction temperature	–40		125	°C
T_A	Operating free-air temperature	–40		85	°C

6.4 Thermal Information

THERMAL METRIC⁽¹⁾		TPS2388	UNIT
THERMAL METRIC⁽¹⁾		VQFN (56 PINS)	UNIT
R_θJA	Junction-to-ambient thermal resistance	25.3	°C/W
R_θJC(top)	Junction-to-case (top) thermal resistance	9.7
R_θJB	Junction-to-board thermal resistance	3.7
ψ_JT	Junction-to-top characterization parameter	0.2
ψ_JB	Junction-to-board characterization parameter	3.7
R_θJC(bot)	Junction-to-case (bottom) thermal resistance	0.5

(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.

6.5 Electrical Characteristics

–40°C ≤ T_J ≤ 125°C unless otherwise noted. V_VDD = 3.3 V, V_VPWR = 48 V, V_DGND = V_AGND, DGND, KSENSA, KSENSB, KSENSC, and KSENSD connected to AGND, and all outputs are unloaded, unless otherwise noted. PoEPn = 0. Positive currents are into pins. R_S = 0.255 Ω, to KSENSA (SEN1 or SEN2), to KSENSB (SEN3 or SEN4), to KSENSC (SEN5 or SEN6) or to KSENSD (SEN7 or SEN8). Typical values are at 25°C. All voltages are with respect to AGND, unless otherwise noted. Operating registers loaded with default values, unless otherwise noted.

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
INPUT SUPPLY VPWR
I_VPWR	VPWR current consumption	V_VPWR = 50 V		10	12.5	mA
I_VPWR	VPWR current consumption	V_VPWR < 8 V			100	µA
V_{UVLOPW_F}	VPWR UVLO falling threshold		14.5		17.5	V
V_{UVLOPW_R}	VPWR UVLO rising threshold		15.5		18.5	V
V_{PUV_F}	VPWR undervoltage falling threshold	VPUV threshold	25	26.5	28	V
TOTAL DEVICE POWER DISSIPATION
P_T	VPWR and VDD consumption	V_VPWR = 50 V			0.67	W
INPUT SUPPLY VDD
I_VDD	VDD Current consumption			6	12	mA
V_{UVDD_F}	VDD UVLO falling threshold	For port deassertion	2.1	2.25	2.4	V
V_{UVDD_R}	VDD UVLO rising threshold		2.45	2.6	2.75	V
V_{UVDD_HYS}	Hysteresis VDD UVLO			0.35		V
V_{UVW_F}	VDD UVLO warning threshold		2.6	2.8	3.0	V
DETECTION
I_DISC	Detection current	First detection point, V_VPWR – V_DRAINn= 0 V	145	160	190	µA
		Second detection point, V_VPWR – V_DRAINn = 0 V	235	270	300
		High-current detection point, V_VPWR– V_DRAINn = 0 V	490	540	585
V_detect	Open-circuit detection voltage	V_VPWR – V_DRAINn	23.5	26	29	V
R_{REJ_LOW}	Rejected resistance low range		0.86		15	kΩ
R_{REJ_HI}	Rejected resistance high range		33		100	kΩ
R_ACCEPT	Accepted resistance range		19	25	26.5	kΩ
R_SHORT	Shorted port threshold				360	Ω
R_OPEN	Open port threshold		400			kΩ
CLASSIFICATION
V_CLASS	Classification voltage	V_VPWR – V_DRAINn, V_SENn ≥ 0 mV, I_port ≥ 180 µA	15.5	18.5	20.5	V
I_{CLASS_Lim}	Classification current limit	VVPWR – VDRAINn = 0 V	65	75	90	mA
I_{CLASS_TH}	Classification threshold current	Class 0-1	5		8	mA
		Class 1-2	13		16	mA
		Class 2-3	21		25	mA
		Class 3-4	31		35	mA
		Class 4-Class overcurrent	45		51	mA
V_MARK	Mark voltage	4 mA ≥ Iport ≥ 180 µA, VVPWR – VDRAINn	7		10	V
I_{MARK_Lim}	Mark sinking current limit	V_VPWR – V_DRAINn = 0 V	10	70	90	mA
GATE
V_GOH	Gate drive voltage	V_GATEn , I_GATE = –1 µA	10		12.5	V
I_GO-	Gate sinking current with Power-on Reset, OSS detected or port turn off command	V_GATEn = 5 V	60	100	190	mA
I_{GO short–}	Gate sinking current with port short-circuit	V_GATEn = 5 V, V_SENn ≥ V_short (or Vshort2X if 2X mode)	60	100	190	mA
I_GO+	Gate sourcing current	V_GATEn = 0V	39	50	63	µA
DRAIN INPUT
V_PGT	Power Good threshold	Measured at V_DRAINn	1.0	2.13	3	V
V_SHT	Shorted FET threshold	Measured at V_DRAINn	4	6	8	V
R_DRAIN	Resistance from DRAINn to VPWR	Any operating mode except during detection or while the port is ON, including in device RESET state	80	100	190	kΩ
I_DRAIN	DRAINn pin bias current	V_VPWR – V_DRAINn = 30 V, port ON		75	120	µA
A/D CONVERTER
t_CONV	Conversion time, current measurement	All ranges, each port	0.64	0.8	0.96	ms
t_{CONV_V}	Conversion time, voltage measurement	All ranges, each port	0.82	1.03	1.2	ms
t_GAP	Gap between adjacent current measurement integrations				5% × t_CONV	ms
t_GAP	Gap between adjacent current averaged results				5% × t_{INT_CUR}	ms
ADC_BW	ADC integration bandwidth (–3 db)	Current measurement		320		Hz
t_{INT_CUR}	Integration (averaging) time, current	Each port, port ON current	82	102	122	ms
t_{INT_DET}	Integration (averaging) time, detection		13.1	16.6	20	ms
t_{INT_portV}	Integration (averaging) time, port voltage	Port powered	3.25	4.12	4.9	ms
t_{INT_inV}	Integration (averaging) time, input voltage		3.25	4.12	4.9	ms
	Powered port voltage conversion scale factor and accuracy	At V_VPWR – V_DRAINn = 57 V	15097	15565	16032	Counts
	Powered port voltage conversion scale factor and accuracy	At V_VPWR – V_DRAINn = 44 V	11654	12015	12375	Counts
	Powered port current conversion scale factor and accuracy	At port current = 770 mA	12363	12616	12868	Counts
	Powered port current conversion scale factor and accuracy	At port current = 7.5 mA	100	123	150	Counts
	Input voltage conversion scale factor and accuracy	At V_VPWR = 57 V	15175	15565	15955	Counts
	Input voltage conversion scale factor and accuracy	At V_VPWR = 44 V	11713	12015	12316	Counts
δ_V/V_port	Voltage reading accuracy	At 44 to 57 V	–3%		3%
σ_V	Voltage reading repeatability	Full scale reading	–18		18	mV
δ_I/I_port	Current reading accuracy	At 50 mA	–3%		3%
δ_I/I_port	Current reading accuracy	At 770 mA	-2%		2%
σ_I	Current reading repeatability	Full scale reading	–7.5		7.5	mA
δ_R/R_port	Resistance reading accuracy	15 kΩ ≤ R_port ≤ 33 kΩ, C_port ≤ 0.25 µF, at 44 to 57 V	–7%		7%
PORT CURRENT SENSE
V_CUT	I_CUT limit	V_DRAINn = 0 V, POL(3:0) = 0001b	9.6	10.2	10.8	mV
		V_DRAINn = 0 V, POL(3:0) = 0010b	14.53	15.3	16.06
		V_DRAINn = 0 V, POL(3:0) = 0111b	38.76	40.8	42.84
		V_DRAINn = 0 V, POL(3:0) = 1111b	77.5	81.6	85.6
		V_DRAINn = 0 V, POL(3:0) = 0000b, PoEPn = 1	77.5	81.6	85.6
		V_DRAINn = 0 V, POL(3:0) = 1111b, PoEPn = 1	222.8	234.6	246.3
δ_V/V_police	Police setting resolution		–6.3%		6.3%
δ_icut/I_CUT	I_CUT tolerance	All settings except POL(3:0) = 0000b and 0001b while PoEPn = 0	–5%		5%
V_Inrush	I_Inrush limit, 1x or 2x mode	V_VPWR – V_DRAINn = 1 V	10	23	31	mV
		V_VPWR – V_DRAINn = 10 V	20	33	46
		V_VPWR – V_DRAINn = 30 V	102		114.7
		V_VPWR – V_DRAINn = 55 V	102		114.7
V_LIM	I_LIM limit in 1x mode	V_DRAINn = 1 V	102		114.7	mV
		V_DRAINn = 13 V	102		114.7
		V_DRAINn = 30 V	15	23	31
		V_DRAINn = 48 V	15	23	31
V_LIM2X	I_LIM limit in 2X mode (PoEPn = 1)	V_DRAINn = 1 V	260	270.3	285	mV
		V_DRAINn = 10 V	127	140	153
		V_DRAINn = 30 V	15	23	31
		V_DRAINn = 48 V	15	23	31
V_short	I_short threshold in 1X mode and during inrush	Threshold for GATE to be less than 1 V, 2 µS after application of pulse	234		306	mV
V_short2X	I_short threshold in 2X mode		357		408	mV
I_bias	Sense pin bias current	Port ON or during class	–2.5		0	µA
V_IMIN	DC disconnect threshold		1.275		2.55	mV
DIGITAL INTERFACE AT V_VDD = 3.3 V
V_IH	Digital input high		2.1			V
V_IL	Digital input low				0.9	V
V_{IT_HYS}	Input voltage hysteresis (SCL, SDAI, A1-A4, RESET, OSS)		0.17			V
V_OL	Digital output Low, SDAO	At 9 mA			0.4	V
V_OL	Digital output Low, INT	At 3 mA			0.4	V
R_pullup	Pullup resistor to VDD	RESET, A1-A4, TEST0	30	50	80	kΩ
R_pulldown	Pulldown resistor to DGND	OSS	30	50	80	kΩ
R_pulldown	Pulldown resistor to DGND	TEST1, 2	30	50	80	kΩ
THERMAL SHUTDOWN
T_SD	Shutdown temperature	Temperature rising	135	146		°C
T_SD	Hysteresis			7		°C

6.6 Timing Requirements

			MIN	TYP	MAX	UNIT
f_SCL	SCL clock frequency		10		400	kHz
t_LOW	LOW period of the clock		1.3			µs
t_HIGH	HIGH period of the clock		0.6			µs
t_fo	SDAO output fall time	SDAO, 2.3 → 0.8 V, Cb = 10 pF, 10 kΩ pull-up to 3.3 V	21		250	ns
t_fo	SDAO output fall time	SDAO, 2.3 → 0.8 V, Cb = 400 pF, 1.3 kΩ pull-up to 3.3 V	21		250	ns
C_I2C	SCL capacitance				10	pF
C_{I2C_SDA}	SDAI, SDAO capacitance (each)				6	pF
t_SU,DATW	Data set-up time (Write operation)		100			ns
t_SU,DATR	Data set-up time (Read operation)	SDAO, Cb = 10 pF, 1.3 kΩ pull-up to 3.3V	600			ns
t_HD,DATW	Data hold time (Write operation)		0			ns
t_HD,DATR	Data hold time (Read operation)		150		600	ns
t_fSDA	Input fall times of SDAI	2.3 → 0.8 V	20		250	ns
t_rSDA	Input rise times of SDAI	0.8 → 2.3 V	20		300	ns
t_r	Input rise time of SCL	0.8 → 2.3 V	20		300	ns
t_f	Input fall time of SCL	2.3 → 0.8 V	20		200	ns
t_BUF	Bus free time between a STOP and START condition		1.3			µs
t_HD,STA	Hold time after (repeated) Start condition		0.6			µs
t_SU,STA	Repeated Start condition set-up time		0.6			µs
t_SU,STO	Stop condition set-up time		0.6			µs
t_{FLT_INT}	Fault to INT assertion	Time to internally register an Interrupt fault, from port turn off		50	500	µs
t_DG	Suppressed spike pulse width, SDAI and SCL		50			ns
t_RDG	RESET input minimum pulse width (deglitch time)				5	µs
t_{bit_OSS}	3-bit OSS bit period	MbitPrty = 1	24	25	26	µs
t_{OSS_IDL}	Idle time between consecutive shutdown code transmission in 3-bit mode	MbitPrty = 1	48	50		µs
t_{r_OSS}	Input rise time of OSS in 3-bit mode	0.8 → 2.3 V, MbitPrty = 1	1		300	ns
t_{f_OSS}	Input fall time of OSS in 3-bit mode	2.3 → 0.8 V, MbitPrty = 1	1		300	ns
t_{WDT_I2C}	I²C Watchdog trip delay		1.1	2.2	3.3	s

6.7 Switching Characteristics

over operating free-air temperature range (unless otherwise noted)

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
δI_fault	Duty cycle of Iport with current fault		5.5%		6.7%
t_OVLD	ICUT time limit (DCUTn = 0)	TOVLD = 00	50		70	ms
		TOVLD = 01	25		35
		TOVLD = 10	100		140
		TOVLD = 11	200		280
t_{ICUT_INT}	ICUT Interrupt time limit when ICUT is disabled (DCUTn = 1)⁽¹⁾	I_CUT limit exceeded but not I_LIM, TLIM = 01, PoEPn = 1		t_LIM/2	t_LIM/2 + 6	ms
t_LIM	ILIM time limit		50		70	ms
		TLIM = 00, PoEPn = 1	50		70
		TLIM = 01, PoEPn = 1	14.5	15	15.75
		TLIM = 10, PoEPn = 1	11.5	12	12.5
		TLIM = 11, PoEPn = 1	9.5	10	10.5
t_START	Maximum current limit duration in port start-up	TSTART = 00	50		70	ms
		TSTART = 01	25		35
		TSTART = 10	100		140
t_DET	Detection duration, 4-point discovery	Time to complete a detection	275	350	425	ms
t_{DET_BOFF}	Detect backoff pause between discovery attempts	V_VPWR – V_DRAINn > 2.5 V	300	400	500	ms
t_{DET_BOFF}	Detect backoff pause between discovery attempts	V_VPWR – V_DRAINn < 2.5 V	15		100	ms
t_{DET_DLY}	Detection delay	From command or PD attachment to port detection complete			590	ms
t_CLE	Classification duration, first and second class event	Semiauto mode. From detection complete	6.5		12	ms
t_pdc	Classification duration, 1-event physical layer class timing	Semiauto mode. From detection complete	6.5		12	ms
t_pdc		Manual mode. From beginning of class	6.5		14	ms
t_ME	Mark Duration, first and second mark event	Semiauto mode. From Class 4 complete	6		12	ms
t_pon	Port Power-On delay, semiauto mode	From end of detection to port turn on using IEEE power enable			200	ms
t_pon	Port Power-On delay, manual mode	From port turn on command to port turn on completed, four ports			4	ms
t_RESET	Reset time duration from RESET pin		1		5	µs
t_ed	Error delay timing. Delay before next attempt to power a port following power removal due to error condition	ICUT , ILIM or IInrush fault, semiauto mode	0.8	1	1.2	s
t_MPDO	PD maintain power signature dropout time limit	TMPDO = 00	300		400	ms
		TMPDO = 01	75		100
		TMPDO = 10	150		200
		TMPDO = 11	600		800
t_MPS	PD maintain power signature time for validity		13	15	17	ms
t_{D_off_OSS}	Gate turn off time from 1-bit OSS input	From OSS to V_GATEn < 1 V, V_SENn = 0 V, MbitPrty = 0	1		5	µs
t_{OSS_OFF}	Gate turn off time from 3-bit OSS input	From Start bit falling edge to V_GATEn < 1 V, V_SENn = 0 V, MbitPrty = 1	72		104	µs
t_{P_off_CMD}	Gate turn off time from port off command	From port off command to V_GATEn < 1 V, V_SENn = 0 V			300	µs
t_{P_off_RST}	Gate turn off time with RESET	From RESET low to V_GATEn < 1 V, V_SENn = 0 V	1		5	µs
t_{D_off_SEN}	Gate turn off time from SENn input	V_DRAINn = 1 V , From V_SENn pulsed to 0.425 V			0.9	µs
t_{D_off_SEN}	Gate turn off time from SENn input (PoEPn = 1)	V_DRAINn = 1 V , From V_SENn pulsed to 0.62 V			0.9	µs
t_POR	Device power-on reset delay				20	ms

(1) The t_{ICUT_INT} maximum value shown in the table only applies to a low percentage (< 10%) of occurence. The rest of the time, it becomes t_LIM/2 + 2 ms.