ZHCSGQ7C September   2017  – May 2019 TDP142

PRODUCTION DATA.  

  1. 特性
  2. 应用
  3. 说明
    1.     Device Images
      1.      简化电路原理图
      2.      显示屏
  4. 修订历史记录
  5. Pin Configuration and Functions
    1.     Pin Functions
  6. Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Characteristics
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. Parameter Measurement Information
  8. Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DisplayPort
      2. 8.3.2 4-level Inputs
      3. 8.3.3 Receiver Linear Equalization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration in GPIO Mode
      2. 8.4.2 Device Configuration In I2C Mode
      3. 8.4.3 Linear EQ Configuration
      4. 8.4.4 Operation Timing – Power Up
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 General Register (address = 0x0A) [reset = 00000001]
        1. Table 6. General Registers
      2. 8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
        1. Table 7. DisplayPort Control/Status Registers (0x10)
      3. 8.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
        1. Table 8. DisplayPort Control/Status Registers (0x11)
      4. 8.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
        1. Table 9. DisplayPort Control/Status Registers (0x12)
      5. 8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
        1. Table 10. DisplayPort Control/Status Registers (0x13)
  9. Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Source Application Implementation
        1. 9.2.1.1 Design Requirement
        2. 9.2.1.2 Detail Design Procedure
      2. 9.2.2 Sink Application Implementation
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 相关链接
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息

Programming

For further programmability, the TDP142 can be controlled using I2C. When I2C_EN !=0, the SCL and SDA pins are used for I2C clock and I2C data respectively.

Table 4. TDP142 I2C Target Address

DPEQ0/A1
PIN LEVEL
A0
PIN LEVEL
Bit 7 (MSB) Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 (W/R)
0 0 1 0 0 0 1 0 0 0/1
0 R 1 0 0 0 1 0 1 0/1
0 F 1 0 0 0 1 1 0 0/1
0 1 1 0 0 0 1 1 1 0/1
R 0 0 1 0 0 0 0 0 0/1
R R 0 1 0 0 0 0 1 0/1
R F 0 1 0 0 0 1 0 0/1
R 1 0 1 0 0 0 1 1 0/1
F 0 0 0 1 0 0 0 0 0/1
F R 0 0 1 0 0 0 1 0/1
F F 0 0 1 0 0 1 0 0/1
F 1 0 0 1 0 0 1 1 0/1
1 0 0 0 0 1 1 0 0 0/1
1 R 0 0 0 1 1 0 1 0/1
1 F 0 0 0 1 1 1 0 0/1
1 1 0 0 0 1 1 1 1 0/1

The following procedure should be followed to write to TDP142 I2C registers:

  1. The master initiates a write operation by generating a start condition (S), followed by the TDP142 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TDP142 acknowledges the address cycle.
  3. The master presents the sub-address (I2C register within TDP142) to be written, consisting of one byte of data, MSB-first.
  4. The TDP142 acknowledges the sub-address cycle.
  5. The master presents the first byte of data to be written to the I2C register.
  6. The TDP142 acknowledges the byte transfer.
  7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing with an acknowledge from the TDP142.
  8. The master terminates the write operation by generating a stop condition (P).

The following procedure should be followed to read the TDP142 I2C registers:

  1. The master initiates a read operation by generating a start condition (S), followed by the TDP142 7-bit address and a one-value “W/R” bit to indicate a read cycle.
  2. The TDP142 acknowledges the address cycle.
  3. The TDP142 transmit the contents of the memory registers MSB-first starting at register 00h or last read sub-address+1. If a write to the T I2C register occurred prior to the read, then the TDP142 shall start at the sub-address specified in the write.
  4. The TDP142 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
  5. If an ACK is received, the TDP142 transmits the next byte of data.
  6. The master terminates the read operation by generating a stop condition (P).

The following procedure should be followed for setting a starting sub-address for I2C reads:

  1. The master initiates a write operation by generating a start condition (S), followed by the TDP142 7-bit address and a zero-value “W/R” bit to indicate a write cycle.
  2. The TDP142 acknowledges the address cycle.
  3. The master presents the sub-address (I2C register within TDP142) to be written, consisting of one byte of data, MSB-first.
  4. The TDP142 acknowledges the sub-address cycle.
  5. The master terminates the write operation by generating a stop condition (P).

NOTE

If no sub-addressing is included for the read procedure, and reads start at register offset 00h and continue byte by byte through the registers until the I2C master terminates the read operation. If a I2C address write occurred prior to the read, then the reads start at the sub-address specified by the address write.

Table 5. Register Legend

ACCESS TAG NAME MEANING
R Read The field may be read by software
W Write The field may be written by software
S Set The field may be set by a write of one. Writes of zeros to the field have no effect.
C Clear The field may be cleared by a write of one. Write of zero to the field have no effect.
U Update Hardware may autonomously update this field.
NA No Access Not accessible or not applicable