• Menu
  • Product
  • Email
  • PDF
  • Order now

  • TDP142 DisplayPortTM 8.1Gbps 线性转接驱动器

    • ZHCSGQ7C September   2017  – May 2019 TDP142

      PRODUCTION DATA.  

  • CONTENTS
  • SEARCH
  • TDP142 DisplayPortTM 8.1Gbps 线性转接驱动器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化电路原理图
      2.      显示屏
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Supply Characteristics
    6. 6.6  DC Electrical Characteristics
    7. 6.7  AC Electrical Characteristics
    8. 6.8  Timing Requirements
    9. 6.9  Switching Characteristics
    10. 6.10 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 DisplayPort
      2. 8.3.2 4-level Inputs
      3. 8.3.3 Receiver Linear Equalization
    4. 8.4 Device Functional Modes
      1. 8.4.1 Device Configuration in GPIO Mode
      2. 8.4.2 Device Configuration In I2C Mode
      3. 8.4.3 Linear EQ Configuration
      4. 8.4.4 Operation Timing – Power Up
    5. 8.5 Programming
    6. 8.6 Register Maps
      1. 8.6.1 General Register (address = 0x0A) [reset = 00000001]
        1. Table 6. General Registers
      2. 8.6.2 DisplayPort Control/Status Registers (address = 0x10) [reset = 00000000]
        1. Table 7. DisplayPort Control/Status Registers (0x10)
      3. 8.6.3 DisplayPort Control/Status Registers (address = 0x11) [reset = 00000000]
        1. Table 8. DisplayPort Control/Status Registers (0x11)
      4. 8.6.4 DisplayPort Control/Status Registers (address = 0x12) [reset = 00000000]
        1. Table 9. DisplayPort Control/Status Registers (0x12)
      5. 8.6.5 DisplayPort Control/Status Registers (address = 0x13) [reset = 00000000]
        1. Table 10. DisplayPort Control/Status Registers (0x13)
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Source Application Implementation
        1. 9.2.1.1 Design Requirement
        2. 9.2.1.2 Detail Design Procedure
      2. 9.2.2 Sink Application Implementation
        1. 9.2.2.1 Design Requirements
        2. 9.2.2.2 Detailed Design Procedure
      3. 9.2.3 Application Curve
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12器件和文档支持
    1. 12.1 相关链接
    2. 12.2 接收文档更新通知
    3. 12.3 社区资源
    4. 12.4 商标
    5. 12.5 静电放电警告
    6. 12.6 Glossary
  13. 13机械、封装和可订购信息
  14. 重要声明
search No matches found.
  • Full reading width
    • Full reading width
    • Comfortable reading width
    • Expanded reading width
  • Card for each section
  • Card with all content

 

DATA SHEET

TDP142 DisplayPortTM 8.1Gbps 线性转接驱动器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • DisplayPort™1.4 高达 8.1Gbps (HBR3)
  • 超低功耗架构
  • 具有高达 14dB 均衡功能的线性转接驱动器
  • 透明呈现 DisplayPort 链路训练
  • 可通过 GPIO 或 I2C 进行配置
  • 支持热插拔
  • 支持 DisplayPort 双模标准版本 1.1（交流耦合 HDMI）
  • 工业级温度范围：-40ºC 至 85ºC (TDP142I)
  • 商业级温度范围：0ºC 至 70ºC (TDP142)
  • 4mm x 6mm、0.4mm 间距 WQFN 封装

2 应用

  • 平板电脑、笔记本电脑、台式电脑、PC
  • 有源电缆
  • 监视器
  • 扩展坞

3 说明

TDP142 是一款能够嗅探 AUX 和 HPD 信号的 DisplayPortTM(DP) 线性转接驱动器。该器件符合 VESA DisplayPort 标准版本 1.4，支持 1-4 通道主链路接口，以符合 HBR3 标准的速率（每个通道 8.1Gbps）发送信号。此外，该器件与位置无关。它可置于源设备、电缆或接收设备内，从而为总体链路预算有效提供“负损耗”分量。

TDP142 提供多个接收线性均衡级别，用于补偿线缆或电路板走线中因码间串扰 (ISI) 而产生的损耗。该器件由 3.3V 单电源供电，支持商业级温度范围 (TDP142) 和工业级温度范围 (TDP142I)。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
TDP142 WQFN (40) 4.00mm x 6.00mm
TDP142I WQFN (40) 4.00mm x 6.00mm
  1. 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品附录。

Device Images

空白

简化电路原理图

TDP142 simplified_diagram.gif

显示屏

TDP142 Laptop_sllsez1.gif

4 修订历史记录

Changes from B Revision (August 2018) to C Revision

  • Added following to pin 11 description: If I2C_EN = “F”, then this pin must be set to “F” or “0”. Go

Changes from A Revision (October 2017) to B Revision

  • Changed the appearance of the pinout image in the Pin Configuration and Function sectionGo
  • Added Note 2 To pins 29 and 32 in the Pin Functions tableGo

Changes from * Revision (September 2017) to A Revision

  • Changed the Human-body model (HBM) value From: ±6000 To: ±5000 in the ESD RatingsGo

5 Pin Configuration and Functions

RNQ Package
40-Pin (WQFN)
Top View

Pin Functions

PIN I/O DESCRIPTION
NAME NO.
VCC 1, 6, 20, 28 P 3.3-V Power Supply.
DPEQ1 2 4 Level I DisplayPort Receiver EQ control. This along with DPEQ0 will select the DisplayPort receiver equalization gain. Refer to Table 2 for equalization settings.
RSVD1 3 I Reserved.(1)
RSVD2 4 O Reserved.(1)
RSVD3 5 O Reserved.(1)
RSVD4 7 I Reserved.(1)
RSVD5 8 I Reserved.(1)
INDP0p 9 I DP Differential positive input for DisplayPort Lane 0.
INDP0n 10 I DP Differential negative input for DisplayPort Lane 0.
A0 11 4 Level I When I2C_EN = 0, leave the pin unconnected. When I2C_EN is not ‘0’, this pin will also set the TDP142 I2C address. See Table 4. If I2C_EN = “F”, then this pin must be set to “F” or “0”.
INDP1p 12 Diff I DP Differential positive input for DisplayPort Lane 1.
INDP1n 13 Diff I DP Differential negative input for DisplayPort Lane 1.
DPEQ0/A1 14 4 Level I DisplayPort Receiver EQ control. This along with DPEQ1 will select the DisplayPort receiver equalization gain. Refer to Table 2 for equalization settings. When I2C_EN is not ‘0’, this pin will also set the TDP142 I2C address. See Table 4.
INDP2p 15 Diff I DP Differential positive input for DisplayPort Lane 2.
INDP2n 16 Diff I DP Differential negative input for DisplayPort Lane 2.
I2C_EN 17 4 Level I I2C Programming Mode or GPIO Programming Select. I2C is only disabled when this pin is ‘0".
0 = GPIO mode (I2C disabled).
R = TI Test Mode (I2C enabled at 3.3 V).
F = I2C enabled at 1.8 V.
1 = I2C enabled at 3.3 V.
INDP3p 18 Diff I DP Differential positive input for DisplayPort Lane 3.
INDP3n 19 Diff I DP Differential negative input for DisplayPort Lane 3.
TEST1/SCL 21 2 Level I When I2C_EN=’0’, pull down with 10k or directly connect to ground. Otherwise this pin is I2C clock. . When used for I2C clock pullup to I2C master's VCC I2C supply.
TEST2/SDA 22 2 Level I When I2C_EN=’0’ , pull down with 10k or directly connect to ground. Otherwise this pin is I2C data. When used for I2C data pullup to I2C master's VCC I2C supply.
DPEN/HPDIN 23 2 Level I
(Failsafe)
(PD)		 DP Enable Pin. When I2C_EN = ‘0’, this pin will enable or disable DisplayPort functionality. Otherwise, when I2C_EN is not "0", DisplayPort functionality is enabled and disabled through I2C registers.
L = DisplayPort Disabled. (Pull-down with 10k resistor)
H = DisplayPort Enabled. (Pull-up with10k resistor)
When I2C_EN is not "0" this pin is an input for Hot Plug Detect (HPD) received from DisplayPort sink. When this HPDIN is low for greater than 2 ms, all DisplayPort lanes are disabled.
AUXp 24 I/O, CMOS This pin along with AUXN is used by the TDP142 for AUX snooping. See the Application and Implementation section for more detail.
AUXn 25 I/O, CMOS This pin along with AUXP is used by the TDP142 for AUX snooping. See the Application and Implementation section for more detail.
RSVD6 26 I/O, CMOS Reserved.(1)
RSVD7 27 I/O, CMOS Reserved.(1)
SNOOPENZ/RSVD8 29(2) I/O
(PD)		 When I2C_EN ! = 0, this pin is reserved. When I2C_EN = 0 , this pin is SNOOPENZ (L = AUX snoop enabled and H = AUX snoop disabled with all lanes active).
OUTDP3p 30 Diff O DP Differential positive output for DisplayPort Lane 3.
OUTDP3n 31 Diff O DP Differential negative output for DisplayPort Lane 3.
HPDIN/RSVD9 32(2) I/O
(PD)		 When I2C_EN ! = 0, this pin is reserved. When I2C_EN = 0, this pin is an input for Hot Plug Detect received from DisplayPort sink. When HPDIN is low for greater than 2ms, all DisplayPort lanes are disabled.
OUTDP2p 33 Diff O DP Differential positive output for DisplayPort Lane 2.
OUTDP2n 34 Diff O DP Differential negative output for DisplayPort Lane 2.
RSVD10 35 I Reserved.(1)
OUTDP1n 36 Diff O DP Differential negative output for DisplayPort Lane 1.
OUTDP1p 37 Diff O DP Differential positive output for DisplayPort Lane 1.
RSVD11 38 I Reserved.(1)
OUTDP0n 39 Diff O DP Differential negative output for DisplayPort Lane 0.
OUTDP0p 40 Diff O DP Differential positive output for DisplayPort Lane 0.
GND Thermal Pad G Ground.
(1) Leave unconnected on PCB.
(2) Not a fail-safe I/O. Actively driving pin high while VCC is removed results in leakage voltage on VCC pins.

 
Texas Instruments

© Copyright 1995-2025 Texas Instruments Incorporated. All rights reserved.
Submit documentation feedback | IMPORTANT NOTICE | Trademarks | Privacy policy | Cookie policy | Terms of use | Terms of sale