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  • 适用于汽车系统，具有集成式 ADC 和可调湿性电流的 TIC12400-Q1 24 路输入多开关检测接口 (MSDI)

    • ZHCSGP5C August   2017  – February 2022 TIC12400-Q1

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  • 适用于汽车系统，具有集成式 ADC 和可调湿性电流的 TIC12400-Q1 24 路输入多开关检测接口 (MSDI)
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Parameter Measurement Information
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1  VS Pin
      2. 8.3.2  VDD Pin
      3. 8.3.3  Device Initialization
      4. 8.3.4  Device Trigger
      5. 8.3.5  Device Reset
        1. 8.3.5.1 VS Supply POR
        2. 8.3.5.2 Hardware Reset
        3. 8.3.5.3 Software Reset
      6. 8.3.6  VS Under-Voltage (UV) Condition
      7. 8.3.7  VS Over-Voltage (OV) Condition
      8. 8.3.8  Switch Inputs Settings
        1. 8.3.8.1 Input Current Source and Sink Selection
        2. 8.3.8.2 Input Mode Selection
        3. 8.3.8.3 Input Enable Selection
        4. 8.3.8.4 Thresholds Adjustment
        5. 8.3.8.5 Wetting Current Configuration
      9. 8.3.9  Interrupt Generation and INT Assertion
        1. 8.3.9.1 INT Pin Assertion Scheme
        2. 8.3.9.2 Interrupt Idle Time (tINT_IDLE) Time
        3. 8.3.9.3 Microcontroller Wake-Up
        4. 8.3.9.4 Interrupt Enable or Disable and Interrupt Generation Conditions
        5. 8.3.9.5 Detection Filter
      10. 8.3.10 Temperature Monitor
        1. 8.3.10.1 Temperature Warning (TW)
        2. 8.3.10.2 Temperature Shutdown (TSD)
      11. 8.3.11 Parity Check and Parity Generation
      12. 8.3.12 Cyclic Redundancy Check (CRC)
    4. 8.4 Device Functional Modes
      1. 8.4.1 Continuous Mode
      2. 8.4.2 Polling Mode
        1. 8.4.2.1 Standard Polling
        2. 8.4.2.2 Matrix polling
      3. 8.4.3 Additional Features
        1. 8.4.3.1 Clean Current Polling (CCP)
        2. 8.4.3.2 Wetting Current Auto-Scaling
        3. 8.4.3.3 VS Measurement
        4. 8.4.3.4 Wetting Current Diagnostic
        5. 8.4.3.5 ADC Self-Diagnostic
    5. 8.5 Programming
      1. 8.5.1 SPI Communication Interface Buses
        1. 8.5.1.1 Chip Select ( CS)
        2. 8.5.1.2 System Clock (SCLK)
        3. 8.5.1.3 Slave In (SI)
        4. 8.5.1.4 Slave Out (SO)
      2. 8.5.2 SPI Sequence
        1. 8.5.2.1 Read Operation
        2. 8.5.2.2 Write Operation
        3. 8.5.2.3 Status Flag
    6. 8.6 Register Maps
    7. 8.7 Programming Guidelines
  9. 9 Application Information Disclaimer
    1. 9.1 Application Information
    2. 9.2 Using TIC12400-Q1 in a 12 V Automotive System
    3. 9.3 Resistor-coded Switches Detection in Automotive Body Control Module
      1. 9.3.1 Design Requirements
      2. 9.3.2 Detailed Design Procedure
      3. 9.3.3 Application Curves
  10. 10Power Supply Recommendations
  11. 11Layout
    1. 11.1 Layout Guidelines
    2. 11.2 Layout Example
  12. 12Device and Documentation Support
    1. 12.1 接收文档更新通知
    2. 12.2 支持资源
    3. 12.3 Trademarks
    4. 12.4 Electrostatic Discharge Caution
    5. 12.5 术语表
  13. 13Mechanical, Packaging, and Orderable Information
  14. 重要声明
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DATA SHEET

适用于汽车系统，具有集成式 ADC 和可调湿性电流的 TIC12400-Q1 24 路输入多开关检测接口 (MSDI)

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 符合汽车应用要求
  • 具有符合 AEC-Q100 标准的下列特性：
    • 器件温度等级 1：–40°C 至 125°C 的工作环境温度范围
    • 器件 HBM ESD 分类等级 H2
    • 器件 CDM ESD 分类等级 C4B
  • 提供功能安全
    • 有助于进行功能安全系统设计的文档
  • 旨在支持 12V 汽车系统，并提供过压和欠压警告
  • 监控多达 24 路直接开关输入，并可配置其中 10 路输入以监控接地或连接到电池的开关
  • 开关输入可承受高达 40V 的电压（负载突降条件）和低至 −24V 的电压（反极性条件）
  • 6 种可配置的湿性电流设置：
    （0mA、1mA、2mA、5mA、10mA 和 15mA）
  • 适用于多位模拟开关监控的 10 位集成 ADC
  • 适用于数字开关监控并具有 4 个可编程阈值的集成比较器
  • 轮询模式下的超低工作电流：
    68μA 典型值（tPOLL = 64ms，tPOLL_ACT = 128μs，
    全部 24 路输入均有效，比较器模式，所有开关均打开）
  • 使用 3.3V/5V 串行外设接口 (SPI) 协议直接与 MCU 对接
  • 可产生中断来支持所有输入的唤醒操作
  • 集成电池和温度传感
  • 采用适当的外部组件根据 ISO-10605 在输入引脚上实现 ±8kV 接触放电 ESD 保护
  • 38 引脚 TSSOP 封装

2 应用

  • 车身控制模块和网关
  • 汽车照明
  • 制热和制冷
  • 电动座椅
  • 后视镜

3 说明

TIC12400-Q1 是一款先进的多开关检测接口 (MSDI)，用于检测 12V 汽车系统中的外部开关状态。TIC12400-Q1 配有集成的 10 位 ADC，用于对多位模拟开关进行监控，并采用比较器以独立于 MCU 的方式对数字开关进行监控。可为 ADC 和比较器设定检测阈值，从而支持各种开关拓扑和系统非理想特性。该器件监控多达 24 路直接开关输入，并可配置其中 10 路输入以监控接地或连接到电池的开关。可为每路输入设定 6 种独特的湿性电流设置，从而支持不同的应用场景。该器件支持所有开关输入的唤醒操作，因此无需持续使 MCU 保持活动状态，进而可降低系统功耗。TIC12400-Q1 还提供集成故障检测、ESD 保护和诊断功能，从而提高系统稳健性。TIC12400-Q1 支持 2 种工作模式：连续模式和轮询模式。连续模式下将连续提供湿性电流。轮询模式下将根据可编程计时器来定期接通湿性电流以对输入状态进行采样，从而显著降低系统功耗。

器件信息
器件型号 封装(1) 封装尺寸（标称值）
TIC12400-Q1 TSSOP (38) 9.70mm × 4.40mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
GUID-E9BB7795-0539-4F3C-B582-C39F591771ED-low.gif简化版原理图

4 Revision History

Changes from Revision B (February 2020) to Revision C (February 2022)

  • 添加了特性“提供功能安全”Go
  • 将提到的旧术语实例全部更改为控制器和响应器Go

Changes from Revision A (September 2017) to Revision B (February 2020)

  • Added ADC error for 0 mA current setting in Section 6.5 tableGo
  • Added RIN_SC spec for VS above 7 V in Section 6.5 tableGo
  • Added RIN_COMP spec for VS above 7 V in Section 6.5 tableGo
  • Changed WC_CFG0 for CSO and CSI in matrix mode in Table 8-59 Go

Changes from Revision * (August 2017) to Revision A (September 2017)

  • Changed the IWETT value in the Electrical Characteristics tableGo
  • Changed From: 4.5 V ≤ VS ≤ 5 V To: 4.5 V ≤ VS < 5.5 V in Figure 6-6 Go
  • Changed From: 4.5 V ≤ VS ≤ 35 V To: 5.5 V ≤ VS ≤ 35 V in Figure 6-7 Go
  • Changed the Microcontroller Wake-Up section, and Figure 8-9 Go
  • Changed Table 9-5 Go
  • Changed text in list item 2 From: current ranging between 4.3 mA and 5.6 mA. To: current ranging between 4.5 mA and 5.5 mA (for VS – INX ≥ 3 V condition). Go

5 Pin Configuration and Functions

GUID-18BF8B18-242E-490F-A38B-23421FA531C1-low.gifFigure 5-1 DCP (TSSOP) Package, 38-Pin, Top View
Pin Functions
PIN TYPE(1) DESCRIPTION
NO. NAME
1 IN13 I/O Ground switch monitoring input with current source.
2 IN14 I/O Ground switch monitoring input with current source.
3 IN15 I/O Ground switch monitoring input with current source.
4 IN16 I/O Ground switch monitoring input with current source.
5 IN17 I/O Ground switch monitoring input with current source.
6 IN18 I/O Ground switch monitoring input with current source.
7 IN19 I/O Ground switch monitoring input with current source.
8 IN20 I/O Ground switch monitoring input with current source.
9 AGND P Ground for analog circuitry.
10 IN21 I/O Ground switch monitoring input with current source.
11 IN22 I/O Ground switch monitoring input with current source.
12 IN23 I/O Ground switch monitoring input with current source.
13 IN0 I/O Ground/VBAT switch monitoring input with configurable current sink or source.
14 IN1 I/O Ground/VBAT switch monitoring input with configurable current sink or source.
15 CS I Active-low input. Chip select from the controller for the SPI Interface.
16 SCLK I Serial clock output from the controller for the SPI Interface.
17 SI I Serial data input for the SPI Interface.
18 SO O Serial data output for the SPI Interface.
19 VDD P 3.3 V to 5.0 V logic supply for the SPI communication. The SPI I/Os are not fail-safe protected: VDD needs to be present during any SPI traffic to avoid excessive leakage currents and corrupted SPI I/O logic levels.
20 CAP_A I/O External capacitor connection for the analog LDO. Use capacitance value of 100 nF.
21 RESET I Keep RESET low for normal operation and drive RESET high and release it to perform a hardware reset of the device. The RESET pin is connected to ground via a 1MΩ pull-down resistor. If not used, the RESET pin shall be grounded to avoid any accidental device reset due to coupled noise onto this pin.
22 CAP_Pre I/O External capacitor connection for the pre-regulator. Use capacitance value of 1 μF.
23 CAP_D I/O External capacitor connection for the digital LDO. Use capacitance value of 100 nF.
24 INT O Open drain output. Pulled low (internally) upon change of state on the input or occurrence of a special event.
25 IN2 I/O Ground/VBAT switch monitoring input with configurable current sink or source.
26 IN3 I/O Ground/VBAT switch monitoring input with configurable current sink or source.
27 IN4 I/O Ground/VBAT switch monitoring input with configurable current sink or source.
28 DGND P Ground for digital circuitry.
29 IN5 I/O Ground/VBAT switch monitoring input with configurable current sink or source.
30 IN6 I/O Ground/VBAT switch monitoring input with configurable current sink or source.
31 IN7 I/O Ground/VBAT switch monitoring input with configurable current sink or source.
32 IN8 I/O Ground/VBAT switch monitoring input with configurable current sink or source.
33 IN9 I/O Ground/VBAT switch monitoring input with configurable current sink or source.
34 IN10 I/O Ground switch monitoring input with current source.
35 IN11 I/O Ground switch monitoring input with current source.
36 IN12 I/O Ground switch monitoring input with current source.
37 VS P Power supply input pin.
38 VS P Power supply input pin.
--- EP P Exposed Pad. The exposed pad is not electrically connected to AGND or DGND. Connect EP to the board ground to achieve rated thermal and ESD performance.
(1) I = input, O = output, I/O = input and output, P = power.

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted).(1)
MIN MAX UNIT
Input voltage VS, INT -0.3 40(2) V
VDD, SCLK, SI, SO, CS, RESET -0.3 6 V
IN0- IN23 -24 40(2) V
CAP_Pre -0.3 5.5 V
CAP_A -0.3 5.5 V
CAP_D -0.3 2 V
Operating junction temperature, TJ -40 150 °C
Storage temperature, Tstg -55 155 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Tested for load dump and jump start conditions with nominal operating voltage no greater than 16 V for the life of a 12-V automotive system. Refer to Section 9.2 for more details.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per AEC Q100-002(1) All pins ±2000 V
Pins IN0-IN23(2) ±4000
Charged-device model (CDM), per AEC Q100-011 All pins ±500
Corner pins (pin 1, 19, 20 and 38) ±750
Contact discharge, un-powered, per ISO- 10605:
  • External components: capacitor = 15 nF; resistor = 10 Ω
  • ESD generator parameters: storage capacitance = 150 pF; discharge resistance = 330 Ω or 2000 Ω
 Pins IN0-IN23 ±8000
Contact discharge, powered-up, per ISO- 10605:
  • External components: capacitor = 15 nF; resistor = 33 Ω
  • ESD generator parameters: storage capacitance = 150 pF or 330pF; discharge resistance = 330 Ω or 2000 Ω
 Pins IN0-IN23 ±8000
(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.
(2) ±4-kV rating on pins IN0-IN23 are stressed with respect to GND (with AGND, DGND, and EP tied together).

6.3 Recommended Operating Conditions

Over operating free-air temperature range and VS = 12 V (unless otherwise noted).
MIN NOM MAX UNIT
VS Power supply voltage 4.5 35 (2) V
VDD Logic supply voltage 3.0 5.5 V
V/INT INT pin voltage 0 35(2) V
VINX IN0 to IN23 input voltage 0 35(2) V
VRESET RESET pin voltage 0 5.5 V
VSPI_IO SPI input/output logic level 0 VDD V
fSPI SPI communication frequency 20(1) 4M Hz
TA Operating free-air temperature -40 125 °C
(1) Lowest frequency characterized.
(2) Tested for load dump and jump start conditions with nominal operating voltage no greater than 16-V for the life of a 12-V automotive system. Refer to Section 9.2 for more details.

6.4 Thermal Information

THERMAL METRIC(1)TIC12400-Q1UNIT
DCP (TSSOP)
38 PINS
RθJAJunction-to-ambient thermal resistance33.6°C/W
RθJC(top)Junction-to-case (top) thermal resistance18.4°C/W
RθJBJunction-to-board thermal resistance15.2°C/W
ψJTJunction-to-top characterization parameter0.5°C/W
ψJBJunction-to-board characterization parameter15.0°C/W
RθJC(bot)Junction-to-case (bottom) thermal resistance1.2°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

6.5 Electrical Characteristics

Over operating free-air temperature range, VS = 4.5 V to 35 V, and VDD = 3 V to 5.5 V (unless otherwise noted).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
POWER SUPPLY
IS_CONTContinuous mode VS power supply currentContinuous mode, IWETT= 10 mA, all switches open, no active ADC conversion or comparator comparison, no unserviced interrupt5.67mA
IS_POLL_COMP_25Polling mode VS power supply average current in comparator modeTA= 25°Polling mode, tPOLL= 64 ms, tPOLL_ACT= 128 µs, all 24 channels active and configured to comparator mode, all switches open, IWETT= 10 mA, no unserviced interrupt68100µA
IS_POLL_COMP_85TA= -40° to 85°C68110µA
IS_POLL_COMPTA= -40° to 125°C68170µA
IS_POLL_ADC_25Polling mode VS power supply average current in ADC modeTA= 25°Polling mode, tPOLL= 64 ms, tPOLL_ACT= 128 µs, all 24 channels active and configured to ADC mode, all switches open, IWETT= 10 mA, no unserviced interrupt75105µA
IS_POLL_ADC_85TA= -40° to 85°C75120µA
IS_POLL_ADCTA= -40° to 125°C75180µA
IS_RESETReset mode VS power supply currentReset mode, VRESET= VDD. VS= 12 V, all switches open, TA=25°C1217µA
IS_IDLE_25VS power supply average current in idle stateTRIGGER bit in CONFIG register = logic 0, TA= 25°C, no unserviced interrupt5075µA
IS_IDLE_85TRIGGER bit in CONFIG register = logic 0, TA= -40°C to 85°C, no unserviced interrupt5095µA
IS_IDLETRIGGER bit in CONFIG register = logic 0, TA= -40°C to 125°C, no unserviced interrupt50145µA
IDDLogic supply current from VDDSCLK = SI = 0 V, CS = INT = VDD, no SPI communication1.510µA
VPOR_RPower on reset (POR) voltage for VSThreshold for rising VS from device OFF condition resulting in INT pin assertion and a flagged POR bit in the INT_STAT register3.854.5V
VPOR_FThreshold for falling VS from device normal operation to reset mode and loss of SPI communication1.952.8V
VOV_ROver-voltage (OV) condition for VSThreshold for rising VS from device normal operation resulting in INT pin assertion and a flagged OV bit in the INT_STAT register3540V
VOV_HYSTOver-voltage (OV) condition hysteresis for VS13.5V
VUV_RUnder-voltage (UV) condition for VSThreshold for rising VS from under-voltage condition resulting in INT pin assertion and a flagged UV bit in the INT_STAT register3.854.5V
VUV_FThreshold for falling VS from under-voltage condition resulting in INT pin assertion and a flagged UV bit in the INT_STAT register3.74.4V
VUV_HYSTUnder-voltage (UV) condition hysteresis for VS(1)75275mV
VDD_FThreshold for falling VDD resulting in loss of SPI communication2.52.9V
VDD_HYSTValid VDD voltage hysteresis50150mV
WETTING CURRENT ACCURACY (DIGITAL SWITCHES, MAXIMUM RESISTANCE VALUE WITH SWITCH CLOSED ≤ 100Ω , MINIMUM RESISTANCE VALUE WITH SWITCH OPEN ≥ 5000 Ω)
IWETT (CSO)Wetting current accuracy for CSO (switch closed)1 mA setting4.5 V ≤ VS ≤ 35 V0.8411.14mA
2 mA setting1.7122.32
5 mA setting4.5 V ≤ VS < 5 V2.395.5
5 V ≤ VS ≤ 35 V4.355.6
10 mA setting4.5 V ≤ VS < 6 V2.411
6 V ≤ VS ≤ 35 V8.41011.4
15 mA setting4.5 V ≤ VS < 6.5 V2.416.5
6.5 V ≤ VS ≤ 35 V12.51517
IWETT (CSI)Wetting current accuracy for CSI (switch closed)1 mA setting4.5 V ≤ VS ≤ 35 V0.751.12.05mA
2 mA setting1.62.23.3
5 mA setting4.35.67.1
10 mA setting9.211.513.4
15 mA setting4.5 V ≤ VS < 6 V1116.519.2
6 V ≤ VS ≤ 35 V13.716.519.2
VCSI_DROP_OPENVoltage drop from INx pin to AGND across CSI (switch open)10 mA setting, RSW= 5 kΩ4.5 V ≤ VS ≤ 35 V1.7V
15 mA setting, RSW= 5 kΩ1.7
VCSI_DROP_CLOSEDVoltage drop from INx pin to ground across CSI (switch closed)2 mA setting, IIN= 1 mA (4.5V ≤ VS ≤ 35V)4.5 V ≤ VS ≤ 35 V1.2V
5 mA setting, IIN= 1mA or 2 mA1.3V
10 mA setting, IIN= 1 mA, 2 mA, or 5 mA1.5V
15 mA setting, IIN= 1 mA, 2 mA, 5 mA, or 10 mA2.1V
WETTING CURRENT ACCURACY (ANALOG SWITCHES)
IWETTWetting current accuracy1 mA setting4.5 V ≤ VS ≤ 35 V, VS – VINX ≥ 2.5 V0.8811.13mA
2 mA setting1.822.25
5 mA setting5.5 V ≤ VS ≤ 35 V, VS – VINX ≥ 2.5 V4.355.5
5.5 V ≤ VS ≤ 35 V, VS – VINX ≥ 3 V4.555.5
10 mA setting6 V ≤ VS ≤ 35 V, VS – VINX ≥ 4 V91011
15 mA setting6.5 V ≤ VS ≤ 35 V, VS – VINX ≥ 5 V12.51516.5
LEAKAGE CURRENTS
IIN_LEAK_OFFLeakage current at input INx when channel is disabled0 V ≤ VINx ≤ VS , channel disabled (EN_INx register bit= logic 0)-45.3µA
IIN_LEAK_OFF_250 V ≤ VINx ≤ VS , channel disabled (EN_INx register bit= logic 0), TA = 25°C-0.50.5
IIN_LEAK_0mALeakage current at input INx when wetting current setting is 0mA0 V ≤ VINx ≤ 6 V, 6 V ≤ VS ≤ 35 V , IWETT setting = 0 mA-110110µA
µA
IIN_LEAK_LOSS_OF_GNDLeakage current at input INx under loss of GND conditionVS = 24 V, 0 V ≤ VINx ≤ 24 V, all grounds (AGND, DGND, and EP) = 24 V, VDD shorted to the grounds(1)-5µA
IIN_LEAK_LOSS_OF_VSLeakage current at input INx under loss of VS condition0 V ≤ VINx ≤ 24 V, VS shorted to the grounds = 0 V, VDD = 0 V5µA
LOGIC LEVELS
V/INT_LINT output low voltageI/INT = 2 mA0.35V
I/INT = 4 mA0.6
VSO_LSO output low voltageISO = 2 mA0.2VDDV
VSO_HSO output high voltageISO = -2 mA0.8VDDV
VIN_LSI, SCLK, and CS input low voltage0.3VDDV
VIN_HSI, SCLK, and CS input high voltage0.7VDDV
VRESET_LRESET input low voltage0.8V
VRESET_HRESET input high voltage1.6V
RRESET_25RESET pin internal pull-down resistorVRESET= 0 to 5.5 V, TA =25°C0.851.251.7MΩ
RRESETVRESET= 0 to 5.5 V, TA = –40° to 125°C0.22.1
SWITCH INPUT AND VS MEASUREMENT CONVERSION PARAMETERS
RESResolution10Bits
VOFFSETADC Offset error0 mA setting–101LSB
VFSEADC Full-scale error0 mA setting–10010LSB
OUTSWSwitch input conversion output1 mA setting4.5 V ≤ VS ≤ 35 V, 100 Ω resistance to ground at INx121726LSB
4.5 V ≤ VS ≤ 35 V, 300 Ω resistance to ground at INx425164
4.5 V ≤ VS ≤ 35 V, 600 Ω resistance to ground at INx87102122
2 mA setting4.5 V ≤ VS ≤ 35 V, 100 Ω resistance to ground at INx283445LSB
4.5 V ≤ VS ≤ 35 V, 300 Ω resistance to ground at INx89102122
4.5 V ≤ VS ≤ 35 V, 600 Ω resistance to ground at INx181205236
5 mA setting5 V ≤ VS ≤ 35 V, 100 Ω resistance to ground at INx7285105LSB
5 V ≤ VS ≤ 35 V, 300 Ω resistance to ground at INx223256296
5 V ≤ VS ≤ 35 V, 600 Ω resistance to ground at INx393512620
10 mA setting6 V ≤ VS ≤ 35 V, 100 Ω resistance to ground at INx142171202LSB
6 V ≤ VS ≤ 35 V, 250 Ω resistance to ground at INx333427486
6 V ≤ VS ≤ 35 V, 400 Ω resistance to ground at INx430683823
15 mA setting6.5 V ≤ VS ≤ 35 V, 100 Ω resistance to ground at INx166256301LSB
6.5 V ≤ VS ≤ 35 V, 200 Ω resistance to ground at INx325512582
6.5 V ≤ VS ≤ 35 V, 300 Ω resistance to ground at INx450768879
OUTVSVS measurement output tolerance to full-scale rangeVS measurements (VS ≥ 4.5 V), VS_RATIO= 0 in register CONFIG±2%
VS measurements (VS ≥ 4.5 V), VS_RATIO= 1 in register CONFIG±2%
VFSRInput full-scale rangeINx measurements6V
VS measurements (VS ≥ 4.5 V), VS_RATIO= 0 in register CONFIG9
VS measurements (VS ≥ 4.5 V), VS_RATIO= 1 in register CONFIG30
RIN, SCInput resistanceINx measurements240kΩ
ADC Equivalent input resistance, VS above 7 VInput switch measurement, ILOAD= 30 µA135234356kΩ
RIN, COMPADC Equivalent input resistance, VS above 7 VTHRES_COMP Setting = 2 V88130172kΩ
THRES_COMP Setting = 2.7 V85126170
THRES_COMP Setting = 3 V73105137
THRES_COMP Setting = 4 V6895124
RRATIOInput voltage divider factor(1)INx measurements2-
VS measurements (VS ≥ 4.5 V), VS_RATIO = 0 in register CONFIG3-
VS measurements (VS ≥ 4.5 V), VS_RATIO = 1 in register CONFIG10-
COMPARATOR PARAMETERS
VTH_ COMP_2VComparator threshold for 2 VTHRES_COMP = 2 V1.852.25V
VTH_ COMP_2p7VComparator threshold for 2.7 VTHRES_COMP = 2.7 V2.42.9V
VTH_ COMP_3VComparator threshold for 3 VTHRES_COMP = 3 V2.853.3V
VTH_ COMP_4VComparator threshold for 4 VTHRES_COMP = 4 V3.74.35V
VS_COMPMinimum VS requirement for proper detectionTHRES_COMP = 2 V4.5V
THRES_COMP = 2.7 V5
THRES_COMP = 3 V5.5
THRES_COMP = 4 V6.5
RIN, COMPComparator equivalent input resistanceTHRES_COMP = 2 V30130kΩ
THRES_COMP = 2.7 V35130
THRES_COMP = 3 V35105
THRES_COMP = 4 V4395
(1) Verified by design.

6.6 Timing Requirements

VS= 4.5 V to 35 V, VDD= 3 V to 5.5 V, and 10 pF capacitive load on SO unless otherwise noted; verified by design and characterization.
PARAMETERTEST CONDITIONMINNOMMAXUNIT
SWITCH MONITORING, INTERRUPT, STARTUP AND RESET
tPOLL_ACTPolling active time accuracyPolling mode-12%12%
tPOLL_ACT_MPolling active time accuracy for matrix inputsPolling mode with matrix enabled-12%12%
tPOLLPolling time accuracyPolling mode-12%12%
tCOMPComparator detection time18µs
tADCADC Conversion timeSample and hold time included24µs
tCCP_TRANTransition time between last input sampling and start of clean current20µs
tCCP_ACTClean current active time-12%12%
tSTARTUPPolling startup time200300400µs
tINT_ACTIVEActive INT assertion duration1.522.5ms
tINT_INACTIVEINT de-assertion duration during a pending interrupt345ms
tINT_IDLEInterrupt idle time80100120µs
tRESETTime required to keep the RESET pin high to successfully reset the device (no pending interrupt)(1)2µs
tREACTDelay between a fault event (OV, UV, TW, or TSD) to a high to low transition on the INT pinSee Figure 7-2 for OV example.20µs
SPI INTERFACE
tLEADFalling edge of CS to rising edge of SCLK setup time100ns
tLAGFalling edge of SCLK to rising edge of CS setup time100ns
tSUSI to SCLK falling edge setup time30ns
tHOLDSI hold time after falling edge of SCLK20ns
tVALIDTime from rising edge of SCLK to valid SO data70ns
tSO(EN)Time from falling edge of CS to SO low-impedance60ns
tSO(DIS)Time from rising edge of CS to SO high-impedanceLoading of 1 kΩ to GND. See Figure 7-3.60ns
tRSI, CS, and SCLK signals rise time530ns
tFSI, CS, and SCLK signals fall time530ns
tINTER_FRAMEDelay between two SPI communication ( CS low) sequences1.5µs
tCKHSCLK High time120ns
tCKLSCLK Low time120ns
tINITIATIONDelay between valid VDD voltage and initial SPI communication45µs
(1) If there is a pending interrupt (/INT pin asserted low), it can take up to 1ms for the device to complete the reset.

6.7 Typical Characteristics

GUID-A8196AAB-3629-4E33-90C3-0949A8C22052-low.gif
TA = 25°C
Figure 6-1 Wetting Current Output - CSO vs. VS Voltage
GUID-D13E5CC3-75B1-433F-8A88-CB6E840AE2E6-low.gif
TA = 25°C
Figure 6-3 Comparator Threshold vs. VS Voltage
GUID-4B8895E0-13F3-40A0-BB96-F8208546E408-low.gif
I(WETT) = 2 mA4.5 V ≤ VS ≤ 35 V
Figure 6-5 ADC Code vs. Equivalent Input Resistance
GUID-775A00FB-8DB2-42D2-9FC9-0DF0F28417D6-low.gif
I(WETT) = 5 mA5.5 V ≤ VS ≤ 35 V
Figure 6-7 ADC Code vs. Equivalent Input Resistance
GUID-A4A4B3CC-4EF1-4313-9A69-15CEDE6C36BD-low.gif
I(WETT) = 10 mA6 V ≤ VS ≤ 35 V
Figure 6-9 ADC Code vs. Equivalent Input Resistance
GUID-002A38DF-5F92-4B65-A2E6-9614E659A1AD-low.gif
I(WETT) = 15 mA6.5 V ≤ VS ≤ 35 V
Figure 6-11 ADC Code vs. Equivalent Input Resistance
GUID-281DE01C-09D5-4C1C-927C-89BEDE706E6F-low.gif
VS = 12 V
Figure 6-2 Wetting Current Output - CSO vs. Temperature
GUID-BC287B54-8714-4A2F-B8F1-A5A4627F3E45-low.gif
I(WETT) = 1 mA4.5 V ≤ VS ≤ 35 V
Figure 6-4 ADC Code vs. Equivalent Input Resistance
GUID-F68D2262-95AA-444A-BCC2-11F2803F512C-low.gif
I(WETT) = 5 mA4.5 V ≤ VS < 5.5 V
Figure 6-6 ADC Code vs. Equivalent Input Resistance
GUID-C7A47155-4426-4D59-8A79-CD8EAD087B58-low.gif
I(WETT) = 10 mA4.5 V ≤ VS < 6 V
Figure 6-8 ADC Code vs. Equivalent Input Resistance
GUID-DCCB8968-E8EB-4473-88D9-2334938A9533-low.gif
I(WETT) = 15 mA4.5 V ≤ VS < 6.5 V
Figure 6-10 ADC Code vs. Equivalent Input Resistance

7 Parameter Measurement Information

GUID-39A48FF4-B2E3-4422-B034-5576CEC2CD33-low.gif Figure 7-1 SPI Timing Parameters
GUID-1311EB1D-8F1B-4552-B6D8-D269FCF0C876-low.gif Figure 7-2 tREACT Timing Parameters
GUID-FFBE8105-9032-4E20-8278-AAC68342C9B8-low.gif Figure 7-3 tSO(DIS) Timing Parameters

8 Detailed Description

8.1 Overview

The TIC12400-Q1 is an advanced 24-input Multiple Switch Detection Interface (MSDI) device designed to detect external mechanical switch status in a 12 V automotive system by acting as an interface between the switches and the low-voltage microcontroller. The TIC12400-Q1 is an integrated solution that replaces many discrete components and provides integrated protection, input serialization, and system wake-up capability.

The device monitors 14 switches to GND and 10 additional switches that can be programmed to be connected to either GND or VBAT. It features SPI interface to report individual switch status and provides programmability to control the device operation. The TIC12400-Q1 features a 10-bit ADC which is useful to monitor analog inputs such as resistor coded switches that have multiple switching positions. To monitor only digital switches, an integrated comparator can be used instead to monitor the input status. The device has 2 modes of operation: continuous mode and polling mode. The polling mode is a low-power mode that can be activated to reduce current drawn in the system by only turning on the wetting current for a small duty cycle to detect switch status changes. An interrupt is generated upon detection of switch status change and it can be used to wake up the microcontroller to bring the entire system back to operation.

 
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