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  • 用于水计量应用的 MSP430FR604x(1)、MSP430FR603x(1)、超声波感应 MSP430™ 微控制器

    • ZHCSGO9C June   2017  – September 2018 MSP430FR6035 , MSP430FR6037 , MSP430FR60371 , MSP430FR6045 , MSP430FR6047 , MSP430FR60471

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  • 用于水计量应用的 MSP430FR604x(1)、MSP430FR603x(1)、超声波感应 MSP430™ 微控制器
  1. 1器件概述
    1. 1.1 特性
    2. 1.2 应用
    3. 1.3 说明
    4. 1.4 功能框图
  2. 2修订历史记录
  3. 3Device Comparison
    1. 3.1 Related Products
  4. 4Terminal Configuration and Functions
    1. 4.1 Pin Diagram
    2. 4.2 Pin Attributes
    3. 4.3 Signal Descriptions
      1. Table 4-2 Signal Descriptions
    4. 4.4 Pin Multiplexing
    5. 4.5 Buffer Type
    6. 4.6 Connection of Unused Pins
  5. 5Specifications
    1. 5.1  Absolute Maximum Ratings
    2. 5.2  ESD Ratings
    3. 5.3  Recommended Operating Conditions
    4. 5.4  Active Mode Supply Current Into VCC Excluding External Current
    5. 5.5  Typical Characteristics, Active Mode Supply Currents
    6. 5.6  Low-Power Mode (LPM0, LPM1) Supply Currents Into VCC Excluding External Current
    7. 5.7  Low-Power Mode (LPM2, LPM3, LPM4) Supply Currents (Into VCC) Excluding External Current
    8. 5.8  Low-Power Mode With LCD Supply Currents (Into VCC) Excluding External Current
    9. 5.9  Low-Power Mode (LPMx.5) Supply Currents (Into VCC) Excluding External Current
    10. 5.10 Typical Characteristics, Low-Power Mode Supply Currents
    11. 5.11 Typical Characteristics, Current Consumption per Module
    12. 5.12 Thermal Resistance Characteristics for 100-Pin LQFP (PZ) Package
    13. 5.13 Timing and Switching Characteristics
      1. 5.13.1  Power Supply Sequencing
        1. Table 5-1 Brownout and Device Reset Power Ramp Requirements
        2. Table 5-2 SVS
      2. 5.13.2  Reset Timing
        1. Table 5-3 Reset Input
      3. 5.13.3  Clock Specifications
        1. Table 5-4 Low-Frequency Crystal Oscillator, LFXT
        2. Table 5-5 High-Frequency Crystal Oscillator, HFXT
        3. Table 5-6 DCO
        4. Table 5-7 Internal Very-Low-Power Low-Frequency Oscillator (VLO)
        5. Table 5-8 Module Oscillator (MODOSC)
      4. 5.13.4  Wake-up Characteristics
        1. Table 5-9  Wake-up Times From Low-Power Modes and Reset
        2. Table 5-10 Typical Wake-up Charges
        3. 5.13.4.1   Typical Characteristics, Average LPM Currents vs Wake-up Frequency
      5. 5.13.5  Digital I/Os
        1. Table 5-11 Digital Inputs
        2. Table 5-12 Digital Outputs
        3. 5.13.5.1   Typical Characteristics, Digital Outputs
      6. 5.13.6  LEA
        1. Table 5-13 Low-Energy Accelerator (LEA) Performance
      7. 5.13.7  Timer_A and Timer_B
        1. Table 5-14 Timer_A
        2. Table 5-15 Timer_B
      8. 5.13.8  eUSCI
        1. Table 5-16 eUSCI (UART Mode) Clock Frequency
        2. Table 5-17 eUSCI (UART Mode) Switching Characteristics
        3. Table 5-18 eUSCI (SPI Master Mode) Clock Frequency
        4. Table 5-19 eUSCI (SPI Master Mode) Switching Characteristics
        5. Table 5-20 eUSCI (SPI Slave Mode) Switching Characteristics
        6. Table 5-21 eUSCI (I2C Mode) Switching Characteristics
      9. 5.13.9  Segment LCD Controller
        1. Table 5-22 LCD_C Recommended Operating Conditions
        2. Table 5-23 LCD_C Electrical Characteristics
      10. 5.13.10 ADC12_B
        1. Table 5-24 12-Bit ADC, Power Supply and Input Range Conditions
        2. Table 5-25 12-Bit ADC, Timing Parameters
        3. Table 5-26 12-Bit ADC, Linearity Parameters
        4. Table 5-27 12-Bit ADC, Dynamic Performance With External Reference
        5. Table 5-28 12-Bit ADC, Dynamic Performance With Internal Reference
        6. Table 5-29 12-Bit ADC, Temperature Sensor and Built-In V1/2
        7. Table 5-30 12-Bit ADC, External Reference
      11. 5.13.11 Reference
        1. Table 5-31 REF, Built-In Reference
      12. 5.13.12 Comparator
        1. Table 5-32 Comparator_E
      13. 5.13.13 FRAM
        1. Table 5-33 FRAM
      14. 5.13.14 USS
        1. Table 5-34 USS Recommended Operating Conditions
        2. Table 5-35 USS LDO
        3. Table 5-36 USSXTAL
        4. Table 5-37 USS HSPLL
        5. Table 5-38 USS SDHS
        6. Table 5-39 USS PHY Output Stage
        7. Table 5-40 USS PHY Input Stage, Multiplexer
        8. Table 5-41 USS PGA
        9. Table 5-42 USS Bias Voltage Generator
      15. 5.13.15 Emulation and Debug
        1. Table 5-43 JTAG and Spy-Bi-Wire Interface
  6. 6Detailed Description
    1. 6.1  Overview
    2. 6.2  CPU
    3. 6.3  Ultrasonic Sensing Solution (USS) Module
    4. 6.4  Low-Energy Accelerator (LEA) for Signal Processing
    5. 6.5  Operating Modes
      1. 6.5.1 Peripherals in Low-Power Modes
      2. 6.5.2 Idle Currents of Peripherals in LPM3 and LPM4
    6. 6.6  Interrupt Vector Table and Signatures
    7. 6.7  Bootloader (BSL)
    8. 6.8  JTAG Operation
      1. 6.8.1 JTAG Standard Interface
      2. 6.8.2 Spy-Bi-Wire (SBW) Interface
    9. 6.9  FRAM Controller A (FRCTL_A)
    10. 6.10 RAM
    11. 6.11 Tiny RAM
    12. 6.12 Memory Protection Unit (MPU) Including IP Encapsulation
    13. 6.13 Peripherals
      1. 6.13.1  Digital I/O
      2. 6.13.2  Oscillator and Clock System (CS)
      3. 6.13.3  Power-Management Module (PMM)
      4. 6.13.4  Hardware Multiplier (MPY)
      5. 6.13.5  Real-Time Clock (RTC_C)
      6. 6.13.6  Measurement Test Interface (MTIF)
      7. 6.13.7  Watchdog Timer (WDT_A)
      8. 6.13.8  System Module (SYS)
      9. 6.13.9  DMA Controller
      10. 6.13.10 Enhanced Universal Serial Communication Interface (eUSCI)
      11. 6.13.11 TA0, TA1, and TA4
      12. 6.13.12 TA2 and TA3
      13. 6.13.13 TB0
      14. 6.13.14 ADC12_B
      15. 6.13.15 USS
      16. 6.13.16 Comparator_E
      17. 6.13.17 CRC16
      18. 6.13.18 CRC32
      19. 6.13.19 AES256 Accelerator
      20. 6.13.20 True Random Seed
      21. 6.13.21 Shared Reference (REF)
      22. 6.13.22 LCD_C
      23. 6.13.23 Embedded Emulation
        1. 6.13.23.1 Embedded Emulation Module (EEM) (S Version)
        2. 6.13.23.2 EnergyTrace++ Technology
    14. 6.14 Input/Output Diagrams
      1. 6.14.1  Port Function Select Registers (PySEL1 , PySEL0)
      2. 6.14.2  Port P1 (P1.0 and P1.1) Input/Output With Schmitt Trigger
      3. 6.14.3  Port P1 (P1.2 to P1.7) Input/Output With Schmitt Trigger
      4. 6.14.4  Port P2 (P2.0 to P2.3) Input/Output With Schmitt Trigger
      5. 6.14.5  Port P2 (P2.4 to P2.7) Input/Output With Schmitt Trigger
      6. 6.14.6  Port P3 (P3.0 to P3.7) Input/Output With Schmitt Trigger
      7. 6.14.7  Port P4 (P4.0 to P4.7) Input/Output With Schmitt Trigger
      8. 6.14.8  Port P5 (P5.0 to P5.7) Input/Output With Schmitt Trigger
      9. 6.14.9  Port P6 (P6.0) Input/Output With Schmitt Trigger
      10. 6.14.10 Port P6 (P6.1 to P6.5) Input/Output With Schmitt Trigger
      11. 6.14.11 Port P6 (P6.6 and P6.7) Input/Output With Schmitt Trigger
      12. 6.14.12 Port P7 (P7.0 to P7.3) Input/Output With Schmitt Trigger
      13. 6.14.13 Port P7 (P7.4) Input/Output With Schmitt Trigger
      14. 6.14.14 Port P7 (P7.5) Input/Output With Schmitt Trigger
      15. 6.14.15 Port P7 (P7.6 and P7.7) Input/Output With Schmitt Trigger
      16. 6.14.16 Port P8 (P8.0 to P8.3) Input/Output With Schmitt Trigger
      17. 6.14.17 Port P8 (P8.4 to P8.7) Input/Output With Schmitt Trigger
      18. 6.14.18 Port P9 (P9.0 to P9.3) Input/Output With Schmitt Trigger
      19. 6.14.19 Port PJ (PJ.0 to PJ.3) JTAG Pins TDO, TMS, TCK, TDI/TCLK, Input/Output With Schmitt Trigger
      20. 6.14.20 Port PJ (PJ.4 and PJ.5) Input/Output With Schmitt Trigger
      21. 6.14.21 Port PJ (PJ.6 and PJ.7) Input/Output With Schmitt Trigger
    15. 6.15 Device Descriptors (TLV)
    16. 6.16 Memory Map
      1. 6.16.1 Peripheral File Map
    17. 6.17 Identification
      1. 6.17.1 Revision Identification
      2. 6.17.2 Device Identification
      3. 6.17.3 JTAG Identification
  7. 7Applications, Implementation, and Layout
    1. 7.1 Device Connection and Layout Fundamentals
      1. 7.1.1  Power Supply Decoupling and Bulk Capacitors
      2. 7.1.2  External Oscillator (HFXT and LFXT)
      3. 7.1.3  USS Oscillator (USSXT)
      4. 7.1.4  Transducer Connection to the USS Module
      5. 7.1.5  Charge Pump Control of Input Multiplexer
      6. 7.1.6  JTAG
      7. 7.1.7  Reset
      8. 7.1.8  Unused Pins
      9. 7.1.9  General Layout Recommendations
      10. 7.1.10 Do's and Don'ts
    2. 7.2 Peripheral- and Interface-Specific Design Information
      1. 7.2.1 ADC12_B Peripheral
        1. 7.2.1.1 Partial Schematic
        2. 7.2.1.2 Design Requirements
        3. 7.2.1.3 Detailed Design Procedure
        4. 7.2.1.4 Layout Guidelines
      2. 7.2.2 LCD_C Peripheral
        1. 7.2.2.1 Partial Schematic
        2. 7.2.2.2 Design Requirements
        3. 7.2.2.3 Detailed Design Procedure
        4. 7.2.2.4 Layout Guidelines
  8. 8器件和文档支持
    1. 8.1 入门和下一步
    2. 8.2 器件命名规则
    3. 8.3 工具和软件
    4. 8.4 文档支持
    5. 8.5 相关链接
    6. 8.6 商标
    7. 8.7 静电放电警告
    8. 8.8 Export Control Notice
    9. 8.9 Glossary
  9. 9机械、封装和可订购信息
  10. 重要声明
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DATA SHEET

用于水计量应用的 MSP430FR604x(1)、MSP430FR603x(1)、超声波感应 MSP430™ 微控制器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 器件概述

1.1 特性

  • 具有超低功耗的一流超声波水流量测量
    • 差分飞行时间 (dTOF) 精度小于 25ps
    • 高精度时间测量分辨率小于 5ps
    • 能够检测低流速（<1 升/小时）
    • 在每秒测量一次的频率下总体电流消耗大约为 3µA
  • 符合并超出 ISO 4064、OIML R49 和 EN 1434 精度标准
  • 能够直接与标准超声波传感器（高达 2.5MHz）连接
  • 集成模拟前端 – 超声波感应解决方案 (USS)
    • 可在不同频率下生成脉冲的可编程脉冲生成 (PPG)
    • 具有低阻抗 (4Ω) 输出驱动器的集成物理接口 (PHY)，可控制输入和输出通道
    • 具有高达 8Msps 输出数据速率的高性能高速 12 位 Σ-Δ ADC (SDHS)
    • 具有 –6.5dB 至 30.8dB 增益的可编程增益放大器 (PGA)
    • 输出范围为 68MHz 至 80MHz 的高性能锁相环 (PLL)
  • 计量测试接口 (MTIF)
    • 脉冲发生器和脉冲计数器
    • 高达 1016 次脉冲/秒 (p/s) 的脉冲率
    • 计数容量高达 65535（16 位）
    • 在 LPM3.5 下以 200nA（典型值）运行
  • 低能耗加速器 (LEA)
    • 独立于 CPU 运行
    • 与 CPU 共享 4KB RAM
    • 256 点高效复变 FFT：
      比 Arm®Cortex®-M0+ 内核快多达 40 倍
  • 嵌入式微控制器
    • 高达 16MHz 时钟频率的 16 位 RISC 架构
    • 3.6V 至 1.8V 的宽电源电压范围（最低电源电压受限于 SVS 电平，请参阅 SVS 规格）
  • 经优化的超低功耗模式
    • 工作模式：大约 120µA/MHz
    • 待机模式下的实时时钟 (RTC) (LPM3.5)：450nA (1)
    • 关断电流 (LPM4.5)：30nA
      • 1. RTC 由 3.7pF 晶振生成。
  • 铁电随机存取存储器 (FRAM)
    • 高达 256KB 的非易失性存储器
    • 超低功耗写入
    • 125ns 每个字的快速写入（4ms 内写入 64KB）
    • 统一标准存储器 = 单个空间内的程序 + 数据 + 存储
    • 1015 写入周期持久性
    • 抗辐射和非磁性
  • 智能数字外设
    • 32 位硬件乘法器 (MPY)
    • 6 通道内部直接存储器访问 (DMA)
    • 具备日历和报警功能的 RTC
    • 六个 16 位定时器，每个定时器具有多达七个捕捉/比较寄存器
    • 32 位和 16 位循环冗余校验 (CRC)
  • 高性能模拟
    • 16 通道模拟比较器
    • 12 位 SAR ADC，具有窗口比较器、内部基准和采样保持功能以及多达 16 条外部输入通道
    • 具有高达 264 段对比度控制的集成 LCD 驱动器
  • 多功能输入/输出端口
    • 可每位、每字节和每字访问（成对访问）
    • 所有端口上，从 LPM 中的边沿可选唤醒
    • 所有端口上可编程上拉和下拉
  • 代码安全性和加密
    • 128 位或 256 位高级加密标准 (AES) 安全加密和解密协处理器
    • 针对随机数生成算法的随机数种子
    • IP 封装防止对存储器进行外部访问
    • FRAM 可提供固有安全性优势
  • 增强型串行通信
    • 多达四个 eUSCI_A 串行通信端口
      • 支持自动波特率侦测的通用异步收发器 (UART)
      • IrDA 编码和解码
    • 多达两个 eUSCI_B 串行通信端口
      • 支持多从设备寻址的 I2C
    • 硬件通用异步收发器 (UART) 或 I2C 自举程序 (BSL)
  • 灵活时钟系统
    • 具有 10 个可选厂家调整频率的定频数控振荡器 (DCO)
    • 低功率低频内部时钟源 (VLO)
    • 32kHz 晶振 (LFXT)
    • 高频晶振 (HFXT)
  • 开发工具和软件（另请参阅工具和软件）
    • 超声波感应设计中心图形用户界面
    • 超声波感应软件库
    • EVM430-FR6047 水表评估模块板
    • 用于 100 引脚封装的 MSP-TS430PZ100E 目标插座板
    • 采用 EnergyTrace++ 技术的免费专业开发环境
    • 用于 MSP430™ 微控制器的 MSP430Ware™
  • 器件比较 汇总了可用的器件型号和封装选项
  • 要获得完整的模块说明，请参见《MSP430FR58xx、MSP430FR59xx 和 MSP430FR6xx 系列用户指南》

1.2 应用

  • 超声波智能水表
  • 超声波智能热量计
  • 液位感应
  • 漏水检测

1.3 说明

德州仪器 (TI) MSP430FR604x 和 MSP430FR603x 系列超声波感应和测量 SoC 是针对水表和热量计进行了优化的强大且高度集成的微控制器 (MCU)。MSP430FR604x MCU 具有集成的超声波感应解决方案 (USS) 模块，该模块可在多种流速条件下提供高精度。USS 模块高度集成，需要的外部组件极少，因而有助于实现超低功耗计量并降低系统成本。MSP430FR604x 和 MSP430FR603x MCU 采用集成式低功耗加速器 (LEA)，可实现基于高速 ADC 的信号采集以及后续优化数字信号处理，为电池供电型计量应用提供了一款理想的超低功耗、高精度计量 解决方案。

USS 模块包括可编程脉冲发生器 (PPG) 和具有低阻抗输出驱动器的物理接口 (PHY)，以实现最佳传感器激励和准确的阻抗匹配，从而在零流量漂移 (ZFD) 方面达到最佳效果。该模块还包含可编程增益放大器 (PGA) 和高速 12 位 8Msps Σ-Δ ADC (SDHS)，便于通过行业标准超声波传感器实现精确的信号采集。

此外，MSP430FR604x 和 MSP430FR603x MCU 还集成了其他外设，可提高系统在计量方面的集成度。这些器件还具有计量测试接口 (MTIF) 模块，能够通过脉冲生成来指示仪表测量的流量。MSP430FR604x 和 MSP430FR603x MCU 还具有片上 8 通道多路复用器 LCD 驱动器、RTC、12 位 SAR ADC、模拟比较器、高级加密加速器 (AES256) 和循环冗余校验 (CRC) 模块。

MSP430FR604x 和 MSP430FR603x MCU 由一款广泛的硬件和软件生态系统提供支持，随附参考设计和代码示例，以便用户快速开展设计。开发套件包括 MSP-TS430PZ100E 100 引脚目标开发板和 EVM430-FR6047 超声波水流量计 EVM。TI 还提供免费软件，包括超声波感应设计中心、超声波感应软件库和 MSP430Ware™ 软件。

TI 的 MSP430 超低功耗 (ULP) FRAM 微控制器平台将独特的嵌入式 FRAM 和全面的超低功耗系统架构相结合，从而使系统设计人员能够在降低能耗的同时提升性能。FRAM 技术将 RAM 的低能耗快速写入、灵活性和耐用性与闪存的非易失性相结合。

器件信息(1)(2)

器件型号 封装 封装尺寸(3)
MSP430FR6047IPZ
MSP430FR60471IPZ
MSP430FR6045IPZ
MSP430FR6037IPZ
MSP430FR60371IPZ
MSP430FR6035IPZ		 LQFP (100) 14mm x 14mm
(1) 要获得所有可用器件的最新部件、封装和订购信息，请参见封装选项附录（Section 9）或浏览 TI 网站 www.ti.com。
(2) 有关提供的所有器件变型的对比，请参见Section 3。
(3) 这里显示的尺寸为近似值。要获得包含误差值的封装尺寸，请参见机械数据（Section 9）。

1.4 功能框图

Figure 1-1 和 Figure 1-2 显示了器件的功能框图。

MSP430FR6047 MSP430FR60471 MSP430FR6045 MSP430FR6037 MSP430FR60371 MSP430FR6035 msp430fr6047-functional-block-diagram.gif

NOTE:

该器件具备 8KB RAM，其中 4KB RAM 与 LEA 子系统共享。
Figure 1-1 MSP430FR604x 功能框图
MSP430FR6047 MSP430FR60471 MSP430FR6045 MSP430FR6037 MSP430FR60371 MSP430FR6035 bd_FR603xNoPo.gif

NOTE:

该器件具备 8KB RAM，其中 4KB RAM 与 LEA 子系统共享。
Figure 1-2 MSP430FR603x 功能框图

2 修订历史记录

Changes from December 16, 2017 to September 25, 2018

  • Updated Section 3.1, Related ProductsGo
  • Added note (1) to Table 5-2, SVSGo
  • Changed capacitor value from 4.7 µF to 470 nF in Figure 7-10, ADC12_B Grounding and Noise ConsiderationsGo
  • Changed capacitor value from 4.7 µF to 470 nF in the last paragraph of Section 7.2.1.2, Design RequirementsGo
  • 更新了Section 8.2器件命名规则 中的文本和图Go

3 Device Comparison

Table 3-1 summarizes the available family members.

Table 3-1 Device Comparison(7)(8)

DEVICE FRAM
(KB)		 SRAM
(KB)		 CLOCK SYSTEM LEA USS
USSXT		 MTIF ADC12_B Comp_E Timer_A(1) Timer_B(2) eUSCI AES BSL I/Os PACKAGE
A(3) B(4)
MSP430FR6047 256 8 DCO
HFXT
LFXT 		Yes Yes Yes 16 ext, 2 int ch. 16 ch. 3, 3(5)
2, 2,2(6) 		7 4 2 Yes UART 76 100 PZ (LQFP)
MSP430FR60471 256 8 DCO
HFXT
LFXT 		Yes Yes Yes 16 ext, 2 int ch. 16 ch. 3, 3(5)
2, 2,2(6) 		7 4 2 Yes I2C 76 100 PZ (LQFP)
MSP430FR6037 256 8 DCO
HFXT
LFXT 		Yes No Yes 16 ext, 2 int ch. 16 ch. 3, 3(5)
2, 2,2(6) 		7 4 2 Yes UART 76 100 PZ (LQFP)
MSP430FR60371 256 8 DCO
HFXT
LFXT 		Yes No Yes 16 ext, 2 int ch. 16 ch. 3, 3(5)
2, 2,2(6) 		7 4 2 Yes I2C 76 100 PZ (LQFP)
MSP430FR6045 128 8 DCO
HFXT
LFXT 		Yes Yes Yes 16 ext, 2 int ch. 16 ch. 3, 3(5)
2, 2,2(6) 		7 4 2 Yes UART 76 100 PZ (LQFP)
MSP430FR6035 128 8 DCO
HFXT
LFXT 		Yes No Yes 16 ext, 2 int ch. 16 ch. 3, 3(5)
2, 2,2(6) 		7 4 2 Yes UART 76 100 PZ (LQFP)
(1) Each number in the sequence represents an instantiation of Timer_A with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_A, the first instantiation having three capture/compare registers and PWM output generators and the second instantiation having five capture/compare registers and PWM output generators, respectively.
(2) Each number in the sequence represents an instantiation of Timer_B with its associated number of capture/compare registers and PWM output generators available. For example, a number sequence of 3, 5 would represent two instantiations of Timer_B, the first instantiation having three capture/compare registers and PWM output generators and the second instantiation having five capture/compare registers and PWM output generators, respectively.
(3) eUSCI_A supports UART with automatic baud-rate detection, IrDA encode and decode, and SPI.
(4) eUSCI_B supports I2C with multiple slave addresses and SPI.
(5) Timers TA0 and TA1 provide internal and external capture/compare inputs and internal and external PWM outputs.
(6) Timers TA2 and TA3 provide only internal capture/compare inputs and only internal PWM outputs (if any) whereas Timer TA4 provides internal, external capture/compare inputs and internal, external PWM outputs.
(7) For the most current package and ordering information, see the Package Option Addendum in Section 9, or see the TI website at www.ti.com.
(8) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at www.ti.com/packaging.

3.1 Related Products

For information about other devices in this family of products or related products, see the following links.

    TI 16-bit and 32-bit microcontrollers

    High-performance, low-power solutions to enable the autonomous future

    Products for MSP430 ultra-low-power sensing and measurement microcontrollers

    One platform. One ecosystem. Endless possibilities.

    Products for MSP430 ultrasonic and performance sensing microcontrollers

    Ultra-low-power single-chip MCUs with integrated sensing peripherals

    Companion products for MSP430FR6047

    Review products that are frequently purchased or used with this product.

    Reference designs for MSP430FR6047

    The TI Designs Reference Design Library is a robust reference design library that spans analog, embedded processor, and connectivity. Created by TI experts to help you jump start your system design, all TI Designs include schematic or block diagrams, BOMs, and design files to speed your time to market. Search and download designs at ti.com/tidesigns.

4 Terminal Configuration and Functions

4.1 Pin Diagram

Figure 4-1 and Figure 4-2 show the pinouts of the 100-pin PZ packages.

MSP430FR6047 MSP430FR60471 MSP430FR6045 MSP430FR6037 MSP430FR60371 MSP430FR6035 MSP430FR604x_100LQFP_2.gif
On devices with UART BSL: P2.0 is BSLTX, P2.1 is BSLRX
On devices with I2C BSL: P1.6 is BSLSDA, P1.7 is BSLSCL
Figure 4-1 MSP430FR604x 100-Pin PZ Package (Top View)
MSP430FR6047 MSP430FR60471 MSP430FR6045 MSP430FR6037 MSP430FR60371 MSP430FR6035 MSP430FR603x_100LQFP_2.gif
On devices with UART BSL: P2.0 is BSLTX, P2.1 is BSLRX
On devices with I2C BSL: P1.6 is BSLSDA, P1.7 is BSLSCL
Figure 4-2 MSP430FR603x 100-Pin PZ Package (Top View)

4.2 Pin Attributes

Table 4-1 lists the attributes of each pin.

Table 4-1 Pin Attributes

PIN NUMBER SIGNAL NAME(1)(4) SIGNAL TYPE(2) BUFFER TYPE(3) POWER SOURCE(5) RESET STATE AFTER BOR(7)
1 P2.2 I/O LVCMOS DVCC OFF
COUT O LVCMOS DVCC –
UCA0CLK I/O LVCMOS DVCC –
A14 I Analog DVCC –
C14 I Analog DVCC –
2 P2.3 I/O LVCMOS DVCC OFF
TA0.0 I/O LVCMOS DVCC –
UCA0STE I/O LVCMOS DVCC –
A15 I Analog DVCC –
C15 I Analog DVCC –
3 P1.0 I/O LVCMOS DVCC OFF
UCA1CLK I/O LVCMOS DVCC –
TA1.0 I/O LVCMOS DVCC –
A0 I Analog DVCC –
C0 I Analog DVCC –
VREF- O Analog DVCC –
VeREF- I Analog DVCC –
4 P1.1 I/O LVCMOS DVCC OFF
UCA1STE I/O LVCMOS DVCC –
TA4.0 I/O LVCMOS DVCC –
A1 I Analog DVCC –
C1 I Analog DVCC –
VREF+ O Analog DVCC –
VeREF+ I Analog DVCC –
5 AVSS2 P Power – N/A
6 PJ.4 I/O LVCMOS DVCC OFF
LFXIN I Analog DVCC –
7 PJ.5 I/O LVCMOS DVCC OFF
LFXOUT O Analog DVCC –
8 AVSS3 P Power – N/A
9 PJ.6 I/O LVCMOS DVCC –
HFXIN I Analog DVCC –
10 PJ.7 I/O LVCMOS DVCC OFF
HFXOUT O Analog DVCC –
11 AVSS4 P Power – N/A
12 P1.4 I/O LVCMOS DVCC OFF
TB0.4 I/O LVCMOS DVCC –
UCB0STE I/O LVCMOS DVCC –
A2 I Analog DVCC –
C2 I Analog DVCC –
13 P1.5 I/O LVCMOS DVCC OFF
TB0.5 I/O LVCMOS DVCC –
UCB0CLK I/O LVCMOS DVCC –
A3 I Analog DVCC –
C3 I Analog DVCC –
14 P1.6 I/O LVCMOS DVCC OFF
UCB0SIMO I/O LVCMOS DVCC –
UCB0SDA I/O LVCMOS DVCC –
A4 I Analog DVCC –
C4 I Analog DVCC –
15 P1.7 I/O LVCMOS DVCC OFF
USSTRG I LVCMOS DVCC –
UCB0SOMI I/O LVCMOS DVCC –
UCB0SCL I/O LVCMOS DVCC –
A5 I Analog DVCC –
C5 I Analog DVCC –
16 P2.0 I/O LVCMOS DVCC OFF
UCA0TXD O LVCMOS DVCC –
UCA0SIMO I/O LVCMOS DVCC –
A6 I Analog DVCC –
C6 I Analog DVCC –
17 P2.1 I/O LVCMOS DVCC OFF
UCA0RXD I LVCMOS DVCC –
UCA0SOMI I/O LVCMOS DVCC –
A7 I Analog DVCC –
C7 I Analog DVCC –
18 P1.2 I/O LVCMOS DVCC OFF
UCA1TXD O LVCMOS DVCC –
UCA1SIMO I/O LVCMOS DVCC –
A8 I Analog DVCC –
C8 I Analog DVCC –
19 P1.3 I/O LVCMOS DVCC OFF
UCA1RXD I LVCMOS DVCC –
UCA1SOMI I/O LVCMOS DVCC –
A9 I Analog DVCC –
C9 I Analog DVCC –
20 TEST I LVCMOS DVCC PD
SBWTCK I LVCMOS DVCC –
21 RST I/O LVCMOS DVCC PU
NMI I LVCMOS DVCC –
SBWTDIO I/O LVCMOS DVCC –
22 PJ.0 I/O LVCMOS DVCC OFF
TDO O LVCMOS DVCC –
ACLK O LVCMOS DVCC –
SRSCG1 O LVCMOS DVCC –
DMAE0 I LVCMOS DVCC –
C10 I Analog DVCC –
23 PJ.1 I/O LVCMOS DVCC OFF
TDI I LVCMOS DVCC –
TCLK I LVCMOS DVCC –
SMCLK O LVCMOS DVCC –
SRSCG0 O LVCMOS DVCC –
TA4CLK I LVCMOS DVCC –
C11 I Analog DVCC –
24 PJ.2 I/O LVCMOS DVCC OFF
TMS I LVCMOS DVCC –
MCLK O LVCMOS DVCC –
SROSCOFF O LVCMOS DVCC –
TB0OUTH I LVCMOS DVCC –
C12 I Analog DVCC –
25 PJ.3 I/O LVCMOS DVCC OFF
TCK I LVCMOS DVCC –
RTCCLK O LVCMOS DVCC –
SRCPUOFF O LVCMOS DVCC –
TB0.6 I/O LVCMOS DVCC –
C13 I Analog DVCC –
26 DVSS1 P Power – N/A
27 DVCC1 P Power – N/A
28 P2.4 I/O LVCMOS DVCC OFF
TA0CLK I LVCMOS DVCC –
TB0CLK I LVCMOS DVCC –
TA1CLK I LVCMOS DVCC –
S32 O Analog DVCC –
29 P2.5 I/O LVCMOS DVCC OFF
TA4.0 I/O LVCMOS DVCC –
S31 O Analog DVCC –
30 P2.6 I/O LVCMOS DVCC OFF
TA4.1 I/O LVCMOS DVCC –
S30 O Analog DVCC –
31 P3.0 I/O LVCMOS DVCC OFF
TB0.0 I/O LVCMOS DVCC –
S29 O Analog DVCC –
32 P3.1 I/O LVCMOS DVCC OFF
TB0.1 O LVCMOS DVCC –
S28 O Analog DVCC –
33 P3.2 I/O LVCMOS DVCC OFF
TB0.2 O LVCMOS DVCC –
S27 O Analog DVCC –
34 P3.3 I/O LVCMOS DVCC OFF
TB0.3 I/O LVCMOS DVCC –
S26 O Analog DVCC –
35 P3.4 I/O LVCMOS DVCC OFF
TB0OUTH I LVCMOS DVCC –
S25 O Analog DVCC –
36 P3.5 I/O LVCMOS DVCC OFF
TB0.4 I/O LVCMOS DVCC –
S24 O Analog DVCC –
37 P3.6 I/O LVCMOS DVCC OFF
TB0.5 I/O LVCMOS DVCC –
S23 O Analog DVCC –
38 P3.7 I/O LVCMOS DVCC OFF
TB0.6 I/O LVCMOS DVCC –
S22 O Analog DVCC –
39 P2.7 I/O LVCMOS DVCC OFF
TA0.0 I/O LVCMOS DVCC –
S21 O Analog DVCC –
40 P9.0 I/O LVCMOS DVCC OFF
TA1.0 I/O LVCMOS DVCC –
S20 O Analog DVCC –
41 P9.1 I/O LVCMOS DVCC OFF
SMCLK O LVCMOS DVCC –
S19 O Analog DVCC –
42 P9.2 I/O LVCMOS DVCC OFF
MCLK O LVCMOS DVCC –
S18 O Analog DVCC –
43 P9.3 I/O LVCMOS DVCC OFF
ACLK O LVCMOS DVCC –
S17 O Analog DVCC –
44 P4.0 I/O LVCMOS DVCC OFF
RTCCLK O LVCMOS DVCC –
S16 O Analog DVCC –
45 P4.1 I/O LVCMOS DVCC OFF
UCA0CLK I/O LVCMOS DVCC –
S15 O Analog DVCC –
46 P4.2 I/O LVCMOS DVCC OFF
UCA0STE I/O LVCMOS DVCC –
S14 O Analog DVCC –
47 P4.3 I/O LVCMOS DVCC OFF
UCA0TXD O LVCMOS DVCC –
UCA0SIMO I/O LVCMOS DVCC –
S13 O Analog DVCC –
48 P4.4 I/O LVCMOS DVCC OFF
UCA0RXD I LVCMOS DVCC –
UCA0SOMI I/O LVCMOS DVCC –
S12 O Analog DVCC –
49 P4.5 I/O LVCMOS DVCC OFF
TA0CLK I LVCMOS DVCC –
TA1CLK I LVCMOS DVCC –
S11 O Analog DVCC –
50 P4.6 I/O LVCMOS DVCC OFF
TB0CLK I LVCMOS DVCC –
TA4CLK I LVCMOS DVCC –
S10 O Analog DVCC –
51 DVSS2 P Power – N/A
52 DVCC2 P Power – N/A
53 P4.7 I/O LVCMOS DVCC OFF
DMAE0 I LVCMOS DVCC –
S9 O Analog DVCC –
54 P5.0 I/O LVCMOS DVCC OFF
UCA2TXD O LVCMOS DVCC –
UCA2SIMO I/O LVCMOS DVCC –
S8 O Analog DVCC –
55 P5.1 I/O LVCMOS DVCC OFF
UCA2RXD I LVCMOS DVCC –
UCA2SOMI I/O LVCMOS DVCC –
S7 O Analog DVCC –
56 P5.2 I/O LVCMOS DVCC OFF
UCA2CLK I/O LVCMOS DVCC –
S6 O Analog DVCC –
57 P5.3 I/O LVCMOS DVCC OFF
UCA2STE I/O LVCMOS DVCC –
S5 O Analog DVCC –
58 P5.4 I/O LVCMOS DVCC OFF
UCB1CLK I/O LVCMOS DVCC –
S4 O Analog DVCC –
59 P5.5 I/O LVCMOS DVCC OFF
TA0CLK I LVCMOS DVCC –
UCB1SIMO I/O LVCMOS DVCC –
UCB1SDA I/O LVCMOS DVCC –
S3 O Analog DVCC –
60 P5.6 I/O LVCMOS DVCC OFF
UCB1SOMI I/O LVCMOS DVCC –
UCB1SCL I/O LVCMOS DVCC –
S2 O Analog DVCC –
61 P5.7 I/O LVCMOS DVCC OFF
UCB1STE I/O LVCMOS DVCC –
S1 O Analog DVCC –
62 P6.0 I/O LVCMOS DVCC OFF
COUT I LVCMOS DVCC –
S0 O Analog DVCC –
63 P6.4 I/O LVCMOS DVCC OFF
COM0 O Analog DVCC –
64 P6.5 I/O LVCMOS DVCC OFF
COM1 O Analog DVCC –
65 P6.6 I/O LVCMOS DVCC OFF
COM2 O Analog DVCC –
S38 O Analog DVCC –
66 P6.7 I/O LVCMOS DVCC OFF
COM3 O Analog DVCC –
S37 O Analog DVCC –
67 P7.0 I/O LVCMOS DVCC OFF
UCA2TXD O LVCMOS DVCC –
UCA2SIMO I/O LVCMOS DVCC –
ACLK O LVCMOS DVCC –
COM4 O Analog DVCC –
S36 O Analog DVCC –
68 P7.1 I/O LVCMOS DVCC OFF
UCA2RXD I LVCMOS DVCC –
UCA2SOMI I/O LVCMOS DVCC –
SMCLK O LVCMOS DVCC –
COM5 O Analog DVCC –
S35 O Analog DVCC –
69 P7.2 I/O LVCMOS DVCC OFF
UCA2CLK I/O LVCMOS DVCC –
TB0.0 I/O LVCMOS DVCC –
COM6 O Analog DVCC –
S34 O Analog DVCC –
70 P7.3 I/O LVCMOS DVCC OFF
UCA2STE I/O LVCMOS DVCC –
TB0.1 I/O LVCMOS DVCC –
COM7 O Analog DVCC –
S33 O Analog DVCC –
71 P6.1 I/O LVCMOS DVCC OFF
R03 I/O Analog DVCC –
72 P6.2 I/O LVCMOS DVCC OFF
R13 I/O Analog DVCC –
LCDREF I Analog - –
73 P6.3 I/O LVCMOS DVCC OFF
R23 I/O Analog DVCC –
74 R33 I/O Analog DVCC -
LCDCAP I/O Analog DVCC –
75 DVSS3 P Power – N/A
76 DVCC3 P Power – N/A
77 P7.4 I/O LVCMOS DVCC OFF
TA0.1 I/O LVCMOS DVCC –
MTIF_OUT_IN I/O LVCMOS DVCC –
78 P7.5 I/O LVCMOS DVCC OFF
TA1.1 I/O LVCMOS DVCC –
MTIF_PIN_EN I LVCMOS DVCC –
79 P8.0 I/O LVCMOS DVCC OFF
UCA3STE I/O LVCMOS DVCC –
TB0.2 I/O LVCMOS DVCC –
DMAE0 I LVCMOS DVCC –
80 P8.1 I/O LVCMOS DVCC OFF
UCA3CLK I/O LVCMOS DVCC –
TB0.3 I/O LVCMOS DVCC –
TB0OUTH I LVCMOS DVCC –
81 P8.2 I/O LVCMOS DVCC OFF
UCA3RXD O LVCMOS DVCC –
UCA3SOMI I/O LVCMOS DVCC –
MCLK O LVCMOS DVCC –
82 P8.3 I/O LVCMOS DVCC OFF
UCA3TXD O LVCMOS DVCC –
UCA3SIMO I/O LVCMOS DVCC –
RTCCLK O LVCMOS DVCC –
83 P7.6 I/O LVCMOS DVCC OFF
TA4.1 I/O LVCMOS DVCC –
DMAE0 I LVCMOS DVCC –
COUT O LVCMOS DVCC –
84 P7.7 I/O LVCMOS DVCC OFF
TA0.2 I/O LVCMOS DVCC –
TB0OUTH I LVCMOS DVCC –
COUT O LVCMOS DVCC –
85 CH1_IN I Analog PVCC –
86 CH1_OUT O Analog PVCC –
87 PVSS P Power – N/A
88 PVCC P Power – N/A
89 PVSS P Power – N/A
90 CH0_OUT O Analog PVCC –
91 CH0_IN I Analog PVCC –
92 P8.4 I/O LVCMOS DVCC OFF
UCB1CLK I/O LVCMOS DVCC –
TA1.2 I/O LVCMOS DVCC –
A10 I Analog DVCC –
93 P8.5 I/O LVCMOS DVCC OFF
UCB1SIMO I/O LVCMOS DVCC –
UCB1SDA I/O LVCMOS DVCC –
A11 I Analog DVCC –
94 P8.6 I/O LVCMOS DVCC OFF
UCB1SOMI I/O LVCMOS DVCC –
UCB1SCL I/O LVCMOS DVCC –
A12 I Analog DVCC –
95 P8.7 I/O LVCMOS DVCC OFF
UCB1STE I/O LVCMOS DVCC –
USSXT_BOUT I/O LVCMOS DVCC –
A13 I Analog DVCC –
96 AVSS5 P Power – N/A
97 USSXTIN(6) I Analog 1.5V –
98 USSXTOUT(6) O Analog 1.5V –
99 AVSS1 P Power – N/A
100 AVCC1 P Power – N/A
(1) The signal that is listed first for each pin is the reset default pin name.
(2) Signal Types: I = Input, O = Output, I/O = Input or Output.
(3) Buffer Types: LVCMOS, Analog, or Power (see Table 4-3 for details)
(4) To determine the pin mux encodings for each pin, see Section 6.14.
(5) The power source shown in this table is the I/O power source, which may differ from the module power source.
(6) Do not connect USSXTIN and USSXTOUT pins to AVCC nor to DVCC. USSXTIN does not support bypass mode, so do not drive an external clock on the USSXTIN pin.
(7) Reset States:
OFF = High impedance with Schmitt-trigger input and pullup or pulldown (if available) disabled
PU = Pullup is enabled
PD = Pulldown is enabled
N/A = Not applicable

4.3 Signal Descriptions

Table 4-2 describes the signals.

Table 4-2 Signal Descriptions

FUNCTION SIGNAL NAME PIN NO. PIN TYPE(1) DESCRIPTION
PZ
ADC A0 3 I ADC analog input A0
A1 4 I ADC analog input A1
A2 12 I ADC analog input A2
A3 13 I ADC analog input A3
A4 14 I ADC analog input A4
A5 15 I ADC analog input A5
A6 16 I ADC analog input A6
A7 17 I ADC analog input A7
A8 18 I ADC analog input A8
A9 19 I ADC analog input A9
A10 92 I ADC analog input A10
A11 93 I ADC analog input A11
A12 94 I ADC analog input A12
A13 95 I ADC analog input A13
A14 1 I ADC analog input A14
A15 2 I ADC analog input A15
VREF+ 4 O Output of positive reference voltage
VREF- 3 O Output of negative reference voltage
VeREF+ 4 I Input for an external positive reference voltage to the ADC
VeREF- 3 I Input for an external negative reference voltage to the ADC
Clock ACLK 22, 43, 67 O ACLK output
HFXIN 9 I Input for high-frequency crystal oscillator HFXT
HFXOUT 10 O Output for high-frequency crystal oscillator HFXT
LFXIN 6 I Input for low-frequency crystal oscillator LFXT
LFXOUT 7 O Output of low-frequency crystal oscillator LFXT
MCLK 24, 42, 81 O MCLK output
SMCLK 23, 41, 68 O SMCLK output
Comparator C0 3 I Comparator input C0
C1 4 I Comparator input C1
C2 12 I Comparator input C2
C3 13 I Comparator input C3
C4 14 I Comparator input C4
C5 15 I Comparator input C5
C6 16 I Comparator input C6
C7 17 I Comparator input C7
C8 18 I Comparator input C8
C9 19 I Comparator input C9
C10 22 I Comparator input C10
C11 23 I Comparator input C11
C12 24 I Comparator input C12
C13 25 I Comparator input C13
C14 1 I Comparator input C14
C15 2 I Comparator input C15
COUT 1, 83, 84 O Comparator output
DMA DMAE0 22, 79, 83 I External DMA trigger
Debug SBWTCK 20 I Spy-Bi-Wire input clock
SBWTDIO 21 I/O Spy-Bi-Wire data input/output
SRCPUOFF 25 O Low-power debug: CPU Status register bit CPUOFF
SROSCOFF 24 O Low-power debug: CPU Status register bit OSCOFF
SRSCG0 23 O Low-power debug: CPU Status register bit SCG0
SRSCG1 22 O Low-power debug: CPU Status register bit SCG1
TCK 25 I Test clock
TCLK 23 I Test clock input
TDI 23 I Test data input
TDO 22 O Test data output port
TEST 20 I Test mode pin, selects digital I/O on JTAG pins
TMS 24 I Test mode select
GPIO Port 1 P1.0 3 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.1 4 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.2 18 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.3 19 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.4 12 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.5 13 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.6 14 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P1.7 15 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO Port 2 P2.0 16 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.1 17 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.2 1 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.3 2 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.4 28 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.5 29 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.6 30 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P2.7 39 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO Port 3 P3.0 31 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.1 32 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.2 33 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.3 34 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.4 35 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.5 36 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.6 37 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P3.7 38 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO Port 4 P4.0 44 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.1 45 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.2 46 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.3 47 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.4 48 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.5 49 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.6 50 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P4.7 53 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO Port 5 P5.0 54 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P5.1 55 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P5.2 56 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P5.3 57 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P5.4 58 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P5.5 59 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P5.6 60 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P5.7 61 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO Port 6 P6.0 62 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P6.1 71 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P6.2 72 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P6.3 73 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P6.4 63 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P6.5 64 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P6.6 65 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P6.7 66 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO Port 7 P7.0 67 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P7.1 68 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P7.2 69 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P7.3 70 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P7.4 77 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P7.5 78 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P7.6 83 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P7.7 84 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO Port 8 P8.0 79 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P8.1 80 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P8.2 81 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P8.3 82 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P8.4 92 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P8.5 93 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P8.6 94 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P8.7 95 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO Port 9 P9.0 40 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P9.1 41 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P9.2 42 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
P9.3 43 I/O General-purpose digital I/O with port interrupt and wakeup from LPMx.5
GPIO Port J PJ.0 22 I/O General-purpose digital I/O
PJ.1 23 I/O General-purpose digital I/O
PJ.2 24 I/O General-purpose digital I/O
PJ.3 25 I/O General-purpose digital I/O
PJ.4 6 I/O General-purpose digital I/O
PJ.5 7 I/O General-purpose digital I/O
PJ.6 9 I/O General-purpose digital I/O
PJ.7 10 I/O General-purpose digital I/O
I2C UCB0SCL 15 I/O I2C clock for eUSCI_B0 I2C mode
UCB0SDA 14 I/O I2C data for eUSCI_B0 I2C mode
UCB1SCL 94, 60 I/O I2C clock for eUSCI_B1 I2C mode
UCB1SDA 93, 59 I/O I2C data for eUSCI_B1 I2C mode
LCD COM0 63 O LCD common output COM0 for LCD backplane
COM1 64 O LCD common output COM1 for LCD backplane
COM2 65 O LCD common output COM2 for LCD backplane
COM3 66 O LCD common output COM3 for LCD backplane
COM4 67 O LCD common output COM4 for LCD backplane
COM5 68 O LCD common output COM5 for LCD backplane
COM6 69 O LCD common output COM6 for LCD backplane
COM7 70 O LCD common output COM7 for LCD backplane
LCDCAP 74 I/O LCD capacitor connection
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
LCDREF 72 I External reference voltage input for regulated LCD voltage
R03 71 I/O Input/output port of lowest analog LCD voltage (V5)
R13 72 I/O Input/output port of third most positive analog LCD voltage (V3 or V4)
R23 73 I/O Input/output port of second most positive analog LCD voltage (V2)
R33 74 I/O Input/output port of most positive analog LCD voltage (V1)
CAUTION: LCDCAP/R33 must be connected to DVSS if not used.
S0 62 O LCD segment output
S1 61 O LCD segment output
S2 60 O LCD segment output
S3 59 O LCD segment output
S4 58 O LCD segment output
S5 57 O LCD segment output
S6 56 O LCD segment output
S7 55 O LCD segment output
S8 54 O LCD segment output
S9 53 O LCD segment output
S10 50 O LCD segment output
S11 49 O LCD segment output
S12 48 O LCD segment output
S13 47 O LCD segment output
S14 46 O LCD segment output
S15 45 O LCD segment output
S16 44 O LCD segment output
S17 43 O LCD segment output
S18 42 O LCD segment output
S19 41 O LCD segment output
S20 40 O LCD segment output
S21 39 O LCD segment output
S22 38 O LCD segment output
S23 37 O LCD segment output
S24 36 O LCD segment output
S25 35 O LCD segment output
S26 34 O LCD segment output
S27 33 O LCD segment output
S28 32 O LCD segment output
S29 31 O LCD segment output
LCD (continued) S30 30 O LCD segment output
S31 29 O LCD segment output
S32 28 O LCD segment output
S33 70 O LCD segment output
S34 69 O LCD segment output
S35 68 O LCD segment output
S36 67 O LCD segment output
S37 66 O LCD segment output
S38 65 O LCD segment output
MTIF MTIF_PIN_EN 78 I Meter test interface pin enable
MTIF_OUT_IN 77 I/O Meter test interface input and output
Power AVCC1 100 P Analog power supply
AVSS1 99 P Analog ground supply
AVSS2 5 P Analog ground supply
AVSS3 8 P Analog ground supply
AVSS4 11 P Analog ground supply
AVSS5 96 P Analog ground supply
DVCC1 27 P Digital power supply
DVCC2 52 P Digital power supply
DVCC3 76 P Digital power supply
DVSS1 26 P Digital ground supply
DVSS2 51 P Digital ground supply
DVSS3 75 P Digital ground supply
PVCC 88 P USS power supply
PVSS 87, 89 P USS ground supply
RTC RTCCLK 25, 44, 82 O RTC clock calibration output
SPI UCA0CLK 1, 45 I/O Clock signal input for eUSCI_A0 SPI slave mode
Clock signal output for eUSCI_A0 SPI master mode
UCA0SIMO 16, 47 I/O Slave in/master out for eUSCI_A0 SPI mode
UCA0SOMI 17, 48 I/O Slave out/master in for eUSCI_A0 SPI mode
UCA0STE 2, 46 I/O Slave transmit enable for eUSCI_A0 SPI mode
UCA1CLK 3 I/O Clock signal input for eUSCI_A1 SPI slave mode
Clock signal output for eUSCI_A1 SPI master mode
UCA1SIMO 18 I/O Slave in/master out for eUSCI_A1 SPI mode
UCA1SOMI 19 I/O Slave out/master in for eUSCI_A1 SPI mode
UCA1STE 4 I/O Slave transmit enable for eUSCI_A1 SPI mode
UCA2CLK 69, 56 I/O Clock signal input for eUSCI_A2 SPI slave mode
Clock signal output for eUSCI_A2 SPI master mode
UCA2SIMO 67, 54 I/O Slave in/master out for eUSCI_A2 SPI mode
UCA2SOMI 68, 55 I/O Slave out/master in for eUSCI_A2 SPI mode
UCA2STE 70, 57 I/O Slave transmit enable for eUSCI_A2 SPI mode
UCA3CLK 80 I/O Clock signal input for eUSCI_A3 SPI slave mode
Clock signal output for eUSCI_A3 SPI master mode
UCA3SIMO 82 I/O Slave in/master out for eUSCI_A3 SPI mode
UCA3SOMI 81 I/O Slave out/master in for eUSCI_A3 SPI mode
UCA3STE 79 I/O Slave transmit enable for eUSCI_A3 SPI mode
UCB0CLK 13 I/O Clock signal input for eUSCI_B0 SPI slave mode
Clock signal output for eUSCI_B0 SPI master mode
UCB0SIMO 14 I/O Slave in/master out for eUSCI_B0 SPI mode
UCB0SOMI 15 I/O Slave out/master in for eUSCI_B0 SPI mode
UCB0STE 12 I/O Slave transmit enable for eUSCI_B0 SPI mode
UCB1CLK 92, 58 I/O Clock signal input for eUSCI_B1 SPI slave mode
Clock signal output for eUSCI_B1 SPI master mode
UCB1SIMO 93, 59 I/O Slave in/master out for eUSCI_B1 SPI mode
UCB1SOMI 94, 60 I/O Slave out/master in for eUSCI_B1 SPI mode
UCB1STE 95, 61 I/O Slave transmit enable for eUSCI_B1 SPI mode
System NMI 21 I Nonmaskable interrupt input
RST 21 I/O Reset input active low
Timer TA0.0 2 I/O TA0 CCR0 capture: CCI0A input, compare: Out0
TA0.0 39 I/O TA0 CCR0 capture: CCI0B input, compare: Out0
TA0.1 77 I/O TA0 CCR1 capture: CCI1A input, compare: Out1
TA0.2 84 I/O TA0 CCR2 capture: CCI2A input, compare: Out2
TA0CLK 28, 49, 59 I TA0 input clock
TA1.0 3 I/O TA1 CCR0 capture: CCI0A input, compare: Out0
TA1.0 40 I/O TA1 CCR0 capture: CCI0B input, compare: Out0
TA1.1 78 I/O TA1 CCR1 capture: CCI1A input, compare: Out1
TA1.2 92 I/O TA1 CCR2 capture: CCI2A input, compare: Out2
TA1CLK 28, 49 I TA1 input clock
TA4.0 4 I/O TA4 CCR0 capture: CCI0A input, compare: Out0
TA4.0 29 I/O TA4 CCR0 capture: CCI0B input, compare: Out0
TA4.1 30 I/O TA4CCR1 capture: CCI1B input, compare: Out1
TA4.1 83 I/O TA4 CCR1 capture: CCI1A input, compare: Out1
TA4CLK 23, 50 I TA4 input clock
TB0.0 31 I/O TB0 CCR0 capture: CCI0B input, compare: Out0
TB0.0 69 I/O TB0 CCR0 capture: CCI0A input, compare: Out0
TB0.1 32 I/O TB0 CCR1 capture: CCI1A input, compare: Out1
TB0.1 70 O TB0 CCR1 compare: Out1
TB0.2 33 I/O TB0 CCR2 capture: CCI2A input, compare: Out2
TB0.2 79 O TB0 CCR2 compare: Out2
TB0.3 34 I/O TB0 CCR3 capture: CCI3A input, compare: Out3
TB0.3 80 I/O TB0 CCR3 capture: CCI3B input, compare: Out3
TB0.4 12 I/O TB0 CCR4 capture: CCI4A input, compare: Out4
TB0.4 36 I/O TB0 CCR4 capture: CCI4B input, compare: Out4
TB0.5 13 I/O TB0 CCR5 capture: CCI5A input, compare: Out5
TB0.5 37 I/O TB0CCR5 capture: CCI5B input, compare: Out5
TB0.6 25 I/O TB0 CCR6 capture: CCI6B input, compare: Out6
TB0.6 38 I/O TB0 CCR6 capture: CCI6A input, compare: Out6
TB0CLK 28, 50 I TB0 clock input
TB0OUTH 24, 35, 80, 84 I Switch all PWM outputs high impedance input – TB0
UART UCA0RXD 17, 48 I Receive data for eUSCI_A0 UART mode
UCA0TXD 16, 47 O Transmit data for eUSCI_A0 UART mode
UCA1RXD 19 I Receive data for eUSCI_A1 UART mode
UCA1TXD 18 O Transmit data for eUSCI_A1 UART mode
UCA2RXD 68, 55 I Receive data for eUSCI_A2 UART mode
UCA2TXD 67, 54 O Transmit data for eUSCI_A2 UART mode
UCA3RXD 81 I Receive data for eUSCI_A3 UART mode
UCA3TXD 82 O Transmit data for eUSCI_A3 UART mode
USS USSTRG 15 I USS trigger
USSXTIN 97 I Input for crystal or resonator of oscillator USSXT
USSXTOUT 98 O Output for crystal or resonator of oscillator USSXT
USSXT_BOUT 95 O Buffered output clock of USSXT
CH0_IN 91 I USS channel 0 RX
CH0_OUT 90 I/O USS channel 0 TX
CH1_IN 85 I USS channel 1 RX
CH1_OUT 86 I/O USS channel 1 TX
(1) I = input, O = output, P = power

4.4 Pin Multiplexing

Pin multiplexing for these devices is controlled by both register settings and operating modes (for example, if the device is in test mode). For details of the settings for each pin and diagrams of the multiplexed ports, see Section 6.14.

4.5 Buffer Type

Table 4-3 describes the buffer types that are referenced in Table 4-1.

Table 4-3 Buffer Type

BUFFER TYPE (STANDARD) NOMINAL VOLTAGE HYSTERESIS PULLUP (PU)
OR
PULLDOWN (PD)		 NOMINAL PU OR PD STRENGTH (µA) OUTPUT DRIVE STRENGTH (mA) OTHER CHARACTERISTICS
Analog(2) 3.0 V N N/A N/A N/A See analog modules in Section 5 for details.
LVCMOS 3.0 V Y(1) Programmable See Section 5.13.5. See Section 5.13.5.
Power (DVCC)(3) 3.0 V N N/A N/A N/A SVS enables hysteresis on DVCC.
Power (AVCC)(3) 3.0 V N N/A N/A N/A
Power (PVCC)(3) 3.0 V N N/A N/A N/A
Power (DVSS and AVSS)(3) 0 V N N/A N/A N/A
(1) Only for input pins
(2) This is a switch, not a buffer.
(3) This is supply input, not a buffer.

4.6 Connection of Unused Pins

Table 4-4 lists the correct termination of unused pins.

Table 4-4 Connection of Unused Pins(1)

PIN POTENTIAL COMMENT
AVCC DVCC
PVCC DVCC
AVSS DVSS
PVSS DVSS
CHx_IN, CHx_OUT DVSS
USSXTIN DVSS Do not connect to DVCC, AVCC, or PVCC
USSXTOUT Open
Px.0 to Px.7 Open Switched to port function, output direction (PxDIR.n = 1)
RST/NMI/SBWTDIO DVCC or VCC 47-kΩ pullup or internal pullup selected with 10-nF (2.2-nF(2)) pulldown
PJ.0/TDO
PJ.1/TDI
PJ.2/TMS
PJ.3/TCK		 Open The JTAG pins are shared with general-purpose I/O function (PJ.x). If these pins are not used, set them to port function, output direction. If used as JTAG pins, leave them open.
TEST Open This pin always has an internal pulldown enabled.
(1) For any unused pin with a secondary function that is shared with general-purpose I/O, follow the guidelines for the Px.0 to Px.7 pins.
(2) The pulldown capacitor must not exceed 2.2 nF when using devices with Spy-Bi-Wire interface in Spy-Bi-Wire mode or in 4-wire JTAG mode with TI tools like FET interfaces or GANG programmers.

5 Specifications

5.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Supply voltage(3) At DVCC and AVCC pins –0.3 4.1 V
At DVCC, AVCC, and PVCC pins –0.3 4.1
Voltage difference between DVCC and AVCC pins(2) ±0.3 V
Voltage difference among DVCC, AVCC, and PVCC pins(2) ±0.3 V
VI Input voltage(3) Applied to CHx_IN –0.3 1.65 V
Applied to CHx_IN with a duty cycle of 10% over 1 ms –0.3 1.8
Applied to USSXTIN (USSXTOUT) –0.3 1.5
Applied to any other pin –0.3 VCC + 0.3 V
(4.1 V Max)
Diode current at any device pin ±2 mA
Tstg Storage temperature (4) –40 125 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) Voltage differences between DVCC and AVCC that exceed the specified limits can cause malfunction of the device including erroneous writes to RAM and FRAM.
(3) Voltages are referenced to VSS.
(4) Higher temperature may be applied during board soldering according to the current JEDEC J-STD-020 specification with peak reflow temperatures not higher than classified on the device label on the shipping boxes or reels.

 
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