ZHCSGM5A August 2017 – November 2017 TLV320AIC3109-Q1
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
Output Driver Power-On Delay Control | Driver Ramp-Up Step Timing Control | Weak Output Common-Mode Voltage Control | 0 | ||||
R/W-0h | R/W-0h | R/W-0h | R/W-0h |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7:4 | Output Driver Power-On Delay Control | R/W | 0h | Output driver power-on delay control. 0000: Driver power-on time = 0 μs 0001: Driver power-on time = 10 μs 0010: Driver power-on time = 100 μs 0011: Driver power-on time = 1 ms 0100: Driver power-on time = 10 ms 0101: Driver power-on time = 50 ms 0110: Driver power-on time = 100 ms 0111: Driver power-on time = 200 ms 1000: Driver power-on time = 400 ms 1001: Driver power-on time = 800 ms 1010: Driver power-on time = 2 s 1011: Driver power-on time = 4 s 1100–1111: Reserved; do not write these sequences to these register bits |
3:2 | Driver Ramp-Up Step Timing Control | R/W | 0h | Driver ramp-up step timing control. 00: Driver ramp-up step time = 0 ms 01: Driver ramp-up step time = 1 ms 10: Driver ramp-up step time = 2 ms 11: Driver ramp-up step time = 4 ms |
1 | Weak Output Common-Mode Voltage Control | R/W | 0h | Weak output common-mode voltage control. 0: Weakly driven output common-mode voltage is generated from resistor divider off the AVDD supply 1: Weakly driven output common-mode voltage is generated from band-gap reference |
0 | Reserved | R/W | 0h | Reserved. Always write zero to this bit. |