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  • 具有相位同步功能和 JESD204B 支持的 LMX2595 20GHz 宽带 PLLATINUM™ 射频合成器

    • ZHCSGL4C June   2017  – April 2019 LMX2595

      PRODUCTION DATA.  

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  • 具有相位同步功能和 JESD204B 支持的 LMX2595 20GHz 宽带 PLLATINUM™ 射频合成器
  1. 1 特性
  2. 2 应用
  3. 3 说明
    1.     Device Images
      1.      简化原理图
  4. 4 修订历史记录
  5. 5 Pin Configuration and Functions
    1.     Pin Functions
  6. 6 Specifications
    1. 6.1 Absolute Maximum Ratings
    2. 6.2 ESD Ratings
    3. 6.3 Recommended Operating Conditions
    4. 6.4 Thermal Information
    5. 6.5 Electrical Characteristics
    6. 6.6 Timing Requirements
    7. 6.7 Typical Characteristics
  7. 7 Detailed Description
    1. 7.1 Overview
    2. 7.2 Functional Block Diagram
    3. 7.3 Feature Description
      1. 7.3.1  Reference Oscillator Input
      2. 7.3.2  Reference Path
        1. 7.3.2.1 OSCin Doubler (OSC_2X)
        2. 7.3.2.2 Pre-R Divider (PLL_R_PRE)
        3. 7.3.2.3 Programmable Multiplier (MULT)
        4. 7.3.2.4 Post-R Divider (PLL_R)
        5. 7.3.2.5 State Machine Clock
      3. 7.3.3  PLL Phase Detector and Charge Pump
      4. 7.3.4  N-Divider and Fractional Circuitry
      5. 7.3.5  MUXout Pin
        1. 7.3.5.1 Lock Detect
        2. 7.3.5.2 Readback
      6. 7.3.6  VCO (Voltage-Controlled Oscillator)
        1. 7.3.6.1 VCO Calibration
        2. 7.3.6.2 Determining the VCO Gain
      7. 7.3.7  Channel Divider
      8. 7.3.8  VCO Doubler
      9. 7.3.9  Output Buffer
      10. 7.3.10 Power-Down Modes
      11. 7.3.11 Phase Synchronization
        1. 7.3.11.1 General Concept
        2. 7.3.11.2 Categories of Applications for SYNC
        3. 7.3.11.3 Procedure for Using SYNC
        4. 7.3.11.4 SYNC Input Pin
      12. 7.3.12 Phase Adjust
      13. 7.3.13 Fine Adjustments for Phase Adjust and Phase SYNC
      14. 7.3.14 Ramping Function
        1. 7.3.14.1 Manual Pin Ramping
          1. 7.3.14.1.1 Manual Pin Ramping Example
        2. 7.3.14.2 Automatic Ramping
          1. 7.3.14.2.1 Automatic Ramping Example (Triangle Wave)
      15. 7.3.15 SYSREF
        1. 7.3.15.1 Programmable Fields
        2. 7.3.15.2 Input and Output Pin Formats
          1. 7.3.15.2.1 Input Format for SYNC and SysRefReq Pins
          2. 7.3.15.2.2 SYSREF Output Format
        3. 7.3.15.3 Examples
        4. 7.3.15.4 SYSREF Procedure
      16. 7.3.16 SysRefReq Pin
    4. 7.4 Device Functional Modes
    5. 7.5 Programming
      1. 7.5.1 Recommended Initial Power-Up Sequence
      2. 7.5.2 Recommended Sequence for Changing Frequencies
      3. 7.5.3 General Programming Requirements
    6. 7.6 Register Maps
      1. 7.6.1  General Registers R0, R1, & R7
        1. Table 25. Field Descriptions
      2. 7.6.2  Input Path Registers
        1. Table 26. Field Descriptions
      3. 7.6.3  Charge Pump Registers (R13, R14)
        1. Table 27. Field Descriptions
      4. 7.6.4  VCO Calibration Registers
        1. Table 28. Field Descriptions
      5. 7.6.5  N Divider, MASH, and Output Registers
        1. Table 29. Field Descriptions
      6. 7.6.6  SYNC and SysRefReq Input Pin Register
        1. Table 30. Field Descriptions
      7. 7.6.7  Lock Detect Registers
        1. Table 31. Field Descriptions
      8. 7.6.8  MASH_RESET
        1. Table 32. Field Descriptions
      9. 7.6.9  SysREF Registers
        1. Table 33. Field Descriptions
      10. 7.6.10 CHANNEL Divider And VCO Doubler Registers
        1. Table 34. Field Descriptions
      11. 7.6.11 Ramping and Calibration Fields
        1. Table 35. Field Descriptions
      12. 7.6.12 Ramping Registers
        1. 7.6.12.1 Ramp Limits
          1. Table 36. Field Descriptions
        2. 7.6.12.2 Ramping Triggers, Burst Mode, and RAMP0_RST
          1. Table 37. Field Descriptions
        3. 7.6.12.3 Ramping Configuration
          1. Table 38. Field Descriptions
      13. 7.6.13 Readback Registers
        1. Table 39. Field Descriptions
  8. 8 Application and Implementation
    1. 8.1 Application Information
      1. 8.1.1 OSCin Configuration
      2. 8.1.2 OSCin Slew Rate
      3. 8.1.3 RF Output Buffer Power Control
      4. 8.1.4 RF Output Buffer Pullup
      5. 8.1.5 Performance Comparison Between 1572 (0x0624) and 3115 (0x0C2B) for Register DBLR_IBIAS_CTRL1 (R25[15:0])
    2. 8.2 Typical Application
      1. 8.2.1 Design Requirements
      2. 8.2.2 Detailed Design Procedure
      3. 8.2.3 Application Curve
  9. 9 Power Supply Recommendations
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11器件和文档支持
    1. 11.1 器件支持
      1. 11.1.1 第三方产品免责声明
      2. 11.1.2 开发支持
    2. 11.2 文档支持
      1. 11.2.1 相关文档
    3. 11.3 接收文档更新通知
    4. 11.4 社区资源
    5. 11.5 商标
    6. 11.6 静电放电警告
    7. 11.7 术语表
  12. 12机械、封装和可订购信息
  13. 重要声明
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DATA SHEET

具有相位同步功能和 JESD204B 支持的 LMX2595 20GHz 宽带 PLLATINUM™ 射频合成器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 10MHz 至 20GHz 输出频率
  • 在 100KHz 偏频和 15GHz 载波的情况下具有 -110dBc/Hz 的相位噪声
  • 7.5GHz 时，具有 45fs rms 抖动（100Hz 至 100MHz）
  • 可编程输出功率
  • PLL 主要规格
    • 品质因数：-236dBc/Hz
    • 标称 1/f 噪声：-129dBc/Hz
    • 最高相位检测器频率
      • 400MHz 整数模式
      • 300MHz 分数模式
    • 32 位分数 N 分频器
  • 用可编程输入乘法器消除整数边界杂散
  • 跨多个设备实现输出相位同步
  • 支持具有 9ps 分辨率可编程延迟的 SYSREF
  • 用于 FMCW 应用的频率斜升和线性调频脉冲生成 能力
  • 小于 20µs VCO 校准速度
  • 3.3V 单电源运行

2 应用

  • 5G 和毫米波无线基础设施
  • 测试和测量设备
  • 雷达
  • MIMO
  • 相控阵天线和波束形成
  • 高速数据转换器时钟（支持 JESD204B）

3 说明

LMX2595 高性能宽带合成器可生成 10MHz 至 20GHz 范围内的任何频率。集成加倍器用于生成 15GHz 以上的频率。品质因数为 -236dBc/Hz 的高性能 PLL 和高相位检测器频率可实现非常低的带内噪声和集成抖动。高速 N 分频器没有预分频器，从而显著减少了杂散的振幅和数量。还有一个可减轻整数边界杂散的可编程输入乘法器。

LMX2595 允许用户同步多个器件的输出，并可在 输入和输出之间确定需要延迟的情况下 应用。频率斜升发生器可在自动斜坡生成选项或手动选项中最多合成 2 段斜坡，以实现最大的灵活性。通过快速校准算法可将频率加快至 20μs 以上。LMX2595 增添了对生成或重复 SYSREF（符合 JESD204B 标准）的支持，此 SYSREF 是高速数据转换器的理想低噪声时钟源。此配置中提供了精细的延迟调节（9ps 分辨率），以解决板迹线的延迟差异。

LMX2595 中的输出驱动器在载波频率为 15GHz 时提供高达 7dBm 的输出功率。该器件采用单个 3.3V 电源供电，并具有集成的 LDO，无需板载低噪声 LDO。

器件信息(1)

器件型号 封装 封装尺寸（标称值）
LMX2595 VQFN (40) 6.00mm × 6.00mm
  1. 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品附录。

Device Images

简化原理图

LMX2595 fbd_snas736.gif

4 修订历史记录

Changes from B Revision (March 2018) to C Revision

  • Changed 将数据表中的最大输出频率从 19GHz 统改为 20GHz。为 DBLR_IBIAS_CTRL1 (R25[15:0]) 新建议的值扩大了输出频率范围，提高了高频性能。DBLR_IBIAS_CTRL1 的原值 (1572) 仍支持高达 19GHz 的输出频率以及电气特性 表中确定的规格。新值 (3115) 可进一步提高性能。Go
  • Deleted the recommended bypass capacitor values for Vcc pins 7, 11, 15, 21, 26 and 37, as these capacitor values are not mandatory and the power supply filtering design is up to the user.Go
  • Added test condition "DBLR_IBIAS_CTRL1 = 1572" for POUT, LVCO2X and H1/2, in order to emphasize that these data are taken while DBLR_IBIAS_CTRL1 is set to the old value (1572). With this register set to 3115, these specs can be improved. The details can be found in the applications section.Go
  • Added a new row for VCO doubler output range in EC table with DBLR_IBIAS_CTRL1 set to 3115. The frequency range is extended to 20 GHz.Go
  • Changed all the 'FRAC_ORDER' to 'MASH_ORDER' to avoid confusionGo
  • Added table note for EC table stating that the performance of 1/2 harmonic, output power and noise floor with doubler enabled can be improved by setting DBLR_IBIAS_CTRL1 = 3115. Go
  • Changed the names of timing specs to align with timing diagram: changed tCE to tES, tCS to tDCS, tCH to tCDH, and tCES to tECSGo
  • Changed the names of timing specs to align with timing diagram: changed tES to tCE, tCES to tECS, added tDCS and tCDH, and changed tCS to tCRGo
  • Changed the serial data input timing diagram and corrected the typo for 'SCK'Go
  • Deleted the note 'The CSB transition from high to low must occur when SCK is low' from the serial data input timing diagram, because SPI mode 4 (CPOL = 1, CPHA = 1) is also supported, and SCK is held high when idle in mode 4Go
  • Added note for the serial data input timing diagram to explain the tCE requirement for mode 4 (CPOL = 1, CPHA = 1) of SPI, because the diagram only indicated SPI mode 1 (CPOL = 0, CPHA = 0)Go
  • Changed the serial data readback timing diagramGo
  • Changed the note about MUXout clocking out and emphasized the effect of tCR on the readback data available timeGo
  • Changed the fOUT test conditions in the Closed-Loop Phase Noise at 3.5 GHz graph from: 14 GHz / 2 = 3.5 GHz to: to 14 GHz / 4 = 3.5 GHz Go
  • Added phase noise plot for 16-, 17- and 20-GHz frequency output Go
  • Changed the phase noise plot for 18- and 19-GHz frequency output after changing DBLR_IBIAS_CTRL1 (R25[15:0]) to the new valueGo
  • Changed the Output Power vs Pull-up graph. Output power below 15GHz is shown in "output power across frequency"; output power above 15GHz is shown in "output power vs temperature with doubler". Go
  • Split the Output Power vs Temperature typical performance plot into two plots: Output Power vs Temperature Without Doubler, which goes up to 15 GHz, and Output Power vs Temperature With Doubler that is between 15 GHz and 21 GHz. The data for "without doubler" is unchanged because change of DBLR_IBIAS_CTRL1 does not impact performance under 15 GHz, while the data for "with doubler" plot is taken with DBLR_IBIAS_CTRL1 (R25[15:0]) set to the new value (3115)Go
  • Added Normalized Output Power Across OUTA_PWR With Resistor Pullup graphGo
  • Changed "Vtune" to "Indirect Vtune" when LD_TYPE = 1Go
  • Changed description for LD_TYPE. Go
  • Added description of Indirect Vtune. Go
  • Added description for the 'no assist' mode, mphasized the effect of VCO_SEL, VCO_DACISET_STRT and VCO_CAPCTRL_STRT under 'no assist' mode, and added recommended values for these registersGo
  • Added description for the 'full assist' mode to allow the user to set VCO amplitude and capcode using linear interpolation under certain conditionsGo
  • Changed OUTx_PWR Recommendations for Resistor Pullup table Go
  • Added description for category 3 of SYNC feature stating that FCAL_EN needs to be 1.Go
  • Changed description of MASH_SEED Go
  • Added 10-ms wait time before re-programming register R0 in recommended initial power-up sequence Go
  • Added the General Programming Requirements section based on frequently asked questionsGo
  • Changed register R4 in the register map to: exposed ACAL_CMP_DLY Go
  • Changed the register R20[14] value from 0 to 1 in the full register map to match the R20 register description Go
  • Changed register R25 in the register map; exposed the register 'DBLR_IBIAS_CTRL1.Go
  • Changed the R0[14] register field name in the register map from VCO_PHASE_SYNC_EN to VCO_PHASE_SYNC. to align with the rest of the data sheetGo
  • Added recommended value for register CAL_CLK_DIV when lock time is not of concernGo
  • Changed the typo for register 'VCO_DACISET' in the register map. Bit 0 of this register was not included in the map. The full register map and register description were correctGo
  • Added description to the R4[15:8]: ACAL_CMP_DLY registerGo
  • Deleted the bit description '0: disabled; 1: enabled' for register 'PLL_N'Go
  • Added description to the R60[15:0] LD_DLY registerGo
  • Added description for register R25[15:0]: DBLR_IBIAS_CTRL1 and changed the default register value from 0x0624 to 0x0C2BGo
  • Changed the R31[14] register name from CHDIV_DIV2 to SEG1_EN to align with the naming in the TICS Pro GUIGo
  • Changed the R105[1:0] field name from RAMP_NEXT_TRIG to RAMP1_NEXT_TRIGGo
  • Added application section "Performance Comparison Between 1572 (0x0624) and 3115 (0x0C2B) For Register DBLR_IBIAS_CTRL1 (R25[15:0])" to compare the performance with old and new DBLR_IBIAS_CTRL1 (R25[15:0]) values.Go
  • Added the Bias Levels of Pins tableGo

Changes from A Revision (August 2017) to B Revision

  • Changed all the VCO Gain typical values in the Electrical Characteristics table. This is due to improved measurement methods and NOT a change in the device itselfGo
  • Moved the high-level output voltage parameter VCC – 0.4 value from the MAX column to the MINGo
  • Moved the high-level output current parameter 0.4 value from the MIN column to the MAXGo
  • Changed bulleted text: data is clocked out on MUXout, not SDI pinGo
  • Added comment that OSCin is clocked on rising edges of the signal. and reformatted with bulleted listGo
  • Added description of the state machine clock Go
  • Changed example from: 200 MHz / 232 to: 200 MHz / (232 – 1) Go
  • Changed LD_DLY description in Table 4 and removed duplicated text in the Lock Detect sectionGo
  • Changed name from VCO_AMPCAL to VCO_DACISET_STRT Go
  • Added more programmable settings to Table 5Go
  • Changed VCO Gain tableGo
  • Added that OUTx_PWR states 32 to 47 are redundant and reworded sectionGo
  • Added term "IncludedDivide" for clarity Go
  • Changed Fixed Diagram to show SEG0, SEG1, SEG2, and SEG3 Go
  • Changed included channel divide to IncludedDivide and 2 X SEG0 to 2 X SEG1. Also clarified IncludedDivide calculationsGo
  • Added more description on conditions for phase adustGo
  • Changed text from: (VCO_PHASE_SYNC = 1) to: (VCO_PHASE_SYNC = 0) Go
  • Changed text so the user does not incorrectly assume that MASH_SEED varies from part ot partGo
  • Changed the RAMP_THRESH programming from: 0 to ± 232 to: 0 to ± 233 – 1Go
  • Removed comment that RAMP_TRIG_CAL only applies in automatic ramping modeGo
  • Changed the RAMP_LOW and _HIGH programming from: 0 to ± 231 to: 0 to ± 233 – 1Go
  • Changed description to be in terms of state machine cyclesGo
  • Changed RAMP_MODE to RAMP_MANUAL in the Manual Pin Ramping and Automatic Ramping sectionsGo
  • Added that the RampCLK pin input is reclocked to the phase detector frequencyGo
  • Added that RampDir rising edges should be targeted away from rising edges of RampCLK pinGo
  • Changed programming enumerations for RAMP0_INC and RAMP1_INCGo
  • Changed programming enumerations for RAMP_THRESH, RAMPx_LEN, and RAMP1_INCGo
  • Changed Figure 35Go
  • Changed SysRef descriptionGo
  • Added divide by 2 to figureGo
  • Changed some entries in the table Go
  • Changed fINTERPOLATOR SYSREF setup equation in Table 19Go
  • Changed SysRef delay from: 224 and 225 to: 225 and 226Go
  • Changed "generator" mode to "master" mode. They mean the same thingGo
  • Changed description for SYSREF_DIVGo
  • Changed Figure 37Go
  • Changed wording for repeater mode and master modeGo
  • Changed description of a few of the stepsGo
  • Changed typo in R17 and R19 Go
  • Deleted reference to VCO_SEL_STRT_EN. This is always 1Go
  • Added VCO_SEL_STRT_EN reference. This is always 1Go
  • Changed the enumerations 0-3 and added content to the INPIN_LVL field description Go
  • Added Divide by 1' to SYSREF_DIV_PRE register description. Also fixed the name misspellingGo
  • Deleted redundant formula for Fout and also clarified SYSREF_DIV starts at 4 and counts by 2Go
  • Deleted reference to VCO_CAPCTRL_EN, which is always 1, and clarifiedGo
  • Changed text from: fMAX to: fHIGHGo
  • Changed text from: RAMP_LIMIT_LOW=232 - (fLOW - fVCO) / fPD × 16777216 to: RAMP_LIMIT_LOW=233 - 16777216 x (fVCO - fLOW) / fPDGo
  • Removed the OSCin Configuration table and added content to the OSCin Configuration sectionGo
  • Changed pin 27 recommendation from 10 µF to 1 µF in Figure 62Go

Changes from * Revision (June 2017) to A Revision

  • Changed "SDA" pin name mispelled. Should be "SDI". Also fixed in timing diagrams. Also added CE Pin Go
  • Clarified that output power assumes that load is matched and losses are de-embeddedGo
  • Swapped SDI and SCK in diagram Go
  • Added section on fine tune adjustments Go
  • Added INPIN_IGNORE, INPIN_LVL, and INPIN_HYSTGo
  • Removed RAMP0_FL from register mapGo
  • Clarified MASH_RESET_N. 0 = RESET (integer mode), 1 = Fractional mode Go
  • Changed OUT_ISEL to OUTI_SET Go
  • Added section for input register descriptions Go
  • Fixed TYPO table to match main register map.Go
  • Corrected RAMP_BURST_TRIG description to match other place in data sheetGo
  • Removed duplicate error in R101[2] Go
  • Changed RAMP1_INC from RAMP0 to RAMP1Go
  • Clarified that the delay was in state machine cyclesGo
  • Fixed pin names in schematic Go

5 Pin Configuration and Functions

RHA Package
40-Pin VQFN
Top View
LMX2595 po_snas696.gif

Pin Functions

PIN I/O DESCRIPTION
NO. NAME
1 CE Input Chip enable input. Active HIGH powers on the device.
2, 4, 25, 31, 34, 39, 40 GND Ground VCO ground.
3 VbiasVCO Bypass VCO bias. Requires a 10-µF capacitor connected to VCO ground. Place close to pin.
5 SYNC Input Phase synchronization pin. Has programmable threshold.
6, 14 GND Ground Digital ground.
7 VccDIG Supply Digital supply. TI recommends bypassing with decoupling capacitor to digital ground.
8 OSCinP Input Reference input clock (+). High-impedance self-biasing pin. Requires AC-coupling capacitor.
(0.1 µF recommended)
9 OSCinM Input Reference input clock (–). High impedance self-biasing pin. Requires AC-coupling capacitor.
(0.1 µF recommended)
10 VregIN Bypass Input reference path regulator output. Requires a 1-µF capacitor connected to ground. Place close to pin.
11 VccCP Supply Charge pump supply. TI recommends bypassing with decoupling capacitor to charge pump ground.
12 CPout Output Charge pump output. TI recommends connecting C1 of loop filter close to pin.
13 GND Ground Charge pump ground.
15 VccMASH Supply Digital supply. TI recommends bypassing with decoupling capacitor to digital ground.
16 SCK Input SPI clock. High impedance CMOS input. 1.8-V to 3.3-V logic.
17 SDI Input SPI data. High impedance CMOS input. 1.8-V to 3.3-V logic.
18 RFoutBM Output Differential output B (–). Requires a pullup (typically 50-Ω resistor) connected to Vcc as close to the pin as possible. Can be used as an output signal or SYSREF output.
19 RFoutBP Output Differential output B (+). Requires a pullup (typically 50-Ω resistor) connected to Vcc as close to the pin as possible. Can be used as an output signal or SYSREF output.
20 MUXout Output Multiplexed output pin — lock detect, readback, diagnostics, ramp status.
21 VccBUF Supply Output buffer supply. TI recommends bypassing with decoupling capacitor to RFout ground.
22 RFoutAM Output Differential output A (–). Requires connecting a 50-Ω resistor pullup to Vcc as close to the pin as possible.
23 RFoutAP Output Differential output A (+). Requires connecting a 50-Ω resistor pullup to Vcc as close to the pin as possible.
24 CSB Input SPI latch. Chip Select Bar. High-impedance CMOS input. 1.8-V to 3.3-V logic.
26 VccVCO2 Supply VCO supply. TI recommends bypassing with decoupling capacitor to VCO ground.
27 VbiasVCO2 Bypass VCO bias. Requires a 1-µF capacitor connected to VCO ground.
28 SysRefReq Input SYSREF request input for JESD204B support.
29 VrefVCO2 Bypass VCO supply reference. Requires a 10-µF capacitor connected to VCO ground.
30 RampClk Input Input pin for ramping mode that can be used to clock the ramp in manual ramping mode or as a trigger input.
32 RampDir Input Input pin for ramping mode that can be used to change ramp direction in manual ramping mode or as a trigger input.
33 VbiasVARAC Bypass VCO Varactor bias. Requires a 10-µF capacitor connected to VCO ground.
35 Vtune Input VCO tuning voltage input.
36 VrefVCO Bypass VCO supply reference. Requires a 10-µF capacitor connected to VCO ground.
37 VccVCO Supply VCO supply. Recommend bypassing with decoupling capacitor to ground.
38 VregVCO Bypass VCO regulator node. Requires a 1-µF capacitor connected to ground.
DAP GND Ground Die Attached Pad. Used for RFout ground.

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCC Power supply voltage –0.3 3.6 V
TJ Junction temperature –40 150 °C
Tstg Storage temperature –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
V(ESD) Electrostatic discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750
(1) JEDEC document JEP155 states that 500 V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 500 V HBM is possible with the necessary precautions. Pins listed as ±XXX V may actually have higher performance.
(2) JEDEC document JEP157 states that 250 V CDM allows safe manufacturing with a standard ESD control process. Manufacturing with less than 250 V CDM is possible with the necessary precautions. Pins listed as ±YYY V may actually have higher performance.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VCC Power supply voltage 3.15 3.3 3.45 V
TA Ambient temperature –40 25 85 °C
TJ Junction temperature 125 °C

6.4 Thermal Information

THERMAL METRIC(1) LMX2595 UNIT
RHA (VQFN)
40 PINS
RθJA Junction-to-ambient thermal resistance 30.5 °C/W
RθJC(top) Junction-to-case (top) thermal resistance (2) 15.3 °C/W
RθJB Junction-to-board thermal resistance 5.4 °C/W
ψJT Junction-to-top characterization parameter 0.2 °C/W
ψJB Junction-to-board characterization parameter 5.3 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9 °C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report (SPRA953).
(2) DAP

6.5 Electrical Characteristics

3.15 V ≤ VCC ≤ 3.45 V, –40°C ≤ TA ≤ +85°C. Typical values are at VCC = 3.3 V, 25°C (unless otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
POWER SUPPLY
VCC Supply voltage 3.15 3.3 3.45 V
ICC Supply current OUTA_PD = 0, OUTB_PD = 1
OUTA_MUX = OUTB_MUX = 1
OUTA_PWR = 31, CPG=7
fOSC= fPD = 100 MHz, fVCO = fOUT = 14 GHz
pOUT = 3 dBm with 50-Ω resistor pullup		 340 mA
Power-on reset current RESET=1 170
Power-down current POWERDOWN=1 5
OUTPUT CHARACTERISTICS
pOUT Single-ended output power(3)(5) 50-Ω resistor pullup
OUTx_PWR = 50 		fOUT = 8 GHz 5 dBm
fOUT = 15 GHz 2
1-nH inductor pullup
OUTx_PWR = 50		 fOUT = 8 GHz 10
fOUT = 15 GHz 7
POUT Single-ended output power with doubler enabled(6) 50-Ω resistor pullup
OUTx_PWR = 20
VCO2X_EN = 1
DBLR_IBIAS_CTRL1 = 1572 		fOUT= 15 GHz 0 dBm
fOUT= 19 GHz –4
1-nH inductor pullup
OUTx_PWR = 20
VCO2X_EN = 1
DBLR_IBIAS_CTRL1 = 1572		 fOUT= 15 GHz 6
fOUT= 19 GHz –1
fVCO2X VCO doubler output range VCO doubler enabled DBLR_IBIAS_CTRL1 = 1572 15 19 GHz
DBLR_IBIAS_CTRL1 = 3115 15 20 GHz
LVCO2X VCO doubler noise floor(6) 50-Ω resistor pullup
OUTx_PWR = 20
DBLR_IBIAS_CTRL1 = 1572		 fOUT= 18 GHz –148 dBc/Hz
Xtalk Isolation between outputs A and B. Measured on output A OUTA_MUX = VCO
OUTB_MUX = channel divider		 –50 dBc
H1/2 1/2 haromnic spur(6) OUTA_MUX=VCO2X
fVCO = 9 GHz
DBLR_IBIAS_CTRL1 = 1572		 –10 dBc
H2 Second harmonic(5) OUTA_MUX = VCO
fVCO = 8 GHz		 –20 dBc
OUTA_MUX = VCO
fVCO = 11 GHz		 –30
H3 Third harmonic(5) OUTA_MUX = VCO
fVCO = 8 GHz		 –50 dBc
INPUT SIGNAL PATH
fOSCin Reference input frequency OSC_2X = 0 5 1400 MHz
OSC_2X = 1 5 200
vOSCin Reference input voltage AC-coupled required (2) 0.2 2 Vpp
fMULT Multiplier frequency (only applies when multiplier is enabled) Input range 30 70 MHz
Output range 180 250
PHASE DETECTOR AND CHARGE PUMP
fPD Phase detector frequency(2) Integer mode MASH_ORDER = 0 0.125 400 MHz
Fractional mode MASH_ORDER= 1, 2, 3 5 300
MASH_ORDER = 4 5 240
ICPout Charge-pump leakage current CPG = 0 15 nA
Effective charge pump current. This is the sum of the up and down currents CPG = 4 3 mA
CPG = 1 6
CPG = 5 9
CPG = 3 12
CPG = 7 15
PNPLL_1/f Normalized PLL 1/f noise fPD = 100 MHz, fVCO = 12 GHz(4)(4)(4)(4) –129 dBc/Hz
PNPLL_flat Normalized PLL noise floor –236 dBc/Hz
VCO CHARACTERISTICS
PNVCO VCO phase noise VCO1
fVCO = 8 GHz		 10 kHz –80 dBc/Hz
100 kHz –107
1 MHz –128
10 MHz –148
90 MHz –157
VCO2
fVCO = 9.2 GHz		 10 kHz –79
100 kHz –105
1 MHz –127
10 MHz –147
90 MHz –157
VCO3
fVCO = 10.3 GHz		 10 kHz –77
100 kHz –104
1 MHz –126
10 MHz –147
90 MHz –157
VCO4
fVCO = 11.3 GHz		 10 kHz –76
100 kHz –103
1 MHz –125
10 MHz –145
90 MHz –158
VCO5
fVCO = 12.5 GHz		 10 kHz –74
100 kHz –100
1 MHz –123
10 MHz –144
90 MHz –157
VCO6
fVCO = 13.3 GHz		 10 kHz –73
100 kHz –100
1 MHz –122
10 MHz –143
90 MHz –155
VCO7
fVCO = 14.5 GHz		 10 kHz –73
100 kHz –99
1 MHz –121
10 MHz –143
90 MHz –152
tVCOCAL VCO calibration speed Switch across the entire frequency band
fOSC = 200 MHz, fPD = 100 MHz(1) 		No assist 50 µs
Partial assist 35
Close frequency 20
Full assist 5
KVCO VCO gain 8 GHz 92 MHz/V
9.2 GHz 91
10.3 GHz 115
11.3 GHz 121
12.5 GHz 195
13.3 GHz 190
14.5 GHz 213
|ΔTCL| Allowable temperature drift when VCO is not recalibrated RAMP_EN = 0 or RAMP_MANUAL= 1 125 °C
H2 VCO second harmonic fVCO = 8 GHz, divider disabled –20 dBc
H3 VCO third haromonic fVCO = 8 GHz, divider disabled –50
SYNC PIN AND PHASE ALIGNMENT
fOSCinSYNC Maximum usable OSCin with sync pin (Figure 33) Category 3 0 100 MHz
Categories1 and 2 0 1400
DIGITAL INTERFACE
Applies to SLK, SDI, CSB, CE, RampDir, RampClk, MUXout, SYNC (CMOS Mode), SysRefReq (CMOS Mode)
VIH High-level input voltage 1.4 Vcc V
VIL Low-level input voltage 0 0.4 V
IIH High-level input current –25 25 µA
IIL Low-level input current –25 25 µA
VOH High-level output voltage MUXout pin Load current = –10 mA VCC – 0.4 V
VOL Low-level output voltage Load current = 10 mA 0.4 V
(1) See Application and Implementation for more details on the different VCO calibration modes.
(2) For lower VCO frequencies, the N divider minimum value can limit the phase-detector frequency.
(3) Single ended output power obtained after de-embedding microstrip trace losses and matching with a manual tuner. Unused port terminated to 50 ohm load.
(4) The PLL noise contribution is measured using a clean reference and a wide loop bandwidth and is composed into flicker and flat components. PLL_flat = PLL_FOM + 20 × log(Fvco/Fpd) + 10 × log(Fpd / 1Hz). PLL_flicker (offset) = PLL_flicker_Norm + 20 × log(Fvco / 1GHz) – 10 × log(offset / 10kHz). Once these two components are found, the total PLL noise can be calculated as PLL_Noise = 10 × log(10 PLL_Flat / 10 + 10 PLL_flicker / 10 )
(5) Output power, spurs, and harmonics can vary based on board layout and components.
(6) 1/2 harmonic, output power and noise floor with doubler enabled are specified in EC table with DBLR_IBIAS_CTRL1 = 1572. However, these specs can be improved by setting DBLR_IBIAS_CTRL1 = 3115. See Performance Comparison Between 1572 (0x0624) and 3115 (0x0C2B) for Register DBLR_IBIAS_CTRL1 (R25[15:0]) for more information.

 
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