具有相位同步功能和 JESD204B 支持的 LMX2595 20GHz 宽带 PLLATINUM™ 射频合成器

1 特性

• 10MHz 至 20GHz 输出频率
• 在 100KHz 偏频和 15GHz 载波的情况下具有 -110dBc/Hz 的相位噪声
• 7.5GHz 时，具有 45fs rms 抖动（100Hz 至 100MHz）
• 可编程输出功率
• PLL 主要规格
  • 品质因数：-236dBc/Hz
  • 标称 1/f 噪声：-129dBc/Hz
  • 最高相位检测器频率
    • 400MHz 整数模式
    • 300MHz 分数模式
  • 32 位分数 N 分频器
• 用可编程输入乘法器消除整数边界杂散
• 跨多个设备实现输出相位同步
• 支持具有 9ps 分辨率可编程延迟的 SYSREF
• 用于 FMCW 应用的频率斜升和线性调频脉冲生成 能力
• 小于 20µs VCO 校准速度
• 3.3V 单电源运行

2 应用

• 5G 和毫米波无线基础设施
• 测试和测量设备
• 雷达
• MIMO
• 相控阵天线和波束形成
• 高速数据转换器时钟（支持 JESD204B）

3 说明

LMX2595 高性能宽带合成器可生成 10MHz 至 20GHz 范围内的任何频率。集成加倍器用于生成 15GHz 以上的频率。品质因数为 -236dBc/Hz 的高性能 PLL 和高相位检测器频率可实现非常低的带内噪声和集成抖动。高速 N 分频器没有预分频器，从而显著减少了杂散的振幅和数量。还有一个可减轻整数边界杂散的可编程输入乘法器。

LMX2595 允许用户同步多个器件的输出，并可在 输入和输出之间确定需要延迟的情况下 应用。频率斜升发生器可在自动斜坡生成选项或手动选项中最多合成 2 段斜坡，以实现最大的灵活性。通过快速校准算法可将频率加快至 20μs 以上。LMX2595 增添了对生成或重复 SYSREF（符合 JESD204B 标准）的支持，此 SYSREF 是高速数据转换器的理想低噪声时钟源。此配置中提供了精细的延迟调节（9ps 分辨率），以解决板迹线的延迟差异。

LMX2595 中的输出驱动器在载波频率为 15GHz 时提供高达 7dBm 的输出功率。该器件采用单个 3.3V 电源供电，并具有集成的 LDO，无需板载低噪声 LDO。

1. 如需了解所有可用封装，请参阅产品说明书末尾的可订购产品附录。

Device Images

简化原理图

4 修订历史记录

Changes from B Revision (March 2018) to C Revision

• Changed 将数据表中的最大输出频率从 19GHz 统改为 20GHz。为 DBLR_IBIAS_CTRL1 (R25[15:0]) 新建议的值扩大了输出频率范围，提高了高频性能。DBLR_IBIAS_CTRL1 的原值 (1572) 仍支持高达 19GHz 的输出频率以及电气特性 表中确定的规格。新值 (3115) 可进一步提高性能。Go
• Deleted the recommended bypass capacitor values for Vcc pins 7, 11, 15, 21, 26 and 37, as these capacitor values are not mandatory and the power supply filtering design is up to the user.Go
• Added test condition "DBLR_IBIAS_CTRL1 = 1572" for P_OUT, L_VCO2X and H1/2, in order to emphasize that these data are taken while DBLR_IBIAS_CTRL1 is set to the old value (1572). With this register set to 3115, these specs can be improved. The details can be found in the applications section.Go
• Added a new row for VCO doubler output range in EC table with DBLR_IBIAS_CTRL1 set to 3115. The frequency range is extended to 20 GHz.Go
• Changed all the 'FRAC_ORDER' to 'MASH_ORDER' to avoid confusionGo
• Added table note for EC table stating that the performance of 1/2 harmonic, output power and noise floor with doubler enabled can be improved by setting DBLR_IBIAS_CTRL1 = 3115. Go
• Changed the names of timing specs to align with timing diagram: changed t_CE to t_ES, t_CS to t_DCS, t_CH to t_CDH, and t_CES to t_ECSGo
• Changed the names of timing specs to align with timing diagram: changed t_ES to t_CE, t_CES to t_ECS, added t_DCS and t_CDH, and changed t_CS to t_CRGo
• Changed the serial data input timing diagram and corrected the typo for 'SCK'Go
• Deleted the note 'The CSB transition from high to low must occur when SCK is low' from the serial data input timing diagram, because SPI mode 4 (CPOL = 1, CPHA = 1) is also supported, and SCK is held high when idle in mode 4Go
• Added note for the serial data input timing diagram to explain the t_CE requirement for mode 4 (CPOL = 1, CPHA = 1) of SPI, because the diagram only indicated SPI mode 1 (CPOL = 0, CPHA = 0)Go
• Changed the serial data readback timing diagramGo
• Changed the note about MUXout clocking out and emphasized the effect of t_CR on the readback data available timeGo
• Changed the f_OUT test conditions in the Closed-Loop Phase Noise at 3.5 GHz graph from: 14 GHz / 2 = 3.5 GHz to: to 14 GHz / 4 = 3.5 GHz Go
• Added phase noise plot for 16-, 17- and 20-GHz frequency output Go
• Changed the phase noise plot for 18- and 19-GHz frequency output after changing DBLR_IBIAS_CTRL1 (R25[15:0]) to the new valueGo
• Changed the Output Power vs Pull-up graph. Output power below 15GHz is shown in "output power across frequency"; output power above 15GHz is shown in "output power vs temperature with doubler". Go
• Split the Output Power vs Temperature typical performance plot into two plots: Output Power vs Temperature Without Doubler, which goes up to 15 GHz, and Output Power vs Temperature With Doubler that is between 15 GHz and 21 GHz. The data for "without doubler" is unchanged because change of DBLR_IBIAS_CTRL1 does not impact performance under 15 GHz, while the data for "with doubler" plot is taken with DBLR_IBIAS_CTRL1 (R25[15:0]) set to the new value (3115)Go
• Added Normalized Output Power Across OUTA_PWR With Resistor Pullup graphGo
• Changed "Vtune" to "Indirect Vtune" when LD_TYPE = 1Go
• Changed description for LD_TYPE. Go
• Added description of Indirect Vtune. Go
• Added description for the 'no assist' mode, mphasized the effect of VCO_SEL, VCO_DACISET_STRT and VCO_CAPCTRL_STRT under 'no assist' mode, and added recommended values for these registersGo
• Added description for the 'full assist' mode to allow the user to set VCO amplitude and capcode using linear interpolation under certain conditionsGo
• Changed OUTx_PWR Recommendations for Resistor Pullup table Go
• Added description for category 3 of SYNC feature stating that FCAL_EN needs to be 1.Go
• Changed description of MASH_SEED Go
• Added 10-ms wait time before re-programming register R0 in recommended initial power-up sequence Go
• Added the General Programming Requirements section based on frequently asked questionsGo
• Changed register R4 in the register map to: exposed ACAL_CMP_DLY Go
• Changed the register R20[14] value from 0 to 1 in the full register map to match the R20 register description Go
• Changed register R25 in the register map; exposed the register 'DBLR_IBIAS_CTRL1.Go
• Changed the R0[14] register field name in the register map from VCO_PHASE_SYNC_EN to VCO_PHASE_SYNC. to align with the rest of the data sheetGo
• Added recommended value for register CAL_CLK_DIV when lock time is not of concernGo
• Changed the typo for register 'VCO_DACISET' in the register map. Bit 0 of this register was not included in the map. The full register map and register description were correctGo
• Added description to the R4[15:8]: ACAL_CMP_DLY registerGo
• Deleted the bit description '0: disabled; 1: enabled' for register 'PLL_N'Go
• Added description to the R60[15:0] LD_DLY registerGo
• Added description for register R25[15:0]: DBLR_IBIAS_CTRL1 and changed the default register value from 0x0624 to 0x0C2BGo
• Changed the R31[14] register name from CHDIV_DIV2 to SEG1_EN to align with the naming in the TICS Pro GUIGo
• Changed the R105[1:0] field name from RAMP_NEXT_TRIG to RAMP1_NEXT_TRIGGo
• Added application section "Performance Comparison Between 1572 (0x0624) and 3115 (0x0C2B) For Register DBLR_IBIAS_CTRL1 (R25[15:0])" to compare the performance with old and new DBLR_IBIAS_CTRL1 (R25[15:0]) values.Go
• Added the Bias Levels of Pins tableGo

Changes from A Revision (August 2017) to B Revision

• Changed all the VCO Gain typical values in the Electrical Characteristics table. This is due to improved measurement methods and NOT a change in the device itselfGo
• Moved the high-level output voltage parameter V_CC – 0.4 value from the MAX column to the MINGo
• Moved the high-level output current parameter 0.4 value from the MIN column to the MAXGo
• Changed bulleted text: data is clocked out on MUXout, not SDI pinGo
• Added comment that OSCin is clocked on rising edges of the signal. and reformatted with bulleted listGo
• Added description of the state machine clock Go
• Changed example from: 200 MHz / 2³² to: 200 MHz / (2³² – 1) Go
• Changed LD_DLY description in Table 4 and removed duplicated text in the Lock Detect sectionGo
• Changed name from VCO_AMPCAL to VCO_DACISET_STRT Go
• Added more programmable settings to Table 5Go
• Changed VCO Gain tableGo
• Added that OUTx_PWR states 32 to 47 are redundant and reworded sectionGo
• Added term "IncludedDivide" for clarity Go
• Changed Fixed Diagram to show SEG0, SEG1, SEG2, and SEG3 Go
• Changed included channel divide to IncludedDivide and 2 X SEG0 to 2 X SEG1. Also clarified IncludedDivide calculationsGo
• Added more description on conditions for phase adustGo
• Changed text from: (VCO_PHASE_SYNC = 1) to: (VCO_PHASE_SYNC = 0) Go
• Changed text so the user does not incorrectly assume that MASH_SEED varies from part ot partGo
• Changed the RAMP_THRESH programming from: 0 to ± 2³² to: 0 to ± 2³³ – 1Go
• Removed comment that RAMP_TRIG_CAL only applies in automatic ramping modeGo
• Changed the RAMP_LOW and _HIGH programming from: 0 to ± 2³¹ to: 0 to ± 2³³ – 1Go
• Changed description to be in terms of state machine cyclesGo
• Changed RAMP_MODE to RAMP_MANUAL in the Manual Pin Ramping and Automatic Ramping sectionsGo
• Added that the RampCLK pin input is reclocked to the phase detector frequencyGo
• Added that RampDir rising edges should be targeted away from rising edges of RampCLK pinGo
• Changed programming enumerations for RAMP0_INC and RAMP1_INCGo
• Changed programming enumerations for RAMP_THRESH, RAMPx_LEN, and RAMP1_INCGo
• Changed Figure 35Go
• Changed SysRef descriptionGo
• Added divide by 2 to figureGo
• Changed some entries in the table Go
• Changed f_INTERPOLATOR SYSREF setup equation in Table 19Go
• Changed SysRef delay from: 224 and 225 to: 225 and 226Go
• Changed "generator" mode to "master" mode. They mean the same thingGo
• Changed description for SYSREF_DIVGo
• Changed Figure 37Go
• Changed wording for repeater mode and master modeGo
• Changed description of a few of the stepsGo
• Changed typo in R17 and R19 Go
• Deleted reference to VCO_SEL_STRT_EN. This is always 1Go
• Added VCO_SEL_STRT_EN reference. This is always 1Go
• Changed the enumerations 0-3 and added content to the INPIN_LVL field description Go
• Added Divide by 1' to SYSREF_DIV_PRE register description. Also fixed the name misspellingGo
• Deleted redundant formula for Fout and also clarified SYSREF_DIV starts at 4 and counts by 2Go
• Deleted reference to VCO_CAPCTRL_EN, which is always 1, and clarifiedGo
• Changed text from: f_MAX to: f_HIGHGo
• Changed text from: RAMP_LIMIT_LOW=2³² - (f_LOW - f_VCO) / f_PD × 16777216 to: RAMP_LIMIT_LOW=2³³ - 16777216 x (f_VCO - f_LOW) / f_PDGo
• Removed the OSCin Configuration table and added content to the OSCin Configuration sectionGo
• Changed pin 27 recommendation from 10 µF to 1 µF in Figure 62Go

Changes from * Revision (June 2017) to A Revision

• Changed "SDA" pin name mispelled. Should be "SDI". Also fixed in timing diagrams. Also added CE Pin Go
• Clarified that output power assumes that load is matched and losses are de-embeddedGo
• Swapped SDI and SCK in diagram Go
• Added section on fine tune adjustments Go
• Added INPIN_IGNORE, INPIN_LVL, and INPIN_HYSTGo
• Removed RAMP0_FL from register mapGo
• Clarified MASH_RESET_N. 0 = RESET (integer mode), 1 = Fractional mode Go
• Changed OUT_ISEL to OUTI_SET Go
• Added section for input register descriptions Go
• Fixed TYPO table to match main register map.Go
• Corrected RAMP_BURST_TRIG description to match other place in data sheetGo
• Removed duplicate error in R101[2] Go
• Changed RAMP1_INC from RAMP0 to RAMP1Go
• Clarified that the delay was in state machine cyclesGo
• Fixed pin names in schematic Go

5 Pin Configuration and Functions

RHA Package

40-Pin VQFN

Top View

6 Specifications

6.1 Absolute Maximum Ratings

6.2 ESD Ratings

6.3 Recommended Operating Conditions

6.4 Thermal Information

6.5 Electrical Characteristics

6.6 Timing Requirements

Figure 1. Serial Data Input Timing Diagram

There are several other considerations for writing on the SPI:

• The R/W bit must be set to 0.
• The data on SDI pin is clocked into a shift register on each rising edge on the SCK pin.
• The CSB must be held low for data to be clocked. Device will ignore clock pulses if CSB is held high.
• When SCK and SDI lines are shared between devices, TI recommends to hold the CSB line high on the device that is not to be clocked.
• Note that t_CE is only a valid spec if CPOL (Clock Polarity) = 0 and CPHA (Clock Phase) = 0 is used for SPI protocol. For SPI mode (CPOL = 1 and CPHA = 1), the minimum distance required between the last rising edge of clock and the rising edge of CSB is t_CE + clock_period/2.

Figure 2. Serial Data Readback Timing Diagram

There are several other considerations for SPI readback:

• The R/W bit must be set to 1.
• The MUXout pin will always be low for the address portion of the transaction.
• The data on MUXout is clocked out at t_CR after the falling edge of SCK. In other words, the readback data will be available at the MUXout pin t_CR after the clock falling edge.
• The data portion of the transition on the SDI line is always ignored.

6.7 Typical Characteristics

fOSC = 100 MHz		Jitter = 55.8 fs (100 Hz - 100 MHz)
fPD = 200 MHz

Figure 3. Closed-Loop Phase Noise at 15 GHz

fOSC = 100 MHz		Jitter = 46.8 fs (100 Hz - 100 MHz)
fPD = 200 MHz

Figure 5. Closed-Loop Phase Noise at 11 GHz

fOSC = 100 MHz		Jitter = 46.87 fs (100 Hz - 100 MHz)
fPD = 200 MHz

Figure 7. Closed-Loop Phase Noise at 8 GHz

fOSC = 100 MHz		fOUT = 14 GHz / 4 = 3.5 GHz
fPD = 200 MHz		Jitter = 49.4 fs (100 Hz - 100 MHz)
fVCO = 14 GHz

Figure 9. Closed-Loop Phase Noise at 3.5 GHz

fOSC = 100 MHz		fOUT = 2 × 8.5 GHz = 17 GHz
fPD = 200 MHz		Jitter = 55.0 fs (100 Hz - 100 MHz)

Figure 11. Closed-Loop Phase Noise at 17 GHz

fOSC = 100 MHz		fOUT = 2 × 9.5 GHz = 19 GHz
fPD = 200 MHz		Jitter = 54.7 fs (100 Hz - 100 MHz)

Figure 13. Closed-Loop Phase Noise at 19 GHz

Figure 15. VCO Ramping 12-GHz to 12.125-GHz Calibration Free

CalTime = 33.6 µs = 5.8 µs (Core) + 14 µs (Fcal) + 13.8 µs (Ampcal)

fOSC = 200 MHz, fPD = 100 MHz, fVCO = 7.5 - 14 GHz, CHDIV = 2

Figure 17. VCO Unassisted Calibration

fVCO = 12 GHz		fPD = 100 MHz

Figure 19. Calculation of PLL Noise Metrics

fVCO = 8 GHz, Narrow Loop Bandwidth (<100 Hz)

Figure 21. VCO Phase Noise Over Temperature

Single-Ended Output	OUTx_PWR = 50
VCO2X_EN = 0

Figure 23. Output Power Across Frequency

Single-ended output with resistor pullup.	OUTA_PWR = 20
DBLR_IBIAS_CTRL1 = 3115

Figure 25. Output Power vs. Temperature With Doubler

This noise adds to the scaled VCO Noise when the channel divider is used.

Figure 27. Additive VCO Divider Noise Floor

fOSC = 100 MHz		Jitter = 52.6 fs (100 Hz - 100 MHz)
fPD = 200 MHz

Figure 4. Closed-Loop Phase Noise at 13 GHz

fOSC = 100 MHz		Jitter = 46.9 fs (100 Hz - 100 MHz)
fPD = 200 MHz

Figure 6. Closed-Loop Phase Noise at 9 GHz

fOSC = 100 MHz		Jitter = 44.1 fs (100 Hz - 100 MHz)
fPD = 200 MHz

Figure 8. Closed-Loop Phase Noise at 7.5 GHz

fOSC = 100 MHz		fOUT = 2 × 8 GHz = 16 GHz
fPD = 200 MHz		Jitter = 52.9 fs (100 Hz - 100 MHz)

Figure 10. Closed-Loop Phase Noise at 16 GHz

fOSC = 100 MHz		fOUT = 2 × 9 GHz = 18 GHz
fPD = 200 MHz		Jitter = 52.6 fs (100 Hz - 100 MHz)

Figure 12. Closed-Loop Phase Noise at 18 GHz

fOSC = 100 MHz		fOUT = 2 × 10 GHz = 20 GHz
fPD = 200 MHz		Jitter = 52.7 fs (100 Hz - 100 MHz)

Figure 14. Closed-Loop Phase Noise at 20 GHz

The glitches in the plot are due to the inability of the measurement equipment to track the VCO while calibrating.

Figure 16. VCO Ramping 7.5-GHz to 15-GHz Triangle Wave With VCO Calibration

CalTime = 25.2 µs = 1.3 µs (Core) + 9.1 µs (Fcal) +14.8 µs (Ampcal)

fOSC = 200 MHz, fPD = 100 MHz, fVCO = 7.5 GHz - 14 GHz, CHDIV = 2

Figure 18. VCO Calibration With Partial Assist

fOSC = 200 MHz

fVCO = 14.8 GHz

Figure 20. PLL Phase Noise Variation vs. f_PD

f_VCO = 8 GHz, Narrow Loop Bandwidth (<100 Hz)

Figure 22. CHANGE in 8-GHz VCO Phase Noise Over Temperature

Single-ended output with resistor pullup and OUTx_PWR = 50. Note that Near 13.3 to 14.3 GHz, output power can be impacted at hot temperature. See the Application Information section for more information.

Figure 24. Output Power vs Temperature Without Doubler

Resistor pullup	Normalized to maximum output power.

Figure 26. Output Power Normalized To Maximum Across OUTA_PWR With Resistor Pullup

7 Detailed Description

7.1 Overview

The LMX2595 is a high-performance, wideband frequency synthesizer with integrated VCO and output divider. The VCO operates from 7.5 GHz to 15 GHz, and this can be combined with the output divider to produce any frequency in the range of 10 MHz to 15 GHz. The LMX2595 also features a VCO doubler that can be used to produce frequencies up to 20 GHz. Within the input path, there are two dividers and a multiplier for flexible frequency planning. The multiplier also allows the reduction of spurs by moving the frequencies away from the integer boundary.

The PLL is fractional-N PLL with a programmable delta-sigma modulator up to 4^th order. The fractional denominator is a programmable 32-bit long, which can easily provide fine frequency steps below 1-Hz resolution, or be used to do exact fractions like 1/3, 7/1000, and many others. The phase frequency detector goes up to 300 MHz in fractional mode or 400 MHz in integer mode, although minimum N-divider values must also be taken into account.

For applications where deterministic or adjustable phase is desired, the SYNC pin can be used to get the phase relationship between the OSCin and RFout pins deterministic. When this is done, the phase can be adjusted in very fine steps of the VCO period divided by the fractional denominator.

The ultra-fast VCO calibration is designed for applications where the frequency must be swept or abruptly changed. The frequency can be manually programmed, or the device can be set up to do ramps and chirps.

The JESD204B support includes using the RFoutB output to create a differential SYSREF output that can be either a single pulse or a series of pulses that occur at a programmable distance away from the rising edges of the output signal.

The LMX2595 device requires only a single 3.3-V power supply. The internal power supplies are provided by integrated LDOs, eliminating the need for high-performance external LDOs.

The digital logic for the SPI interface and is compatible with voltage levels from 1.8 V to 3.3 V.

Table 1 shows the range of several of the dividers, multipliers, and fractional settings.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 Reference Oscillator Input

The OSCin pins are used as a frequency reference input to the device. The input is high impedance and requires AC-coupling caps at the pin. A CMOS clock or XO can drive the single-ended OSCin pins. Differential clock input is also supported, making it easier to interface with high-performance system clock devices such as TI’s LMK series clock devices. As the OSCin signal is used as a clock for the VCO calibration, a proper reference signal must be applied at the OSCin pin at the time of programming FCAL_EN.

7.3.2 Reference Path

The reference path consists of an OSCin doubler (OSC_2X), Pre-R divider, multiplier (MULT) and a Post-R divider.

Figure 28. Reference Path Diagram

The OSCin doubler (OSC_2X) can double up low OSCin frequencies. Pre-R (PLL_R_PRE) and Post-R (PLL_R) dividers both divide frequency down while the multiplier (MULT) multiplies frequency up. The purposes of adding a multiplier is to reduce integer boundary spurs or to increase the phase detector frequency. Use Equation 1 to calculate the phase detector frequency, f_PD:

• In the OSCin doubler or input multiplier is used, the OSCin signal should have a 50% duty cycle as both the rising and falling edges are used.
• If neither the OSCin doubler nor the input multiplier are used, only rising edges of the OSCin signal are used and duty cycle is not critical.
• The input multiplier and OSCin doubler should not both be used at the same time.