Data Sheet
LMK62XX 高性能低抖动振荡器
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1 特性
- 低噪声、高性能
- 抖动：150fs RMS 典型值 Fout > 100MHz
- PSRR：–60dBc，具有强大的抗电源噪声能力
- 支持的输出格式：
- 低压正发射极耦合逻辑 (LVPECL)、低压差分信令 (LVDS) 和高速收发器逻辑 (HCSL) 高达 400MHz
- 总频率容差：±50ppm (LMK62X2) 和 ±25ppm (LMK62X0)
- 3.3V 工作电压
- 工业温度范围：–40°C 至 +85°C
- 5mm × 3.2mm 6 引脚封装，与业界通用 5032 XO 封装引脚兼容
2 应用
- 晶体振荡器、SAW 振荡器或芯片振荡器的高性能替代产品
- 开关、路由器、网卡、基带装置 (BBU)、服务器、存储/SAN
- 测试和测量
- 医疗成像
- FPGA、处理器连接
3 说明
LMK62XX 器件是一款低抖动振荡器，可生成常用参考时钟。该器件在工厂预编程，可支持任何参考时钟频率；支持的输出格式是 LVPECL、LVDS 和 HCSL（最高 400MHz）。内部电源调节功能提供出色的电源纹波抑制 (PSRR)，降低了供电网络的成本和复杂性。该器件由单个 3.3V ± 5% 电源供电。
器件信息
| 器件型号 | 输出频率 (MHz) 及格式 | 总频率稳定性 (ppm) | 封装尺寸(1)(2) |
|---|---|---|---|
| LMK62E2-100M | 100 LVPECL | ±50 | SIA（QFM，6） 5.00mm × 3.20mm |
| LMK62E2-156M | 156.25 LVPECL | ±50 | |
| LMK62E0-156M | 156.25 LVPECL | ±25 | |
| LMK62A2-100M | 100 LVDS | ±50 | |
| LMK62A2-150M | 150 LVDS | ±50 | |
| LMK62A2-156M | 156.25 LVDS | ±50 | |
| LMK62A2-200M | 200 LVDS | ±50 | |
| LMK62A2-266M | 266.66 LVDS | ±50 | |
| LMK62I0-100M | 100 HCSL | ±25 | |
| LMK62I0-156M | 156.25 HCSL | ±25 |
(1) 有关所有可用封装，请参阅节 10。
(2) 封装尺寸（长 × 宽）为标称值，并包括引脚（如适用）。
引脚分配4 Pin Configuration and Functions
Figure 4-1 SIA Package6-pin QFMTop ViewTable 4-1 Pin Functions
| PIN | I/O | DESCRIPTION | |
|---|---|---|---|
| NAME | NO. | ||
| POWER | |||
| GND | 3 | Ground | Device ground |
| VDD | 6 | Analog | 3.3-V power supply |
| OUTPUT BLOCK | |||
| OUTP | 4 | Universal | Differential output pair (LVPECL, LVDS or HCSL). |
| OUTN | 5 | ||
| DIGITAL CONTROL / INTERFACES | |||
| NC | 2 | N/A | No connect |
| OE | 1 | LVCMOS | Output enable (internal pulldown). When set to low,
output pair is disabled and set at high impedance. The recommended external pullup resistor value is 10 kΩ. |
5 Specifications
5.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
| MIN | MAX | UNIT | ||
|---|---|---|---|---|
| VDD | Device supply voltage | –0.3 | 3.6 | V |
| VIN | Output voltage for logic inputs | –0.3 | VDD + 0.3 | V |
| VOUT | Output voltage for clock outputs | –0.3 | VDD + 0.3 | V |
| TJ | Junction temperature | 150 | °C | |
| Tstg | Storage temperature | –40 | 125 | °C |
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute maximum-rated conditions for extended periods may affect device reliability.
5.2 ESD Ratings
| VALUE | UNIT | |||
|---|---|---|---|---|
| V(ESD) | Electrostatic discharge | Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) | ±2000 | V |
| Charged-device model (CDM), per JEDEC specification JESD22-C101(2) | ±500 | |||
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
| MIN | NOM | MAX | UNIT | ||
|---|---|---|---|---|---|
| VDD | Device supply voltage | 3.135 | 3.3 | 3.465 | V |
| TA | Ambient temperature | –40 | 25 | 85 | °C |
| TJ | Junction temperature | 105 | °C | ||
| tRAMP | VDD power-up ramp time | 0.1 | 100 | ms | |
5.4 Thermal Information
| THERMAL METRIC(1) | LMK62XX (2) (3) (4) | UNIT | |||
|---|---|---|---|---|---|
| SIA (QFM ) | |||||
| 6 PINS | |||||
| Airflow (LFM) 0 | |||||
| RθJA | Junction-to-ambient thermal resistance | 94.5 | °C/W | ||
| RθJC(top) | Junction-to-case (top) thermal resistance | 65.1 | °C/W | ||
| RθJB | Junction-to-board thermal resistance | 59 | °C/W | ||
| ψJT | Junction-to-top characterization parameter | 23.3 | °C/W | ||
| ψJB | Junction-to-board characterization parameter | 64.1 | °C/W | ||
| RθJC(bot) | Junction-to-case (bottom) thermal resistance | n/a | °C/W | ||
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.
(2) The package thermal resistance is calculated on a 4-layer JEDEC board.
(3) Connected to GND with 2 thermal vias (0.3-mm diameter).
(4) ψJB (junction to board) is used when the main heat flow is from the junction to the GND pad. Please refer to Thermal Considerations section for more information on ensuring good system reliability and quality.
5.5 Electrical Characteristics - Power Supply
VDD = 3.3 V ± 5%, TA = –40°C to 85°C(1)
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| IDD | Device current consumption | LVPECL(2) | 95 | 110 | mA | |
| LVDS | 85 | 100 | ||||
| HCSL(3) | 90 | 105 | ||||
| IDD-PD | Device current consumption when output is disabled | OE = GND | 70 | mA | ||
(1) See Parameter Measurement Information for relevant test conditions.
(2) On-chip power dissipation should exclude 40 mW, dissipated in the 150-Ω termination resistors, from total power dissipation.
(3) Excludes load current.
5.6 LVPECL Output Characteristics
VDD = 3.3 V ± 5%, TA = –40°C to 85°C(1)
| PARAMETER | TEST CONDITIONS | MIN | TYP | MAX | UNIT | |
|---|---|---|---|---|---|---|
| fOUT | Output frequency(2) | 400 | MHz | |||
| VOD | Output voltage swing (VOH – VOL)(2) | 700 | 950 | 1200 | mV | |
| VOUT, DIFF, PP | Differential output peak-to-peak swing | 2 × |VOD| | V | |||
| VOS | Output common-mode voltage | VDD – 1.45 | V | |||
| tR / tF | Output rise/fall time (20% to 80%)(3) | 260 | 350 | ps | ||
| ODC | Output duty cycle(3) | 45% | 55% | |||
(1) See Parameter Measurement Information for relevant test conditions.
(2) An output frequency over fOUT max spec is possible, but output swing may be less than VOD min spec.
(3) Ensured by characterization.
