具有宽占空比范围的 LM25145 6V 至 42V 同步降压直流/直流控制器

8.3.1 Input Range (VIN)

The LM25145 operational input voltage range is from 6 V to 42 V. The device is intended for step-down conversions from 12-V, 24-V, 28-V and 36-V unregulated, semiregulated, and fully-regulated supply rails. The application circuit of Figure 31 shows all the necessary components to implement an LM25145-based wide-V_IN step-down regulator using a single supply. The LM25145 uses an internal LDO subregulator to provide a 7.5-V VCC bias rail for the gate drive and control circuits (assuming the input voltage is higher than 7.5 V plus the necessary subregulator dropout specification).

Figure 31. Schematic Diagram for VIN Operating Range of 6 V to 42 V

In high voltage applications, take extra care to ensure the VIN pin does not exceed the absolute maximum voltage rating of 55 V during line or load transient events. Voltage ringing on the VIN pin that exceeds the Absolute Maximum Ratings can damage the IC. Use high-quality ceramic input capacitors to minimize ringing. An RC filter from the input rail to the VIN pin (for example, 4.7 Ω and 0.1 µF) provides supplementary filtering at the VIN pin.

8.3.2 Output Voltage Setpoint and Accuracy (FB)

The reference voltage at the FB pin is set at 0.8 V with a feedback system accuracy over the full junction temperature range of ±1%. Junction temperature range for the device is –40°C to +125°C. While dependent on switching frequency and load current levels, the LM25145 is generally capable of providing output voltages in the range of 0.8 V to a maximum of slightly less than VIN. The DC output voltage setpoint during normal operation is set by the feedback resistor network, R_FB1 and R_FB2, connected to the output.

8.3.3 High-Voltage Bias Supply Regulator (VCC)

The LM25145 contains an internal high-voltage VCC regulator that provides a bias supply for the PWM controller and its gate drivers for the external MOSFETs. The input pin (VIN) can be connected directly to an input voltage source up to 42 V. The output of the VCC regulator is set to 7.5 V. However, when the input voltage is below the VCC setpoint level, the VCC output tracks V_IN with a small voltage drop. Connect a ceramic decoupling capacitor between 1 µF and 5 µF from VCC to AGND for stability.

The VCC regulator output has a current limit of 40 mA (minimum). At power up, the regulator sources current into the capacitor connected to the VCC pin. When the VCC voltage exceeds its rising UVLO threshold of 4.93 V, the output is enabled (if EN/UVLO is above 1.2 V) and the soft-start sequence begins. The output remain active until the VCC voltage falls below its falling UVLO threshold of 4.67 V (typical) or if EN/UVLO goes to a standby or shutdown state.

Internal power dissipation of the VCC regulator can be minimized by connecting the output voltage or an auxiliary bias supply rail (up to 13 V) to VCC using a diode D_VCC as shown in Figure 32. A diode in series with the input prevents reverse current flow from VCC to VIN if the input voltage falls below the external VCC rail.

Figure 32. VCC Bias Supply Connection From VOUT or Auxiliary Supply

Note that a finite bias supply regulator dropout voltage exists and is manifested to a larger extent when driving high gate charge (Q_G) power MOSFETs at elevated switching frequencies. For example, at V_VIN = 6 V, the VCC voltage is 5.8 V with a DC operating current, I_VCC, of 20 mA. Such a low gate drive voltage may be insufficient to fully enhance the power MOSFETs. At the very least, MOSFET on-state resistance, R_DS(ON), may increase at such low gate drive voltage.

Here are the main considerations when operating at input voltages below 7.5 V:

• Increased MOSFET R_DS(on) at lower V_GS, leading to Increased conduction losses and reduced OCP setpoint.
• Increased switching losses given the slower switching times when operating at lower gate voltages.
• Restricted range of suitable power MOSFETs to choose from (MOSFETs with R_DS(on) rated at V_GS = 4.5 V become mandatory).

8.3.4 Precision Enable (EN/UVLO)

The EN/UVLO input supports adjustable input undervoltage lockout (UVLO) with hysteresis programmed by the resistor values for application specific power-up and power-down requirements. EN/UVLO connects to a comparator-based input referenced to a 1.2-V bandgap voltage. An external logic signal can be used to drive the EN/UVLO input to toggle the output ON and OFF and for system sequencing or protection. The simplest way to enable the operation of the LM25145 is to connect EN/UVLO directly to VIN. This allows self start-up of the LM25145 when V_CC is within its valid operating range. However, many applications benefit from using a resistor divider R_UV1 and R_UV2 as shown in Figure 33 to establish a precision UVLO level.

Use Equation 1 and Equation 2 to calculate the UVLO resistors given the required input turnon and turnoff voltages.

Equation 1.

Equation 2.

Figure 33. Programmable Input Voltage UVLO Turnon and Turnoff

The LM25145 enters a low I_Q shutdown mode when EN/UVLO is pulled below approximately 0.4 V. The internal LDO regulator powers off and the internal bias supply rail collapses, shutting down the bias currents of the LM25145. The LM25145 operates in standby mode when the EN/UVLO voltage is between the hard shutdown and precision enable (standby) thresholds.

8.3.5 Power Good Monitor (PGOOD)

The LM25145 provides a PGOOD flag pin to indicate when the output voltage is within a regulation window. Use the PGOOD signal as shown in Figure 34 for start-up sequencing of downstream converters, fault protection, and output monitoring. PGOOD is an open-drain output that requires a pullup resistor to a DC supply not greater than 13 V. The typical range of pullup resistance is 10 kΩ to 100 kΩ. If necessary, use a resistor divider to decrease the voltage from a higher voltage pullup rail.

Figure 34. Master-Slave Sequencing Implementation Using PGOOD and EN/UVLO

When the FB voltage exceeds 94% of the internal reference V_REF, the internal PGOOD switch turns off and PGOOD can be pulled high by the external pullup. If the FB voltage falls below 92% of V_REF, the internal PGOOD switch turns on, and PGOOD is pulled low to indicate that the output voltage is out of regulation. Similarly, when the FB voltage exceeds 108% of V_REF, the internal PGOOD switch turns on, pulling PGOOD low. If the FB voltage subsequently falls below 105% of V_REF, the PGOOD switch is turned off and PGOOD is pulled high. PGOOD has a built-in deglitch delay of 25 µs.

8.3.6 Switching Frequency (RT, SYNCIN)

There are two options for setting the switching frequency, F_SW, of the LM25145, thus providing a power supply designer with a level of flexibility when choosing external components for various applications. To adjust the frequency, use a resistor from the RT pin to AGND, or synchronize the LM25145 to an external clock signal through the SYNCIN pin.

8.3.6.1 Frequency Adjust

Adjust the LM25145 free-running switching frequency by using a resistor from the RT pin to AGND. The switching frequency range is from 100 kHz to 1 MHz. The frequency set resistance, R_RT, is governed by Equation 3. E96 standard-value resistors for common switching frequencies are given in Table 1.

Equation 3.

Table 1. Frequency Set Resistors

SWITCHING FREQUENCY (kHz)	FREQUENCY SET RESISTANCE (kΩ)
100	100
200	49.9
250	40.2
300	33.2
400	24.9
500	20
750	13.3
1000	10

8.3.6.2 Clock Synchronization

Apply an external clock synchronization signal to the LM25145 to synchronize switching in both frequency and phase. Requirements for the external clock SYNC signal are:

• Clock frequency range: 100 kHz to 1 MHz
• Clock frequency: –20% to +50% of the free-running frequency set by R_RT
• Clock maximum voltage amplitude: 13 V
• Clock minimum pulse width: 50 ns

Figure 35. Typical 400-kHz SYNCIN and SW Voltage Waveforms

Figure 35 shows a clock signal at 400 kHz and the corresponding SW node waveform (V_IN = 24 V, V_OUT = 5 V, free-running frequency = 280 kHz). The SW voltage waveform is synchronized with respect to the rising edge of SYNCIN. The rising edge of the SW voltage is phase delayed relative to SYNCIN by approximately 100 ns.

8.3.7 Configurable Soft-Start (SS/TRK)

After the EN/UVLO pin exceeds its rising threshold of 1.2 V, the LM25145 begins charging the output to the DC level dictated by the feedback resistor network. The LM25145 features an adjustable soft-start (set by a capacitor from the SS/TRK pin to GND) that determines the charging time of the output. A 10-µA current source charges this soft-start capacitor. Soft-start limits inrush current as a result of high output capacitance to avoid an overcurrent condition. Stress on the input supply rail is also reduced. The soft-start time, t_SS, for the output voltage to ramp to its nominal level is set by Equation 4.

Equation 4.

where

• C_SS is the soft-start capacitance
• V_REF is the 0.8-V reference
• I_SS is the 10-µA current sourced from the SS/TRK pin.

More simply, calculate C_SS using Equation 5.

Equation 5.

The SS/TRK pin is internally clamped to V_FB + 115 mV to allow a soft-start recovery from an overload event. The clamp circuit requires a soft-start capacitance greater than 2 nF for stability and has a current limit of approximately 2 mA.

8.3.7.1 Tracking

The SS/TRK pin also doubles as a tracking pin when master-slave power-supply tracking is required. This tracking is achieved by simply dividing down the output voltage of the master with a simple resistor network. Coincident, ratiometric, and offset tracking modes are possible.

If an external voltage source is connected to the SS/TRK pin, the external soft-start capability of the LM25145 is effectively disabled. The regulated output voltage level is reached when the SS/TRACK pin reaches the 0.8-V reference voltage level. It is the responsibility of the system designer to determine if an external soft-start capacitor is required to keep the device from entering current limit during a start-up event. Likewise, the system designer must also be aware of how fast the input supply ramps if the tracking feature is enabled.

Figure 36. Typical Output Voltage Tracking and PGOOD Waveforms

Figure 36 shows a triangular voltage signal directly driving SS/TRK and the corresponding output voltage tracking response. Nominal output voltage here is 5 V, with oscilloscope channel scaling chosen such that the waveforms overlap during tracking. As expected, the PGOOD flag transitions at thresholds of 94% (rising) and 92% (falling) of the nominal output voltage setpoint.

Two practical tracking configurations, ratiometric and coincident, are shown in Figure 37. The most common application is coincident tracking, used in core versus I/O voltage tracking in DSP and FPGA implementations. Coincident tracking forces the master and slave channels to have the same output voltage ramp rate until the slave output reaches its regulated setpoint. Conversely, ratiometric tracking sets the output voltage of the slave to a fraction of the output voltage of the master during start-up.

Figure 37. Tracking Implementation With Master, Ratiometric Slave, and Coincident Slave Rails

For coincident tracking, connect the SS/TRK input of the slave regulator to a resistor divider from the output voltage of the master that is the same as the divider used on the FB pin of the slave. In other words, simply select R_TRK3 = R_FB3 and R_TRK4 = R_FB4 as shown in . As the master voltage rises, the slave voltage rises identically (aside from the 80-mV offset from SS/TRK to FB when V_FB is below 0.8 V). Eventually, the slave voltage reaches its regulation voltage, at which point the internal reference takes over the regulation while the SS/TRK input continues to 115 mV above FB, and no longer controls the output voltage.

In all cases, to ensure that the output voltage accuracy is not compromised by the SS/TRK voltage being too close to the 0.8-V reference voltage, the final value of the SS/TRK voltage of the slave should be at least 100 mV above FB.

8.3.8 Voltage-Mode Control (COMP)

The LM25145 incorporates a voltage-mode control loop implementation with input voltage feedforward to eliminate the input voltage dependence of the PWM modulator gain. This configuration allows the controller to maintain stability throughout the entire input voltage operating range and provides for optimal response to input voltage transient disturbances. The constant gain provided by the controller greatly simplifies loop compensation design because the loop characteristics remain constant as the input voltage changes, unlike a buck converter without voltage feedforward. An increase in input voltage is matched by a concomitant increase in ramp voltage amplitude to maintain constant modulator gain. The input voltage feedforward gain, k_FF, is 15, equivalent to the input voltage divided by the ramp amplitude, V_IN/V_RAMP. See Control Loop Compensation for more detail.

8.3.9 Gate Drivers (LO, HO)

The LM25145 gate driver impedances are low enough to perform effectively in high output current applications where large die-size or paralleled MOSFETs with correspondingly large gate charge, Q_G, are used. Measured at V_VCC = 7.5 V, the low-side driver of the LM25145 has a low impedance pulldown path of 0.9 Ω to minimize the effect of dv/dt induced turnon, particularly with low gate-threshold voltage MOSFETs. Similarly, the high-side driver has 1.5-Ω and 0.9-Ω pullup and pulldown impedances, respectively, for faster switching transition times, lower switching loss, and greater efficiency.

The high-side gate driver works in conjunction with an integrated bootstrap diode and external bootstrap capacitor, C_BST. When the low-side MOSFET conducts, the SW voltage is approximately at 0 V and C_BST is charged from VCC through the integrated boot diode. Connect a 0.1-μF or larger ceramic capacitor close to the BST and SW pins.

Furthermore, there is a proprietary adaptive dead-time control on both switching edges to prevent shoot-through and cross-conduction, minimize body diode conduction time, and reduce body diode reverse recovery losses.

8.3.10 Current Sensing and Overcurrent Protection (ILIM)

The LM25145 implements a lossless current sense scheme designed to limit the inductor current during an overload or short-circuit condition. Figure 38 portrays the popular current sense method using the on-state resistance of the low-side MOSFET. Meanwhile, Figure 39 shows an alternative implementation with current shunt resistor, R_S. The LM25145 senses the inductor current during the PWM off-time (when LO is high).

Figure 38. MOSFET R_DS(on) Current Sensing

Figure 39. Shunt Resistor Current Sensing

The ILIM pin of the LM25145 sources a reference current that flows in an external resistor, designated R_ILIM, to program of the current limit threshold. A current limit comparator on the ILIM pin prevents further SW pulses if the ILIM pin voltage goes below GND. Figure 40 shows the implementation.

Resistor R_ILIM is tied to SW to use the R_DS(on) of the low-side MOSFET as a sensing element (termed R_DS-ON mode). Alternatively, R_ILIM is tied to a shunt resistor connected at the source of the low-side MOSFET (termed R_SENSE mode). The LM25145 detects the appropriate mode at start-up and sets the source current amplitude and temperature coefficient (TC) accordingly.

The ILIM current with R_DS-ON sensing is 200 µA at 27°C junction temperature and incorporates a TC of +4500 ppm/°C to generally track the R_DS(on) temperature variation of the low-side MOSFET. Conversely, the ILIM current is a constant 100 µA in R_SENSE mode. This controls the valley of the inductor current during a steady-state overload at the output. Depending on the chosen mode, select the resistance of R_ILIM using Equation 6.

Equation 6.

where

• ΔI_L is the peak-to-peak inductor ripple current
• R_DS(on)Q2 is the on-state resistance of the low-side MOSFET
• I_RDSON is the ILIM pin current in R_DS-ON mode
• R_S is the resistance of the current-sensing shunt element, and
• I_RS is the ILIM pin current in R_SENSE mode.

Given the large voltage swings of ILIM in R_DS-ON mode, a capacitor designated C_ILIM connected from ILIM to PGND is essential to the operation of the valley current limit circuit. Choose this capacitance such that the time constant R_ILIM · C_ILIM is approximately 6 ns.

Figure 40. OCP Setpoint Defined by Current Source I_RDSON and Resistor R_ILIM in R_DS-ON Mode

Note that current sensing with a shunt component is typically implemented at lower output current levels to provide accurate overcurrent protection. Burdened by the unavoidable efficiency penalty, PCB layout, and additional cost implications, this configuration is not usually implemented in high-current applications (except where OCP setpoint accuracy and stability over the operating temperature range are critical specifications).

8.3.11 OCP Duty Cycle Limiter

Figure 41. OCP Duty Cycle Limiting Waveforms

In addition to valley current limiting, the LM25145 uses a proprietary duty-cycle limiter circuit to reduce the PWM on-time during an overcurrent condition. As shown in Figure 40, an auxiliary PWM comparator along with a modulated CLAMP voltage limits how quickly the on-time increases in response to a large step in the COMP voltage that typically occurs with a voltage-mode control loop architecture.

As depicted in Figure 41, the CLAMP voltage, V_CLAMP, is normally regulated above the COMP voltage to provide adequate headroom during a response to a load-on transient. If the COMP voltage rises quickly during an overloaded or shorted output condition, the on-time pulse terminates thereby limiting the on-time and peak inductor current. Moreover, the CLAMP voltage is reduced if additional valley current limit events occur, further reducing the average output current.

If the overcurrent condition exists for 128 continuous clock cycles, a hiccup event is triggered and SS is pulled low for 8192 clock cycles before a soft-start sequence is initiated.

8.4.1 Shutdown Mode

The EN/UVLO pin provides ON / OFF control for the LM25145. When the EN/UVLO voltage is below 0.37 V (typical), the device is in shutdown mode. Both the internal bias supply LDO and the switching regulator are off. The quiescent current in shutdown mode drops to 13.5 μA (typical) at V_IN = 24 V. The LM25145 also includes undervoltage protection of the internal bias LDO. If the internal bias supply voltage is below its UVLO threshold level, the switching regulator remains off.

8.4.2 Standby Mode

The internal bias supply LDO has a lower enable threshold than the switching regulator. When the EN/UVLO voltage exceeds 0.42 V (typical) and is below the precision enable threshold (1.2 V typically), the internal LDO is on and regulating. Switching action and output voltage regulation are disabled in standby mode.

8.4.3 Active Mode

The LM25145 is in active mode when the VCC voltage is above its rising UVLO threshold of 5 V and the EN/UVLO voltage is above the precision EN threshold of 1.2 V. The simplest way to enable the LM25145 is to tie EN/UVLO to VIN. This allows self start-up of the LM25145 when the input voltage exceeds the VCC threshold plus the LDO dropout voltage from VIN to VCC.

8.4.4 Diode Emulation Mode

The LM25145 provides a diode emulation feature that can be enabled to prevent reverse (drain-to-source) current flow in the low-side MOSFET. When configured for diode emulation, the low-side MOSFET is switched off when reverse current flow is detected by sensing of the SW voltage using a zero-cross comparator. The benefit of this configuration is lower power loss at no-load and light-load conditions, the disadvantage being slower light-load transient response.

The diode emulation feature is configured with the SYNCIN pin. To enable diode emulation and thus achieve discontinuous conduction mode (DCM) operation at light loads, connect the SYNCIN pin to AGND or leave SYNCIN floating. If forced PWM (FPWM) continuous conduction mode (CCM) operation is desired, tie SYNCIN to VCC either directly or using a pullup resistor. Note that diode emulation mode is automatically engaged to prevent reverse current flow during a prebias start-up. A gradual change from DCM to CCM operation provides monotonic start-up performance.

8.4.5 Thermal Shutdown

The LM25145 includes an internal junction temperature monitor. If the temperature exceeds 175°C (typical), thermal shutdown occurs.

When entering thermal shutdown, the device:

1. Turns off the low-side and high-side MOSFETs;
2. Pulls SS/TRK and PGOOD low;
3. Initiates a soft-start sequence when the die temperature decreases by the thermal shutdown hysteresis of 20°C (typical).

9.1.1 Design and Implementation

To expedite the process of designing of a LM25145-based regulator for a given application, please use the LM25145 Quickstart Calculator available as a free download, as well as numerous LM25145 reference designs populated in TI Designs™ reference design library, or the designs provided in Typical Applications. The LM25145 is also WEBENCH® Designer enabled.

9.1.2 Power Train Components

Comprehensive knowledge and understanding of the power train components are key to successfully completing a synchronous buck regulator design.

9.1.2.1 Inductor

For most applications, choose an inductance such that the inductor ripple current, ΔI_L, is between 30% and 40% of the maximum DC output current at nominal input voltage. Choose the inductance using Equation 7 based on a peak inductor current given by Equation 8.

Equation 7.

Equation 8.

Check the inductor datasheet to ensure that the saturation current of the inductor is well above the peak inductor current of a particular design. Ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can then concentrate on copper loss and preventing saturation. Low inductor core loss is evidenced by reduced no-load input current and higher light-load efficiency. However, ferrite core materials exhibit a hard saturation characteristic and the inductance collapses abruptly when the saturation current is exceeded. This results in an abrupt increase in inductor ripple current, higher output voltage ripple, not to mention reduced efficiency and compromised reliability. Note that the saturation current of an inductor generally deceases as its core temperature increases. Of course, accurate overcurrent protection is key to avoiding inductor saturation.

9.1.2.2 Output Capacitors

Ordinarily, the output capacitor energy store of the regulator combined with the control loop response are prescribed to maintain the integrity of the output voltage within the dynamic (transient) tolerance specifications. The usual boundaries restricting the output capacitor in power management applications are driven by finite available PCB area, component footprint and profile, and cost. The capacitor parasitics—equivalent series resistance (ESR) and equivalent series inductance (ESL)—take greater precedence in shaping the load transient response of the regulator as the load step amplitude and slew rate increase.

The output capacitor, C_OUT, filters the inductor ripple current and provides a reservoir of charge for step-load transient events. Typically, ceramic capacitors provide extremely low ESR to reduce the output voltage ripple and noise spikes, while tantalum and electrolytic capacitors provide a large bulk capacitance in a relatively compact footprint for transient loading events.

Based on the static specification of peak-to-peak output voltage ripple denoted by ΔV_OUT, choose an output capacitance that is larger than that given by Equation 9.

Equation 9.

Figure 42 conceptually illustrates the relevant current waveforms during both load step-up and step-down transitions. As shown, the large-signal slew rate of the inductor current is limited as the inductor current ramps to match the new load-current level following a load transient. This slew-rate limiting exacerbates the deficit of charge in the output capacitor, which must be replenished as rapidly as possible during and after the load step-up transient. Similarly, during and after a load step-down transient, the slew rate limiting of the inductor current adds to the surplus of charge in the output capacitor that must be depleted as quickly as possible.

Figure 42. Load Transient Response Representation Showing C_OUT Charge Surplus or Deficit

In a typical regulator application of 24-V input to low output voltage (for example, 5 V), it should be recognized that the load-off transient represents worst-case. In that case, the steady-state duty cycle is approximately 10% and the large-signal inductor current slew rate when the duty cycle collapses to zero is approximately –V_OUT/L. Compared to a load-on transient, the inductor current takes much longer to transition to the required level. The surplus of charge in the output capacitor causes the output voltage to significantly overshoot. In fact, to deplete this excess charge from the output capacitor as quickly as possible, the inductor current must ramp below its nominal level following the load step. In this scenario, a large output capacitance can be advantageously employed to absorb the excess charge and limit the voltage overshoot.

To meet the dynamic specification of output voltage overshoot during such a load-off transient (denoted as ΔV_OVERSHOOT with step reduction in output current given by ΔI_OUT), the output capacitance should be larger than

Equation 10.

The ESR of a capacitor is provided in the manufacturer’s data sheet either explicitly as a specification or implicitly in the impedance vs. frequency curve. Depending on type, size and construction, electrolytic capacitors have significant ESR, 5 mΩ and above, and relatively large ESL, 5 nH to 20 nH. PCB traces contribute some parasitic resistance and inductance as well. Ceramic output capacitors, on the other hand, have low ESR and ESL contributions at the switching frequency, and the capacitive impedance component dominates. However, depending on package and voltage rating of the ceramic capacitor, the effective capacitance can drop quite significantly with applied DC voltage and operating temperature.

Ignoring the ESR term in Equation 9 gives a quick estimation of the minimum ceramic capacitance necessary to meet the output ripple specification. One to four 47-µF, 10-V, X7R capacitors in 1206 or 1210 footprint is a common choice. Use Equation 10 to determine if additional capacitance is necessary to meet the load-off transient overshoot specification.

A composite implementation of ceramic and electrolytic capacitors highlights the rationale for paralleling capacitors of dissimilar chemistries yet complementary performance. The frequency response of each capacitor is accretive in that each capacitor provides desirable performance over a certain portion of the frequency range. While the ceramic provides excellent mid- and high-frequency decoupling characteristics with its low ESR and ESL to minimize the switching frequency output ripple, the electrolytic device with its large bulk capacitance provides low-frequency energy storage to cope with load transient demands.

9.1.2.3 Input Capacitors

Input capacitors are necessary to limit the input ripple voltage to the buck power stage due to switching-frequency AC currents. TI recommends using X5R or X7R dielectric ceramic capacitors to provide low impedance and high RMS current rating over a wide temperature range. To minimize the parasitic inductance in the switching loop, position the input capacitors as close as possible to the drain of the high-side MOSFET and the source of the low-side MOSFET. The input capacitor RMS current is given by Equation 11.

Equation 11.

The highest input capacitor RMS current occurs at D = 0.5, at which point the RMS current rating of the capacitors should be greater than half the output current.

Ideally, the DC component of input current is provided by the input voltage source and the AC component by the input filter capacitors. Neglecting inductor ripple current, the input capacitors source current of amplitude (I_OUT − I_IN) during the D interval and sinks I_IN during the 1−D interval. Thus, the input capacitors conduct a square-wave current of peak-to-peak amplitude equal to the output current. It follows that the resultant capacitive component of AC ripple voltage is a triangular waveform. Together with the ESR-related ripple component, the peak-to-peak ripple voltage amplitude is given by Equation 12.

Equation 12.

The input capacitance required for a particular load current, based on an input voltage ripple specification of ΔV_IN, is given by Equation 13.

Equation 13.

Low-ESR ceramic capacitors can be placed in parallel with higher valued bulk capacitance to provide optimized input filtering for the regulator and damping to mitigate the effects of input parasitic inductance resonating with high-Q ceramics. One bulk capacitor of sufficiently high current rating and two or three 2.2-μF 100-V X7R ceramic decoupling capacitors are usually sufficient. Select the input bulk capacitor based on its ripple current rating and operating temperature.

9.1.2.4 Power MOSFETs

The choice of power MOSFETs has significant impact on DC-DC regulator performance. A MOSFET with low on-state resistance, R_DS(on), reduces conduction loss, whereas low parasitic capacitances enable faster transition times and reduced switching loss. Normally, the lower the R_DS(on) of a MOSFET, the higher the gate charge and output charge (Q_G and Q_OSS respectively), and vice versa. As a result, the product R_DS(on) × Q_G is commonly specified as a MOSFET figure-of-merit. Low thermal resistance ensures that the MOSFET power dissipation does not result in excessive MOSFET die temperature.

The main parameters affecting power MOSFET selection in an LM25145 application are as follows:

• R_DS(on) at V_GS = 7.5 V;
• Drain-source voltage rating, BV_DSS, typically 30 V, 40 V or 60 V, depending on maximum input voltage;
• Gate charge parameters at V_GS = 7.5 V;
• Output charge, Q_OSS, at the relevant input voltage;
• Body diode reverse recovery charge, Q_RR;
• Gate threshold voltage, V_GS(th), derived from the plateau in the Q_G vs. V_GS plot in the MOSFET data sheet. With a MOSFET Miller plateau voltage typically in the range of 3 V to 5 V, the 7.5-V gate drive amplitude of the LM25145 provides an adequately-enhanced MOSFET when on and a margin against Cdv/dt shoot-through when off.

The MOSFET-related power losses are summarized by the equations presented in Table 2, where suffixes 1 and 2 represent high-side and low-side MOSFET parameters, respectively. While the influence of inductor ripple current is considered, second-order loss modes, such as those related to parasitic inductances and SW node ringing, are not included. Consult the LM25145 Quickstart Calculator to assist with power loss calculations.

Table 2. Buck Regulator MOSFET Power Losses

POWER LOSS MODE	HIGH-SIDE MOSFET	LOW-SIDE MOSFET
MOSFET Conduction(2)(3)
MOSFET Switching		Negligible
MOSFET Gate Drive(1)
MOSFET Output Charge(4)
Body Diode Conduction	N/A
Body Diode Reverse Recovery(5)

(1) Gate drive loss is apportioned based on the internal gate resistance of the MOSFET, externally-added series gate resistance and the relevant driver resistance of the LM25145.

(2) MOSFET R_DS(on) has a positive temperature coefficient of approximately 4500 ppm/°C. The MOSFET junction temperature, T_J, and its rise over ambient temperature is dependent upon the device total power dissipation and its thermal impedance.

(3) D' = 1–D is the duty cycle complement.

(4) MOSFET output capacitances, C_oss1 and C_oss2, are highly non-linear with voltage. These capacitances are charged losslessly by the inductor current at high-side MOSFET turn-off. During turn-on, however, a current flows from the input to charge the output capacitance of the low-side MOSFET. E_oss1, the energy of C_oss1, is dissipated at turn-on, but this is offset by the stored energy E_oss2 on C_oss2.

(5) MOSFET body diode reverse recovery charge, Q_RR, depends on many parameters, particularly forward current, current transition speed and temperature.

The high-side (control) MOSFET carries the inductor current during the PWM on-time (or D interval) and typically incurs most of the switching losses. It is therefore imperative to choose a high-side MOSFET that balances conduction and switching loss contributions. The total power dissipation in the high-side MOSFET is the sum of the losses due to conduction, switching (voltage-current overlap), output charge, and typically two-thirds of the net loss attributed to body diode reverse recovery.

The low-side (synchronous) MOSFET carries the inductor current when the high-side MOSFET is off (or 1–D interval). The low-side MOSFET switching loss is negligible as it is switched at zero voltage – current just commutates from the channel to the body diode or vice versa during the transition dead-times. The LM25145, with its adaptive gate drive timing, minimizes body diode conduction losses when both MOSFETs are off. Such losses scale directly with switching frequency.

In high step-down ratio applications, the low-side MOSFET carries the current for a large portion of the switching period. Therefore, to attain high efficiency, it is critical to optimize the low-side MOSFET for low R_DS(on). In cases where the conduction loss is too high or the target R_DS(on) is lower than available in a single MOSFET, connect two low-side MOSFETs in parallel. The total power dissipation of the low-side MOSFET is the sum of the losses due to channel conduction, body diode conduction, and typically one-third of the net loss attributed to body diode reverse recovery. The LM25145 is well suited to drive TI's comprehensive portfolio of NexFET™ power MOSFETs.

9.1.3 Control Loop Compensation

The poles and zeros inherent to the power stage and compensator are respectively illustrated by red and blue dashed rings in the schematic embedded in Table 3.

The compensation network typically employed with voltage-mode control is a Type-III circuit with three poles and two zeros. One compensator pole is located at the origin to realize high DC gain. The normal compensation strategy uses two compensator zeros to counteract the LC double pole, one compensator pole located to nullify the output capacitor ESR zero, with the remaining compensator pole located at one-half switching frequency to attenuate high frequency noise. The resistor divider network to FB determines the desired output voltage. Note that the lower feedback resistor, R_FB2, has no impact on the control loop from an AC standpoint because the FB node is the input to an error amplifier and is effectively at AC ground. Hence, the control loop is designed irrespective of output voltage level. The proviso here is the necessary output capacitance derating with bias voltage and temperature.

Table 3. Buck Regulator Poles and Zeros⁽¹⁾⁽²⁾

POWER STAGE POLES	POWER STAGE ZEROS	COMPENSATOR POLES	COMPENSATOR ZEROS

(1) R_ESR represents the ESR of the output capacitor C_OUT.

(2) R_DAMP = D · R_{DS(on)high-side} + (1–D) · R_{DS(on) low-side} + R_DCR, shown as a lumped element in the schematic, represents the effective series damping resistance.

The small-signal open-loop response of a buck regulator is the product of modulator, power train and compensator transfer functions. The power stage transfer function can be represented as a complex pole pair associated with the output LC filter and a zero related to the ESR of the output capacitor. The DC (and low frequency) gain of the modulator and power stage is V_IN/V_RAMP. The gain from COMP to the average voltage at the input of the LC filter is held essentially constant by the PWM line feedforward feature of the LM25145 (15 V/V or 23.5 dB).

Complete expressions for small-signal frequency analysis are presented in Table 4. The transfer functions are denoted in normalized form. While the loop gain is of primary importance, a regulator is not specified directly by its loop gain but by its performance related characteristics, namely closed-loop output impedance and audio susceptibility.

Table 4. Buck Regulator Small-Signal Analysis

TRANSFER FUNCTION	EXPRESSION
Open-loop transfer function
Duty-cycle-to-output transfer function
Compensator transfer function(1)
Modulator transfer function

(1) K_mid = R_C1/R_FB1 is the mid-band gain of the compensator. By expressing one of the compensator zeros in inverted zero format, the mid-band gain is denoted explicitly.

An illustration of the open-loop response gain and phase is given in Figure 43. The poles and zeros of the system are marked with x and o symbols, respectively, and a + symbol indicates the crossover frequency. When plotted on a log (dB) scale, the open-loop gain is effectively the sum of the individual gain components from the modulator, power stage, and compensator (see Figure 44). The open-loop response of the system is measured experimentally by breaking the loop, injecting a variable-frequency oscillator signal and recording the ensuing frequency response using a network analyzer setup.

Figure 43. Typical Buck Regulator Loop Gain and Phase With Voltage-Mode Control

If the pole located at ω_p1 cancels the zero located at ω_ESR and the pole at ω_p2 is located well above crossover, the expression for the loop gain, T_v(s) in Table 4, can be manipulated to yield the simplified expression given in Equation 14.

Equation 14.

Essentially, a multi-order system is reduced to a single-order approximation by judicious choice of compensator components. A simple solution for the crossover frequency, denoted as f_c in Figure 43, with Type-III voltage-mode compensation is derived as shown in Equation 15 and Equation 16.

Equation 15.

Equation 16.

Figure 44. Buck Regulator Constituent Gain Components

The loop crossover frequency is usually selected between one-tenth to one-fifth of switching frequency. Inserting an appropriate crossover frequency into Equation 15 gives a target for the mid-band gain of the compensator, K_mid. Given an initial value for R_FB1, R_FB2 is then selected based on the desired output voltage. Values for R_C1, R_C2, C_C1, C_C2 and C_C3 are calculated from the design expressions listed in Table 5, with the premise that the compensator poles and zeros are set as follows: ω_z1 = 0.5·ω_o, ω_z2 = ω_o, ω_p1 = ω_ESR, ω_p2 = ω_SW/2.

Table 5. Compensation Component Selection

RESISTORS	CAPACITORS

Referring to the bode plot in Figure 43, the phase margin, indicated as φ_M, is the difference between the loop phase and –180° at crossover. A target of 50° to 70° for this parameter is considered ideal. Additional phase boost is dialed in by locating the compensator zeros at a frequency lower than the LC double pole (hence why C_C1 is scaled by a factor of 2 above). This helps mitigate the phase dip associated with the LC filter, particularly at light loads when the Q-factor is higher and the phase dip becomes especially prominent. The ramification of low phase in the frequency domain is an under-damped transient response in the time domain.

The power supply designer now has all the necessary expressions to optimally position the loop crossover frequency while maintaining adequate phase margin over the required line, load and temperature operating ranges. The LM25145 Quickstart Calculator is available to expedite these calculations and to adjust the bode plot as needed.

9.1.4 EMI Filter Design

Switching regulators exhibit negative input impedance, which is lowest at the minimum input voltage. An underdamped LC filter exhibits a high output impedance at the resonant frequency of the filter. For stability, the filter output impedance must be less than the absolute value of the converter input impedance.

Equation 17.

The EMI filter design steps are as follows:

• Calculate the required attenuation of the EMI filter at the switching frequency, where C_IN represents the existing capacitance at the input of the switching converter;
• Input filter inductor L_IN is usually selected between 1 μH and 10 μH, but it can be lower to reduce losses in a high current design;
• Calculate input filter capacitor C_F.

Figure 45. Buck Regulator With π-Stage EMI Filter

By calculating the first harmonic current from the Fourier series of the input current waveform and multiplying it by the input impedance (the impedance is defined by the existing input capacitor C_IN), a formula is derived to obtain the required attenuation as shown by Equation 18.

Equation 18.

V_MAX is the allowed dBμV noise level for the applicable EMI standard, for example EN55022 Class B. C_IN is the existing input capacitance of the buck regulator, D_MAX is the maximum duty cycle, and I_PEAK is the peak inductor current. For filter design purposes, the current at the input can be modeled as a square-wave. Determine the EMI filter capacitance C_F from Equation 19.

Equation 19.

Adding an input filter to a switching regulator modifies the control-to-output transfer function. The output impedance of the filter must be sufficiently small such that the input filter does not significantly affect the loop gain of the buck converter. The impedance peaks at the filter resonant frequency. The resonant frequency of the filter is given by Equation 20.

Equation 20.

The purpose of R_D is to reduce the peak output impedance of the filter at the resonant frequency. Capacitor C_D blocks the DC component of the input voltage to avoid excessive power dissipation in R_D. Capacitor C_D should have lower impedance than R_D at the resonant frequency with a capacitance value greater than that of the input capacitor C_IN. This prevents C_IN from interfering with the cutoff frequency of the main filter. Added damping is needed when the output impedance of the filter is high at the resonant frequency (Q of filter formed by L_IN and C_IN is too high). An electrolytic capacitor C_D can be used for damping with a value given by Equation 21.

Equation 21.

Select the damping resistor R_D using Equation 22.

Equation 22.

9.2.1 Design 1 – 20-A High-Efficiency Synchronous Buck Regulator for Telecom Power Applications

Figure 46 shows the schematic diagram of a 5-V, 20-A buck regulator with a switching frequency of 500 kHz. In this example, the target full-load efficiency is 94% at a nominal input voltage of 24 V that ranges from 6.5 V to as high as 32 V. The switching frequency is set by means of a synchronization input signal at 500 kHz, and the free-running switching frequency (in the event that the synchronization signal is removed) is set at 450 kHz by resistor R_RT. In terms of control loop performance, the target loop crossover frequency is 70 kHz with a phase margin greater than 50°. The output voltage soft-start time is 4 ms.

Figure 46. Application Circuit #1 With LM25145 24-V to 5-V, 20-A Buck Regulator at 500 kHz

9.2.1.4 Application Curves

SYNCIN tied to VCC

Figure 47. Efficiency and Power Loss vs I_OUT and V_IN, CCM

VIN step to 24 V

0.25-Ω Load

Figure 49. Start-Up, 20-A Resistive Load

VIN = 24 V

0.25-Ω Load

Figure 51. ENABLE ON, 20-A Resistive Load

VIN = 24 V

Figure 53. Load Transient Response, 10 A to 20 A to 10 A

VIN = 24 V

IOUT = 0 A

Figure 55. SYNCOUT and SW Node Voltages

SYNCIN tied to GND

Figure 48. Efficiency and Power Loss vs I_OUT and V_IN, DCM

VIN 24 V to 6 V

0.25-Ω Load

Figure 50. Shutdown Through Input UVLO, 20-A Resistive Load

VIN = 24 V

0.25-Ω Load

Figure 52. ENABLE OFF, 20-A Resistive Load

VIN = 24 V

Figure 54. Load Transient Response, 0 A to 20 A to 0 A

VIN = 24 V

IOUT = 20 A

Figure 56. SW Node Voltage

9.2.2 Design 2 – High Density, 12-V, 8-A Rail With LDO Low-Noise Auxiliary Output for Industrial Applications

Figure 57 shows the schematic diagram of a 425-kHz, 12-V output, 8-A synchronous buck regulator intended for RF power applications.

An auxiliary 10-V, 800-mA rail to power noise-sensitive circuits is available using the LP38798 ultra-low noise LDO as a post-regulator. The internal pullup of the EN pin of the LP38798 facilitates direct connection to the PGOOD of the LM25145 for sequential start-up control.

Figure 57. Application Circuit #2 With LM25145 24-V to 12-V Synchronous Buck Regulator at 425 kHz

9.2.2.2 Detailed Design Procedure

A high power density, high-efficiency regulator solution is realized by using TI NexFET™ Power MOSFETs, such as CSD18543Q3A (60-V, 8.5-mΩ MOSFET in a SON 3.3-mm × 3.3-mm package), together with a low-DCR inductor and all-ceramic capacitor design. The design occupies 15 mm × 15 mm on a single-sided PCB. The overcurrent (OC) setpoint in this design is set at 11 A based on the resistor R_ILIM and the 8.5-mΩ R_DS(on) of the low-side MOSFET (typical at T_J = 25°C and V_GS = 7.5 V). Connecting VCC to either V_OUT1 or V_OUT2 using a series diode reduces bias power dissipation and improves efficiency, especially at light loads.

The selected buck converter powertrain components are cited in Table 9, including power MOSFETs, buck inductor, input and output capacitors, and ICs. Using the LM25145 Quickstart Calculator, compensation components are selected based on a target loop crossover frequency of 70 kHz and phase margin greater than 55°. The output voltage soft-start time is 4 ms based on the selected soft-start capacitance, C_SS, of 47 nF.

Table 9. List of Materials for Design 2

REFERENCE DESIGNATOR	QTY	SPECIFICATION	MANUFACTURER	PART NUMBER
CIN	4	10 µF, 50 V, X7R, 1210, ceramic	TDK	C3225X7R1H106M
			Murata	GRM32ER71H106KA12L
			AVX	12105C106KAT2A
COUT	4	22 µF, 25 V, X7R, 1210, ceramic	Murata	GRM32ER71E226KE15L
			Taiyo Yuden	TMK325B7226MM-TR
			TDK	C3225X7R1E226M
LF	1	5.6 µH, 17 mΩ, 18 A, 10.85 × 10 × 3.8 mm	Cyntec	CMLS104T-5R6MS
		5.6 µH, 20 mΩ, 14 A, 10.85 × 10 × 3.8 mm	Delta	MPT1040-5R6H1
		5.6 µH, 16 mΩ, 12 A, 10.7 × 10 × 4 mm	Bourns	SRP1040-5R6M
		5.6 µH, 19.3 mΩ, 16 A, 11 × 10 × 4 mm	Laird	MGV10045R6M-10
		6.8 µH, 17.5 mΩ, 14 A, 11 × 10 × 3.8 mm	Würth Electronik	WE-LHMI 74437368068
		6.8 µH, 17.9 mΩ, 25 A, 10.5 × 10 × 4 mm	TDK	SPM10040VT-6R8M-D
		6.8 µH, 18.3 mΩ, 12.1 A, 10.7 × 10 × 4 mm	Panasonic	ETQP4M6R8KVC
Q1, Q2	2	60 V, 8 mΩ, MOSFET, SON 3 × 3	Texas Instruments	CSD18543Q3A
U1	1	Wide VIN synchronous buck controller	Texas Instruments	LM25145RGYR
U2	1	Ultra-low noise and high-PSRR LDO for RF and analog circuits, 4-mm × 4-mm 12-pin WSON	Texas Instruments	LP38798SD-ADJ

If needed, a 2.2-Ω resistor can be added in series with C_BST is used to slow the turn-on transition of the high-side MOSFET, reducing the spike amplitude and ringing of the SW node voltage and minimizing the possibility of Cdv/dt-induced shoot-through of the low-side MOSFET. If needed, place an RC snubber (for example, 2.2 Ω and 100 pF) close to the drain (SW node) and source (PGND) terminals of the low-side MOSFET to further attenuate any SW node voltage overshoot and/or ringing. Please refer to the application note Reduce Buck Converter EMI and Voltage Stress by Minimizing Inductive Parasitics for more detail.

9.2.2.2.1 Application Curves

Figure 58. Efficiency vs I_OUT and V_IN

VIN step to 24 V

1.5-Ω Load

Figure 60. Start-Up, 8-A Resistive Load

VIN = 24 V

1.5-Ω Load

Figure 62. ENABLE ON, 8-A Resistive Load

VIN = 24 V

IOUT = 0 A

Figure 64. Pre-Biased Start-Up

VIN = 24 V

Figure 66. Load Transient Response, 4 A to 8 A to 4 A

IOUT = 8 A

Figure 68. Line Transient Response, 18 V to 36 V

VIN = 24 V

IOUT = 4 A

Figure 59. SYNCOUT and SW Node Voltages

1.5-Ω Load

Figure 61. Shutdown Through Input UVLO, 8-A Resistive Load

VIN = 24 V

1.5-Ω Load

Figure 63. ENABLE OFF, 8-A Resistive Load

VIN = 24 V

IOUT = 0 A

Figure 65. SW Node and VOUT Ripple

VIN = 24 V

Figure 67. Load Transient Response, 0.8 A to 8 A to 0.8 A

IOUT = 8 A

Figure 69. Line Transient Response, 36 V to 18 V

9.2.3 Design 3 – Powering a Multicore DSP From a 24-V Rail

	For technical solutions, industry trends, and insights for designing and managing power supplies, please refer to TI's Power House blog series.

Figure 70 shows the schematic diagram of a 10-A synchronous buck regulator for a DSP core voltage supply.

Figure 70. Application Circuit #3 With LM25145 DSP Core Voltage Supply

9.2.3.3 Application Curves

VOUT = 1.1 V

VAUX = 8 V

Figure 71. Efficiency vs I_OUT and V_IN

VIN = 24 V

0.11-Ω Load

Figure 73. ENABLE ON and OFF, 10-A Resistive Load

VIN step to 24 V

0.11-Ω Load

Figure 72. Start-Up, 10-A Resistive Load

VIN = 24 V

Figure 74. Load Transient Response, 0 A to 10 A to 0 A