ZHCSG62A March 2017 – May 2017 TPD2S703-Q1
PRODUCTION DATA.
MIN | TYP | MAX | UNIT | |||
---|---|---|---|---|---|---|
VPWR | 5-V DC supply voltage for internal circuitry | 4.5 | 7 | V | ||
VREF | Mode 0. Voltage range for VREF pin (for setting OVP threshold) | 3 | 3.6 | V | ||
VREF | Mode 1. Voltage range for VREF pin (for setting OVP threshold) | 0.63 | 3.8 | V | ||
VD+, VD– | Voltage range from connector-side USB data lines | 0 | 3.6 | V | ||
D+, D– | Voltage range for internal USB data lines | 0 | 3.6 | V | ||
VEN | Voltage range for enable | 0 | 7 | V | ||
VFLT | Voltage range for FLT | 0 | 7 | V | ||
IFLT | Current into open drain FLT pin FET | 0 | 3 | mA | ||
CVPWR | VPWR capacitance(1) | VPWR pin | 1 | 10 | µF | |
CVREF | VREF capacitance | VREF pin | 0.3 | 1 | 3 | µF |
CMODE | Allowed parasitic capacitance on mode pin from PCB and mode 1 external resistors | 20 | pF | |||
RMODE_0 | Resistance to GND to set to mode 0 | 2 | 2.6 | kΩ | ||
RMODE_1 | Resistance to GND to set to mode 1 (calculate parallel combination of RTOP and RBOT) | 14 | 20 | kΩ |