LMG5200 80V、10A GaN 半桥功率级
- ZHCSFT3D March 2015 – March 2017 LMG5200
  
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LMG5200 80V、10A GaN 半桥功率级

本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

集成 15mΩ GaN FET 和驱动器
80V 连续电压，100V 脉冲电压额定值
封装经过优化，可实现简单的 PCB 布局，无需考虑底层填料、爬电和余隙要求
超低共源电感可确保实现高压摆率开关，同时在硬开关拓扑中不会造成过度振铃
非常适合隔离式和非隔离式应用
栅极驱动器支持高达 10MHz 的开关频率
内部自举电源电压钳位可防止 GaN FET 过驱
电源轨欠压锁定保护
优异的传播延迟（典型值为 29.5ns）和匹配（典型值为 2ns）
低功耗

2 应用

宽 V_IN 数兆赫兹同步降压转换器
D 类音频放大器
适用于电信、工业和企业计算的 48V 负载点 (POL) 转换器
高功率密度单相和三相电机驱动

3 说明

LMG5200 器件集成了 80V、10A 驱动器和 GaN 半桥功率级，采用增强模式氮化镓 (GaN) FET 提供了一套集成功率级解决方案。该器件包含两个 80V GaN FET，它们由采用半桥配置的同一高频 GaN FET 驱动器提供驱动。

GaN FET 在功率转换方面的优势显著，因为其反向恢复电荷几乎为零，输入电容 C_ISS 也非常小。所有器件均安装在一个完全无键合线的封装平台上，尽可能减少了封装寄生元件数。LMG5200 器件采用 6mm × 8mm × 2mm 无铅封装，可轻松安装在 PCB 上。

该器件的输入与 TTL 逻辑兼容，无论 VCC 电压如何，都能够承受高达 12V 的输入电压。专有的自举电压钳位技术确保了增强模式 GaN FET 的栅极电压处于安全的工作范围内。

该器件配有用户友好型接口且更为出色，进一步提升了分立式 GaN FET 的优势。对于具有高频、高效操作及小尺寸要求的应用而言，该器件堪称理想的解决方案。与 TPS53632G 控制器搭配使用时，LMG5200 能够直接将 48V 电压转换为负载点电压 (0.5-1.5V)。

器件信息⁽¹⁾

器件型号	封装	封装尺寸（标称值）
LMG5200	QFM (9)	6.00mm × 8.00mm

如需了解所有可用封装，请参阅产品说明书末尾的可订购产品附录。已更正中的印刷错误

简化框图

4 修订历史记录

Changes from C Revision (December 2016) to D Revision

通用编辑全局编写和 SDS 更新Go
Changed Thermal Information tableGo

Changes from B Revision (January 2016) to C Revision

Changed “GaN 技术预览”至“量产数据”Go
Added Device Functional Modes Section Go
Added Typical Application Section Go
Updated Power Supply Recommendations Section Go
Added 链接至“开发支持”部分Go

Changes from A Revision (March 2015) to B Revision

Changed part number typographical error in Figure 14Go

Changes from * Revision (March 2015) to A Revision

简化框图Go
Corrected typographical error in Figure 5Go
Corrected typographical error in Figure 10Go
Corrected typographical error in Figure 11Go

5 Pin Configuration and Functions

MOF Package

9-Pin QFM

Top View

Pin Functions

PIN		I/O⁽¹⁾	DESCRIPTION
NAME	NO.	I/O⁽¹⁾	DESCRIPTION
AGND	7	G	Analog ground. Ground of driver device.
HB	2	P	High-side gate driver bootstrap rail.
HI	4	I	High-side gate driver control input
HS	3	P	High-side GaN FET source connection
LI	5	I	Low-side driver control input
PGND	9	G	Power ground. Low-side GaN FET source. Electrically shorted to AGND pin.
SW	8	P	Switching node. Electrically shorted to HS pin. Ensure low capacitance at this node on PCB.
VCC	6	P	5-V positive gate drive supply
VIN	1	P	Input voltage pin. Electrically connected to high-side GaN FET drain.

(1) I = Input, O = Output, G = Ground, P = Power

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER	MIN	MAX	UNIT
VIN to PGND	0	80	V
VIN to PGND (pulsed, 100-ms maximum duration)⁽²⁾		100	V
HB to AGND	–0.3	86	V
HS to AGND	–5	80	V
HI to AGND	–0.3	12	V
LI to AGND	–0.3	12	V
VCC to AGND	–0.3	6	V
HB to HS	–0.3	6	V
HB to VCC	0	80	V
SW to PGND	–5	80	V
IOUT from SW pin		10	A
Junction temperature, T_J	–40	125	°C
Storage temperature, T_stg	–40	150	°C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) Device can withstand 1000 pulses up to 100 V of 100-ms duration and less than 1% duty cycle over its lifetime.

6.2 ESD Ratings

			VALUE	UNIT
V_(ESD)	Electrostatic discharge	Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001⁽¹⁾	±1000	V
V_(ESD)	Electrostatic discharge	Charged-device model (CDM), per JEDEC specification JESD22-C101⁽²⁾	±500	V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)

	MIN	NOM	MAX	UNIT
VCC	4.75	5	5.25	V
LI or HI Input	0		12	V
VIN	0		80	V
HS, SW	–5		80	V
HB	V_HS + 4		V_HS + 5.25	V
HS, SW slew rate⁽¹⁾			50	V/ns
Junction temperature, T_J	–40		125	°C

(1) This parameter is ensured by design. Not tested in production.

6.4 Thermal Information

THERMAL METRIC ⁽¹⁾ ⁽²⁾		LMG5200	UNIT
		MOF (QFM)
		9 PINS
R _θJA	Junction-to-ambient thermal resistance	35	°C/W
R _θJC(top)	Junction-to-case (top) thermal resistance	18	°C/W
R _θJB	Junction-to-board thermal resistance	16	°C/W
ψ _JT	Junction-to-top characterization parameter	1.8	°C/W
ψ _JB	Junction-to-board characterization parameter	16	°C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report.

(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator .

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)⁽¹⁾

PARAMETER		TEST CONDITIONS	MIN	TYP	MAX	UNIT
SUPPLY CURRENTS
I_CC	VCC quiescent current	LI = HI = 0 V, VCC = 5 V, HB-HS = 4.6 V		0.08	0.125	mA
I_CCO	Total VCC operating current	f = 500 kHz		3	5	mA
I_HB	HB quiescent current	LI = HI = 0 V, VCC = 5 V, HB-HS = 4.6 V		0.09	0.15	mA
I_HBO	HB operating current	f = 500 kHz, 50% Duty cycle, V_DD = 5 V		1.5	2.5	mA
INPUT PINS
V_IH	High-level input voltage threshold	Rising edge	1.87	2.06	2.22	V
V_IL	Low-level input voltage threshold	Falling edge	1.48	1.66	1.76	V
V_HYS	Hysteresis between rising and falling threshold			400		mV
R_I	Input pulldown resistance		100	200	300	kΩ
UNDERVOLTAGE PROTECTION
V_CCR	V_CC Rising edge threshold	Rising	3.2	3.8	4.5	V
V_CC(hyst)	V_CC UVLO threshold hysteresis			200		mV
V_HBR	HB Rising edge threshold	Rising	2.5	3.2	3.9	V
V_HB(hyst)	HB UVLO threshold hysteresis			200		mV
BOOTSTRAP DIODE
V_DL	Low-current forward voltage	I_VDD-HB = 100 µA		0.45	0.65	V
V_DH	High current forward voltage	I_VDD-HB = 100 mA		0.9	1.0	V
R_D	Dynamic resistance	I_VDD-HB = 100 mA		1.85	2.8	Ω
	HB-HS clamp	Regulation Voltage	4.65	5	5.2	V
t_BS	Bootstrap diode reverse recovery time	I_F = 100 mA, IR = 100 mA		40		ns
Q_RR	Bootstrap diode reverse recovery charge	V_VIN = 50 V		2		nC
POWER STAGE
R_DS(ON)HS	High-side GaN FET on-resistance	LI = 0 V, HI = VCC=5 V, HB-HS = 5 V, VIN-SW = 10 A, T_J = 25℃		15	20	mΩ
R_DS(ON)LS	Low-side GaN FET on-resistance	LI = VCC = 5V, HI = 0 V, HB-HS = 5 V, SW-PGND = 10 A, T_J = 25℃		15	20	mΩ
V_SD	GaN 3rd quadrant conduction drop	I_SD = 500 mA, V_IN floating, V_VCC = 5 V, HI = LI = 0 V		2		V
I_L-VIN-SW	Leakage from VIN to SW when the high-side GaN FET and low-side GaN FET are off	VIN = 80 V, HI = LI = 0 V, V_VCC = 5 V, T_J= 25℃		25	150	µA
I_L-SW-GND	Leakage from SW to GND when the high-side GaN FET and low-side GaN FET are off	SW = 80 V, HI = LI = 0 V, V_VCC = 5V, T_J = 25℃		25	150	µA
C_OSS	Output capacitance of high-side GaN FET and low-side GaN FET	V_DS=40 V, V_GS= 0V (HI = LI = 0 V)		266		pF
Q_G	Total gate charge	V_DS=40 V, I_D= 10A, V_GS= 5 V		3.8		nC
Q_OSS	Output charge	V_DS=40 V, I_D= 10 A		21		nC
Q_RR	Source-to-drain reverse recovery charge	Not including internal driver bootstrap diode		0		nC
t_HIPLH	Propagation delay: HI rising⁽²⁾	LI = 0 V, VCC = 5 V, HB-HS = 5 V, VIN = 30 V		29.5	50	ns
t_HIPHL	Propagation delay: HI falling⁽²⁾	LI = 0 V, VCC = 5 V, HB-HS = 5 V, VIN = 30 V		29.5	50	ns
t_LPLH	Propagation delay: LI rising⁽²⁾	HI = 0 V, VCC = 5 V, HB-HS = 5 V, VIN = 30 V		29.5	50	ns
t_LPHL	Propagation delay: LI falling⁽²⁾	HI = 0 V, VCC = 5 V, HB-HS = 5 V, VIN = 30 V		29.5	50	ns
t_MON	Delay matching: LI high and HI low⁽²⁾			2	8	ns
t_MOFF	Delay matching: LI low and HI high⁽²⁾			2	8	ns
t_PW	Minimum input pulse width that changes the output			10		ns

(1) Parameters that show only a typical value are ensured by design and may not be tested in production.

(2) See Propagation Delay and Mismatch Measurement.

6.6 Typical Characteristics

All the curves are based on measurements made on a PCB design with dimensions of 3.2 inches (W) × 2.7 inches (L) × 0.062 inch (T) and 4 layers of 2 oz copper.

The safe operating area (SOA) curves displays the temperature boundaries within an operating system by incorporating the thermal resistance and system power loss. A buck converter is used for measuring the SOA. Figure 2 outlines the temperature and airflow conditions required for a given load current. The area under the curve dictates the SOA for different airflow conditions.

V_DD = 5 V

Figure 1. V_DD Supply Current vs Switching Frequency

GaN third quadrant conduction.

Figure 3. Source-to-Drain Current vs Source-to-Drain Voltage

V_IN = 48 V

V_OUT = 5 V

f_SW = 1 MHz

Figure 2. Safe Operating Area

Figure 4. GaN FET On-Resistance vs Junction Temperature

7 Parameter Measurement Information

7.1 Propagation Delay and Mismatch Measurement

Figure 5 shows the typical test setup used to measure the propagation mismatch. As the gate drives are not accessible, pullup and pulldown resistors in this test circuit are used to indicate when the low-side GaN FET turns ON and the high-side GaN FET turns OFF and vice versa to measure the t_MON and t_MOFF parameters. Resistance values used in this circuit for the pullup and pulldown resistors are in the order of 1 kΩ; the current sources used are 2 A.

Figure 6 through Figure 9 show propagation delay measurement waveforms. For turnon propagation delay measurements, the current sources are not used. For turnoff time measurements, the current sources are set to 2 A, and a voltage clamp limit is also set, referred to as VIN_(CLAMP). When measuring the high-side component turnoff delay, the current source across the high-side FET is turned on, the current source across the low-side FET is off, HI transitions from high-to-low, and output voltage transitions from V_IN to V_IN(CLAMP). Similarly, for low-side component turnoff propagation delay measurements, the high-side component current source is turned off, and the low-side component current source is turned on, LI transitions from high to low and the output transitions from GND potential to V_IN(CLAMP). The time between the transition of LI and the output change is the propagation delay time.