ZHCSFS0A December 2016 – June 2018 SN65DSI83-Q1
PRODUCTION DATA.
7 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
PLL_EN_STAT | Reserved | LVDS_CLK_RANGE | HS_CLK_SRC | ||||
R | R | R/W | R/W |
LEGEND: R/W = Read/Write; R = Read only; -n = value after reset |
Bit | Field | Type | Reset | Description |
---|---|---|---|---|
7 | PLL_EN_STAT | R | 0 | 0 – PLL not enabled (default)
1 – PLL enabled Note: After PLL_EN_STAT = 1, wait at least 3ms for PLL to lock. |
6-4 | Reserved | R | ||
3-1 | LVDS_CLK_RANGE | R/W | 101 | This field selects the frequency range of the LVDS output clock.
000 – 25 MHz ≤ LVDS_CLK < 37.5 MHz 001 – 37.5 MHz ≤ LVDS_CLK < 62.5 MHz 010 – 62.5 MHz ≤ LVDS_CLK < 87.5 MHz 011 – 87.5 MHz ≤ LVDS_CLK < 112.5 MHz 100 – 112.5 MHz ≤ LVDS_CLK < 137.5 MHz 101 – 137.5 MHz ≤ LVDS_CLK ≤ 154 MHz (default) 110 – Reserved 111 – Reserved |
0 | HS_CLK_SRC | R/W | 0 | 0 – LVDS pixel clock derived from input REFCLK (default)
1 – LVDS pixel clock derived from MIPI D-PHY channel A HS continuous clock |