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  • 具有单输入的UCC205204A/6A、5.7 kVRMS 隔离式双通道栅极驱动器

    • ZHCSFN1A November   2016  – January 2022 UCC20520

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  • 具有单输入的UCC205204A/6A、5.7 kVRMS 隔离式双通道栅极驱动器
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety-Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay and Pulse Width Distortion
    2. 7.2 Rising and Falling Time
    3. 7.3 PWM Input and Disable Response Time
    4. 7.4 Programable Dead Time
    5. 7.5 CMTI Testing
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in UCC20520
    4. 8.4 Device Functional Modes
      1. 8.4.1 Disable Pin
      2. 8.4.2 Programmable Dead Time (DT) Pin
        1. 8.4.2.1 Tying the DT Pin to VCC
        2. 8.4.2.2 DT Pin Left Open or Connected to a Programming Resistor between DT and GND Pins
        3. 8.4.2.3 39
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing PWM Input Filter
        2. 9.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 9.2.2.3 Gate Driver Output Resistor
        4. 9.2.2.4 Estimate Gate Driver Power Loss
        5. 9.2.2.5 Estimating Junction Temperature
        6. 9.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.6.1 Selecting a VCCI Capacitor
          2. 9.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 9.2.2.6.3 Select a VDDB Capacitor
        7. 9.2.2.7 Dead Time Setting Guidelines
        8. 9.2.2.8 Application Circuits with Output Stage Negative Bias
        9. 9.2.2.9 56
      3. 9.2.3 Application Curves
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
      1. 11.3.1 Certifications
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 重要声明
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DATA SHEET

具有单输入的UCC205204A/6A、5.7 kVRMS 隔离式双通道栅极驱动器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 单输入、双输出
  • 工作温度范围：–40 至125° C
  • 开关参数：
    • 19ns 典型传播延迟
    • 10ns 最小脉冲宽度
    • 5ns 最大延迟匹配
    • 6ns 最大脉宽失真
  • 共模瞬态抗扰度 (CMTI) 大于 100V/ns
  • 浪涌抗扰度高达 12.8kV
  • 隔离栅寿命大于 40 年
  • 4A 峰值拉电流、6A 峰值灌电流输出
  • TTL 和 CMOS 兼容输入
  • 3V 至 18V 输入 VCCI 范围，可与数字控制器和模拟控制器连接
  • 高达 25V 的 VDD 输出驱动电源
  • 可编程死区时间
  • 抑制短于 5ns 的输入脉冲和噪声瞬态
  • 快速禁用电源定序
  • 业界通用的宽体 SOIC-16 (DW) 封装
  • 安全相关及监管批准：
    • 符合 DIN V VDE V 0884-11:2017-01 标准的 8000VPK 隔离
    • 符合 UL 1577 标准且长达 1 分钟的 5700VRMS 隔离
    • 获得 CSA 认证，符合 IEC 60950-1、IEC 62368-1、IEC 61010-1 和 IEC 60601-1 终端设备标准
    • 获得 CQC 认证，符合 GB4943.1-2011 标准

2 应用

  • 隔离式交流/直流电源转换器
  • 服务器、电信、IT 和工业基础设施
  • 电机驱动和直流/交流光伏逆变器
  • LED 照明
  • 感应加热
  • 不间断电源 (UPS)
  • HEV 和 BEV 电池充电器

3 说明

UCC20520 是一款隔离式单输入、双通道栅极驱动器，其峰值拉电流为 4A，峰值灌电流为 6A。该器件设计用于驱动高达 5MHz 的功率 MOSFET、IGBT 和 SiC MOSFET，具有一流的传播延迟和脉宽失真度。

输入侧通过 5.7kVRMS 增强型隔离层与两个输出驱动器隔离，具有最少100V/ns的共模瞬态抗扰度 (CMTI) 。两个次级侧驱动器之间的内部功能隔离，支持的工作电压高达 1500 VDC。

该驱动器可用于具有可编程死区时间 (DT) 的半桥驱动器。禁用引脚在设为高电平时可同时关断两个输出，并在开路或接地时允许正常运行。作为一种故障安全措施，初级侧逻辑故障强制两个输出均为低电平。

此器件接受高达 25V 的 VDD 电源电压。3V 到 18V 的宽输入电压 VCCI 范围使得该驱动器适用于与模拟和数字控制器连接。所有电源电压引脚都具有欠压锁定 (UVLO) 保护功能。

凭借所有这些高级特性，UCC20520 能够在各种各样的电源应用中实现高效率、高电源密度和稳健性。

器件信息
零件编号封装(1)封装尺寸（标称值）
UCC20520DW SOIC (16)10.30mm × 7.50mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
GUID-0ED0BC3D-96C7-4EFE-8B3B-D8C6CB2CBE60-low.gif功能框图

4 Revision History

Changes from Revision * (November 2016) to Revision A (January 2022)

  • 更新了整个文档中的表格、图和交叉参考的编号格式Go
  • 将 #GUID-86CFDB16-D80B-4CCD-BC8A-F78C637D53E3/TITLE-SLUSCN0SLUSCJ97865 中的最大脉宽失真值从“5ns”更改为“6ns”Go
  • Changed maximum pulse width distortion specification in Section 6.10 from "5 ns" to "6 ns"Go
  • Updated bench test waveform colors for better readability only. No data or measurment changes. Go

5 Pin Configuration and Functions

GUID-83A186AF-684D-41F7-89EB-96945026CC41-low.gif Figure 5-1 DW Package, 16-Pin SOIC (Top View)
Table 5-1 Pin Functions
PIN TYPE1 DESCRIPTION
NAME NO.
DISABLE 5 I Disables both driver outputs if asserted high, enables if set low or left open. This pin is pulled low internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise immunity.
DT 6 I Programmable dead time function.

Tying DT to VCCI disables the DT function with dead time ≅ 0 ns. Leaving DT open sets the dead time to <15 ns. Placing a 500-Ω to 500-kΩ resistor (RDT) between DT and GND adjusts dead time according to: DT (in ns) = 10 × RDT (in kΩ). It is recommended to parallel a ceramic capacitor, ≥2.2-nF, with RDT to achieve better noise immunity.
GND 4 P Primary-side ground reference. All signals in the primary side are referenced to this ground.
NC 2 – No connection.
NC 7 – No connection.
NC 12 – No connection.
NC 13 – No connection.
OUTA 15 O Output of driver A. Connect to the gate of the A channel FET or IGBT. Output A is in phase with PWM input with a propagation delay
OUTB 10 O Output of driver B. Connect to the gate of the B channel FET or IGBT. Output B is always complementary to output A with a programmed dead time.
PWM 1 I PWM input has a TTL/CMOS compatible input threshold. This pin is pulled low internally if left open.
VCCI 3 P Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor located as close to the device as possible.
VCCI 8 P Primary-side supply voltage. This pin is internally shorted to pin 3.
VDDA 16 P Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL capacitor located as close to the device as possible.
VDDB 11 P Secondary-side power for driver B. Locally decoupled to VSSB using a low ESR/ESL capacitor located as close to the device as possible.
VSSA 14 P Ground for secondary-side driver A. Ground reference for secondary side A channel.
VSSB 9 P Ground for secondary-side driver B. Ground reference for secondary side B channel.
  1. I = input, O = output, I/O = input or output, FB = feedback, G = ground, P = power

 
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