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  • 具有单输入的UCC205204A/6A、5.7 kVRMS 隔离式双通道栅极驱动器

    • ZHCSFN1A November   2016  – January 2022 UCC20520

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  • 具有单输入的UCC205204A/6A、5.7 kVRMS 隔离式双通道栅极驱动器
  1. 1 特性
  2. 2 应用
  3. 3 说明
  4. 4 Revision History
  5. 5 Pin Configuration and Functions
  6. 6 Specifications
    1. 6.1  Absolute Maximum Ratings
    2. 6.2  ESD Ratings
    3. 6.3  Recommended Operating Conditions
    4. 6.4  Thermal Information
    5. 6.5  Power Ratings
    6. 6.6  Insulation Specifications
    7. 6.7  Safety-Related Certifications
    8. 6.8  Safety-Limiting Values
    9. 6.9  Electrical Characteristics
    10. 6.10 Switching Characteristics
    11. 6.11 Insulation Characteristics Curves
    12. 6.12 Typical Characteristics
  7. 7 Parameter Measurement Information
    1. 7.1 Propagation Delay and Pulse Width Distortion
    2. 7.2 Rising and Falling Time
    3. 7.3 PWM Input and Disable Response Time
    4. 7.4 Programable Dead Time
    5. 7.5 CMTI Testing
  8. 8 Detailed Description
    1. 8.1 Overview
    2. 8.2 Functional Block Diagram
    3. 8.3 Feature Description
      1. 8.3.1 VDD, VCCI, and Under Voltage Lock Out (UVLO)
      2. 8.3.2 Input and Output Logic Table
      3. 8.3.3 Input Stage
      4. 8.3.4 Output Stage
      5. 8.3.5 Diode Structure in UCC20520
    4. 8.4 Device Functional Modes
      1. 8.4.1 Disable Pin
      2. 8.4.2 Programmable Dead Time (DT) Pin
        1. 8.4.2.1 Tying the DT Pin to VCC
        2. 8.4.2.2 DT Pin Left Open or Connected to a Programming Resistor between DT and GND Pins
        3. 8.4.2.3 39
  9. 9 Application and Implementation
    1. 9.1 Application Information
    2. 9.2 Typical Application
      1. 9.2.1 Design Requirements
      2. 9.2.2 Detailed Design Procedure
        1. 9.2.2.1 Designing PWM Input Filter
        2. 9.2.2.2 Select External Bootstrap Diode and its Series Resistor
        3. 9.2.2.3 Gate Driver Output Resistor
        4. 9.2.2.4 Estimate Gate Driver Power Loss
        5. 9.2.2.5 Estimating Junction Temperature
        6. 9.2.2.6 Selecting VCCI, VDDA/B Capacitor
          1. 9.2.2.6.1 Selecting a VCCI Capacitor
          2. 9.2.2.6.2 Selecting a VDDA (Bootstrap) Capacitor
          3. 9.2.2.6.3 Select a VDDB Capacitor
        7. 9.2.2.7 Dead Time Setting Guidelines
        8. 9.2.2.8 Application Circuits with Output Stage Negative Bias
        9. 9.2.2.9 56
      3. 9.2.3 Application Curves
  10. 10Layout
    1. 10.1 Layout Guidelines
    2. 10.2 Layout Example
  11. 11Device and Documentation Support
    1. 11.1 Documentation Support
      1. 11.1.1 Related Documentation
    2. 11.2 接收文档更新通知
    3. 11.3 支持资源
      1. 11.3.1 Certifications
    4. 11.4 Trademarks
    5. 11.5 Electrostatic Discharge Caution
    6. 11.6 术语表
  12. 重要声明
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DATA SHEET

具有单输入的UCC205204A/6A、5.7 kVRMS 隔离式双通道栅极驱动器

本资源的原文使用英文撰写。 为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。 为确认准确性，请务必访问 ti.com 参考最新的英文版本（控制文档）。

1 特性

  • 单输入、双输出
  • 工作温度范围：–40 至125° C
  • 开关参数：
    • 19ns 典型传播延迟
    • 10ns 最小脉冲宽度
    • 5ns 最大延迟匹配
    • 6ns 最大脉宽失真
  • 共模瞬态抗扰度 (CMTI) 大于 100V/ns
  • 浪涌抗扰度高达 12.8kV
  • 隔离栅寿命大于 40 年
  • 4A 峰值拉电流、6A 峰值灌电流输出
  • TTL 和 CMOS 兼容输入
  • 3V 至 18V 输入 VCCI 范围，可与数字控制器和模拟控制器连接
  • 高达 25V 的 VDD 输出驱动电源
  • 可编程死区时间
  • 抑制短于 5ns 的输入脉冲和噪声瞬态
  • 快速禁用电源定序
  • 业界通用的宽体 SOIC-16 (DW) 封装
  • 安全相关及监管批准：
    • 符合 DIN V VDE V 0884-11:2017-01 标准的 8000VPK 隔离
    • 符合 UL 1577 标准且长达 1 分钟的 5700VRMS 隔离
    • 获得 CSA 认证，符合 IEC 60950-1、IEC 62368-1、IEC 61010-1 和 IEC 60601-1 终端设备标准
    • 获得 CQC 认证，符合 GB4943.1-2011 标准

2 应用

  • 隔离式交流/直流电源转换器
  • 服务器、电信、IT 和工业基础设施
  • 电机驱动和直流/交流光伏逆变器
  • LED 照明
  • 感应加热
  • 不间断电源 (UPS)
  • HEV 和 BEV 电池充电器

3 说明

UCC20520 是一款隔离式单输入、双通道栅极驱动器，其峰值拉电流为 4A，峰值灌电流为 6A。该器件设计用于驱动高达 5MHz 的功率 MOSFET、IGBT 和 SiC MOSFET，具有一流的传播延迟和脉宽失真度。

输入侧通过 5.7kVRMS 增强型隔离层与两个输出驱动器隔离，具有最少100V/ns的共模瞬态抗扰度 (CMTI) 。两个次级侧驱动器之间的内部功能隔离，支持的工作电压高达 1500 VDC。

该驱动器可用于具有可编程死区时间 (DT) 的半桥驱动器。禁用引脚在设为高电平时可同时关断两个输出，并在开路或接地时允许正常运行。作为一种故障安全措施，初级侧逻辑故障强制两个输出均为低电平。

此器件接受高达 25V 的 VDD 电源电压。3V 到 18V 的宽输入电压 VCCI 范围使得该驱动器适用于与模拟和数字控制器连接。所有电源电压引脚都具有欠压锁定 (UVLO) 保护功能。

凭借所有这些高级特性，UCC20520 能够在各种各样的电源应用中实现高效率、高电源密度和稳健性。

器件信息
零件编号封装(1)封装尺寸（标称值）
UCC20520DW SOIC (16)10.30mm × 7.50mm
(1) 如需了解所有可用封装，请参阅数据表末尾的可订购产品附录。
GUID-0ED0BC3D-96C7-4EFE-8B3B-D8C6CB2CBE60-low.gif功能框图

4 Revision History

Changes from Revision * (November 2016) to Revision A (January 2022)

  • 更新了整个文档中的表格、图和交叉参考的编号格式Go
  • 将 #GUID-86CFDB16-D80B-4CCD-BC8A-F78C637D53E3/TITLE-SLUSCN0SLUSCJ97865 中的最大脉宽失真值从“5ns”更改为“6ns”Go
  • Changed maximum pulse width distortion specification in Section 6.10 from "5 ns" to "6 ns"Go
  • Updated bench test waveform colors for better readability only. No data or measurment changes. Go

5 Pin Configuration and Functions

GUID-83A186AF-684D-41F7-89EB-96945026CC41-low.gif Figure 5-1 DW Package, 16-Pin SOIC (Top View)
Table 5-1 Pin Functions
PIN TYPE1 DESCRIPTION
NAME NO.
DISABLE 5 I Disables both driver outputs if asserted high, enables if set low or left open. This pin is pulled low internally if left open. It is recommended to tie this pin to ground if not used to achieve better noise immunity.
DT 6 I Programmable dead time function.

Tying DT to VCCI disables the DT function with dead time ≅ 0 ns. Leaving DT open sets the dead time to <15 ns. Placing a 500-Ω to 500-kΩ resistor (RDT) between DT and GND adjusts dead time according to: DT (in ns) = 10 × RDT (in kΩ). It is recommended to parallel a ceramic capacitor, ≥2.2-nF, with RDT to achieve better noise immunity.
GND 4 P Primary-side ground reference. All signals in the primary side are referenced to this ground.
NC 2 – No connection.
NC 7 – No connection.
NC 12 – No connection.
NC 13 – No connection.
OUTA 15 O Output of driver A. Connect to the gate of the A channel FET or IGBT. Output A is in phase with PWM input with a propagation delay
OUTB 10 O Output of driver B. Connect to the gate of the B channel FET or IGBT. Output B is always complementary to output A with a programmed dead time.
PWM 1 I PWM input has a TTL/CMOS compatible input threshold. This pin is pulled low internally if left open.
VCCI 3 P Primary-side supply voltage. Locally decoupled to GND using a low ESR/ESL capacitor located as close to the device as possible.
VCCI 8 P Primary-side supply voltage. This pin is internally shorted to pin 3.
VDDA 16 P Secondary-side power for driver A. Locally decoupled to VSSA using a low ESR/ESL capacitor located as close to the device as possible.
VDDB 11 P Secondary-side power for driver B. Locally decoupled to VSSB using a low ESR/ESL capacitor located as close to the device as possible.
VSSA 14 P Ground for secondary-side driver A. Ground reference for secondary side A channel.
VSSB 9 P Ground for secondary-side driver B. Ground reference for secondary side B channel.
  1. I = input, O = output, I/O = input or output, FB = feedback, G = ground, P = power

6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VCCI to GND –0.3 20 V
VDDA-VSSA, VDDB-VSSB –0.3 30 V
OUTA to VSSA, OUTB to VSSB –0.3 VVDDA+0.3, VVDDB+0.3 V
OUTA to VSSA, OUTB to VSSB, Transient for 200 ns –2 VVDDA+0.3, VVDDB+0.3 V
PWM, DIS, DT to GND –0.3 VVCCI+0.3 V
PWM Transient for 50 ns –5 VVCCI+0.3 V
VSSA-VSSB, VSSB-VSSA 1500 V
Junction temperature, TJ (2) –40 150 °C
Storage temperature, Tstg –65 150 °C
(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) To maintain the recommended operating conditions for TJ, see the Section 6.4.

6.2 ESD Ratings

VALUEUNIT
V(ESD)Electrostatic dischargeHuman-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)±4000V
Charged-device model (CDM), per JEDEC specification JESD22-C101(2)±1500
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)
MINMAXUNIT
VCCIVCCI Input supply voltage318V
VDDA, VDDBDriver output bias supply9.225V
TAAmbient Temperature–40125°C
TJJunction Temperature–40130°C

6.4 Thermal Information

THERMAL METRIC(1)UCC20520UNIT
DW-16 (SOIC)
RθJAJunction-to-ambient thermal resistance78.1°C/W
RθJC(top)Junction-to-case (top) thermal resistance11.1°C/W
RθJBJunction-to-board thermal resistance48.4°C/W
ψJTJunction-to-top characterization parameter12.5°C/W
ψJBJunction-to-board characterization parameter48.4°C/W
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application report, SPRA953.

6.5 Power Ratings

VALUEUNIT
PDPower dissipation by UCC20520DWVCCI = 18 V, VDDA/B = 12 V, PWM = 3.3 V, 3 MHz 50% duty cycle square wave 1-nF load1.05W
PDIPower dissipation by primary side of UCC20520DW0.05W
PDA, PDBPower dissipation by secondary driver side of UCC20520DW0.5W

6.6 Insulation Specifications

PARAMETERTEST CONDITIONSVALUEUNIT
CLRExternal clearance(1)Shortest terminal to terminal distance through air> 8mm
CPGExternal creepage(1)Shortest terminal to terminal distance across the package surface> 8mm
DTIDistance through insulationDistance through internal isolation (internal clearance)>21µm
CTIComparative tracking indexDIN EN 60112 (VDE 0303-11); IEC 60112> 600V
Material groupAccording to IEC 60664-1I
Overvoltage category per IEC 60664-1Rated mains voltage ≤ 600 VRMSI-IV
Rated mains voltage ≤ 1000 VRMSI-III
DIN V VDE 0884-10 (VDE V 0884-10): 2006-2012(2)
VIORMMaximum repetitive peak isolation voltageAC voltage (bipolar)2121VPK
VIOWMMaximum isolation working voltageTime dependent dielectric breakdown (TDDB) test, (See Figure 6-1)1500VRMS
2121VDC
VIOTMMaximum transient isolation voltageVTEST = VIOTM
t = 60 sec (qualification)
t = 1 sec (100% production)		8000VPK
VIOSMMaximum surge isolation voltage(3)Test method per IEC 60065, 1.2/50 µs waveform, VTEST = 1.6 × VIOSM = 12800 VPK (qualification)8000VPK
qpdApparent charge(4)Method a, After Input/Output safety test subgroup 2/3. Vini = VIOTM, tini = 60s;

Vpd(m) = 1.2 X VIORM = 2545 VPK, tm = 10s

<5pC
Method a, After environmental tests subgroup 1. Vini = VIOTM, tini = 60s;

Vpd(m) = 1.6 X VIORM = 3394 VPK, tm = 10s

<5

Method b1; At routine test (100% production) and preconditioning (type test)

Vini = VIOTM; tini = 1s;

Vpd(m) = 1.875 * VIORM = 3977 VPK , tm = 1s

<5
CIOBarrier capacitance, input to output(5)VIO = 0.4 sin (2πft), f =1 MHz1.2pF
RIOIsolation resistance, input to outputVIO = 500 V at TA = 25°C> 1012Ω
VIO = 500 V at 100°C ≤ TA ≤ 125°C> 1011
VIO = 500 V at TS =150°C> 109
Pollution degree2
Climatic category40/125/21
UL 1577
VISOWithstand isolation voltageVTEST = VISO = 5700 VRMS, t = 60 sec. (qualification),

VTEST = 1.2 × VISO = 6840VRMS, t = 1 sec (100% production)

5700VRMS
(1) Creepage and clearance requirements should be applied according to the specific equipment isolation standards of an application. Care should be taken to maintain the creepage and clearance distance of a board design to ensure that the mounting pads of the isolator on the printed-circuit board do not reduce this distance. Creepage and clearance on a printed-circuit board become equal in certain cases. Techniques such as inserting grooves and/or ribs on a printed circuit board are used to help increase these specifications.
(2) This coupler is suitable for basic electrical insulation only within the maximum operating ratings. Compliance with the safety ratings shall be ensured by means of suitable protective circuits.
(3) Testing is carried out in air or oil to determine the intrinsic surge immunity of the isolation barrier.
(4) Apparent charge is electrical discharge caused by a partial discharge (pd).
(5) All pins on each side of the barrier tied together creating a two-terminal device.

6.7 Safety-Related Certifications

VDECSAULCQC
Certified according to DIN VDE V 0884-10 (VDE V 0884-10):2006-12 and DIN EN 60950-1 (VDE 0805 Teil 1):2011-01Approved under CSA Component Acceptance Notice 5A, IEC 60950-1 and IEC 60601-1Certified according to UL 1577 component recognition programCertified according to
GB 4943.1-2011
Reinforced insulation maximum transient isolation voltage,
8000 VPK;
maximum repetitive peak isolation voltage,
2121 VPK;
maximum surge isolation voltage,
8000 VPK		Reinforced insulation per CSA 60950-1-07+A1+A2 and IEC 60950-1 2nd Ed. Single protection,
5700 VRMS		Reinforced insulation,
Altitude ≤ 5000 m,
Tropical climate, 400 VRMS maximum working voltage
Certification number:
40040142		Agency qualification plannedFile number:
E181974		Certification number:
CQC16001155011

6.8 Safety-Limiting Values

Safety limiting intends to prevent potential damage to the isolation barrier upon failure of input or output circuitry. A failure of the I/O can allow low resistance to ground or the supply and, without current limiting, dissipate sufficient power to overheat the die and damage the isolation barrier potentially leading to secondary system failures.
PARAMETERTEST CONDITIONSSIDEMINTYPMAXUNIT
ISSafety output supply currentRθJA = 78.1°C/W, VDDA/B = 12 V, TA = 25°C, TJ = 150°C

See Figure 6-2

DRIVER A, DRIVER B64mA
RθJA = 78.1°C/W, VDDA/B = 25 V, TA = 25°C, TJ = 150°CDRIVER A, DRIVER B31mA
PSSafety supply powerRθJA = 78.1°C/W, TA = 25°C, TJ = 150°C

See Figure 6-3

INPUT50mW
DRIVER A775
DRIVER B775
TOTAL1600
TSSafety temperature150°C

The maximum safety temperature is the maximum junction temperature specified for the device. The power dissipation and junction-to-air thermal impedance of the device installed in the application hardware determines the junction temperature. The assumed junction-to-air thermal resistance in the Section 6.4 table is that of a device installed on a High-K test board for leaded surface mount packages. The power is the recommended maximum input voltage times the current. The junction temperature is then the ambient temperature plus the power times the junction-to-air thermal resistance.

6.9 Electrical Characteristics

VVCCI = 3.3 V or VVCCI = 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted)
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
SUPPLY CURRENTS
IVCCIVCCI quiescent currentDISABLE = VCCI1.52.0mA
IVDDA,
IVDDB		VDDA and VDDB quiescent currentDISABLE = VCCI1.01.8mA
IVCCIVCCI operating current(f = 500 kHz) current per channel, COUT = 100 pF2.5mA
IVDDA,
IVDDB		VDDA and VDDB operating current(f = 500 kHz) current per channel, COUT = 100 pF2.5mA
VCCI SUPPLY UNDERVOLTAGE LOCKOUT THRESHOLDS
VVCCI_ONRising threshold VCCI_ON2.552.72.85V
VVCCI_OFFFalling threshold VCCI_OFF2.352.52.65V
VVCCI_HYSThreshold hysteresis0.2V
VDDA/VDDB SUPPLY UNDERVOLTAGE LOCKOUT THRESHOLDS
VVDDA_ON,
VVDDB_ON		Rising threshold VDDA_ON, VDDB_ON88.59V
VVDDA_OFF,
VVDDB_OFF		Falling threshold VDDA_OFF, VDDB_OFF7.588.5V
VVDDA_HYS,
VVDDB_HYS		Threshold hysteresis0.5V
PWM AND DISABLE
VPWMH, VDISHInput high voltage1.61.82V
VPWML, VDISLInput low voltage0.811.2V
VPWM_HYS, VDIS_HYSInput hysteresis0.8V
VPWMNegative transient, ref to GND, 50 ns pulseNot production tested, bench test only–5V
OUTPUT
IOA+, IOB+Peak output source currentCVDD = 10 µF, CLOAD = 0.18 µF, f = 1 kHz, bench measurement4A
IOA-, IOB-Peak output sink currentCVDD = 10 µF, CLOAD = 0.18 µF, f = 1 kHz, bench measurement6A
ROHA, ROHBOutput resistance at high stateIOUT = –10 mA, TA = 25°C, ROHA, ROHBdo not represent drive pull-up performance. See tRISE in Section 6.10 and Section 8.3.4 for details.5Ω
ROLA, ROLBOutput resistance at low stateIOUT = 10 mA, TA = 25°C0.55Ω
VOHA, VOHBOutput voltage at high stateVVDDA, VVDDB = 12 V, IOUT = –10 mA, TA = 25°C11.95V
VOLA, VOLBOutput voltage at low stateVVDDA, VVDDB = 12 V, IOUT = 10 mA, TA = 25°C5.5mV
DEADTIME AND OVERLAP PROGRAMMING
Dead timePull DT pin to VCCI0ns
DT pin is left open, min spec characterized only, tested for outliers815ns
RDT = 20 kΩ160200240ns

6.10 Switching Characteristics

VVCCI = 3.3 V or 5 V, 0.1-µF capacitor from VCCI to GND, VVDDA = VVDDB = 12 V, 1-µF capacitor from VDDA and VDDB to VSSA and VSSB, TA = –40°C to +125°C, (unless otherwise noted).
PARAMETERTEST CONDITIONSMINTYPMAXUNIT
tRISEOutput rise time, 20% to 80% measured pointsCOUT = 1.8 nF 616ns
tFALLOutput fall time, 90% to 10% measured pointsCOUT = 1.8 nF712ns
tPWminMinimum pulse widthOutput off for less than minimum, COUT = 0 pF20ns
tPDHLPropagation delay from INx to OUTx falling edges1930ns
tPDLHPropagation delay from INx to OUTx rising edges1930ns
tPWDPulse width distortion |tPDLH – tPDHL|6ns
tDMPropagation delays matching between VOUTA, VOUTBf = 100 kHz5ns
CMTIStatic common-mode transient immunity (See Section 7.5)Slew rate of GND versus VSSA and VSSB, PWM is tied to GND or VCCI100V/ns

6.11 Insulation Characteristics Curves

GUID-B2B7DF73-0317-40D0-8B52-F5A2E15730C1-low.gifFigure 6-1 Reinforced Isolation Capacitor Life Time Projection
GUID-F87E4121-96D8-4477-82C9-5A818DDA5C67-low.gifFigure 6-2 Thermal Derating Curve for Safety-Related Limiting Current (Current in Each Channel with Both Channels Running Simultaneously)
GUID-2C264EF8-48F9-4DF8-B4DF-515925852DE5-low.gifFigure 6-3 Thermal Derating Curve for Safety-Related Limiting Power

6.12 Typical Characteristics

VDDA = VDDB= 12 V, VCCI = 3.3 V, TA = 25°C, No load unless otherwise noted.

GUID-7EB1668B-2900-4653-AE43-CE51C1FD0002-low.gif
No load
Figure 6-4 Per Channel Current Consumption vs. Frequency
GUID-707C6271-E5A7-4CAD-87B9-58CADD49CA8B-low.gif
CLOAD = 10 nF
Figure 6-6 Per Channel Current Consumption (IVDDA/B) vs. Frequency
GUID-3CA99BF4-A386-48FF-B641-CBCE792188EF-low.gif
No load Input low No switching
Figure 6-8 Per Channel (IVDDA/B) Quiescent Supply Current vs Temperature
GUID-5AB3A7AE-C432-4139-8B0C-29F86A385FCD-low.gif
VDD = 12 V
Figure 6-10 Rising and Falling Times vs. Load
GUID-CD90CB71-91B4-46B1-B657-3F8E65F52EB8-low.gifFigure 6-12 Propagation Delay vs. Temperature
GUID-A853C500-8421-4072-905D-24732854F47F-low.gifFigure 6-14 Pulse Width Distortion vs. Temperature
GUID-0B87720F-8A64-40FC-AFC9-D203DA631198-low.gifFigure 6-16 Propagation Delay Matching (tDM) vs. Temperature
GUID-9F2AC1E7-D2DB-48B6-BBBE-605DD3FF85E8-low.gifFigure 6-18 VDD UVLO Threshold vs. Temperature
GUID-665D0494-BB4C-492D-863B-CDEF64FFC04C-low.gifFigure 6-20 PWM/DIS Low Threshold
GUID-8CBF6142-44F1-4E82-9F0F-3057AA63C3EE-low.gifFigure 6-22 Dead Time vs. Temperature
GUID-2AA51C59-083E-474A-A495-A0671403EF5A-low.gifFigure 6-24 Typical Output Voltage
GUID-693E9ECB-F4C4-4ED7-8501-51FB53CB3628-low.gif
CLOAD = 1 nF
Figure 6-5 Per Channel Current Consumption (IVDDA/B) vs. Frequency
GUID-6D27E1DF-7201-48B9-AD96-7C68BC255E4A-low.gif
No load
Figure 6-7 Per Channel (IVDDA/B) Supply Current Vs. Temperature
GUID-3B962825-9B0F-4022-8F5C-DF92F350768A-low.gif
No load DIS is high No switching
Figure 6-9 IVCCI Quiescent Supply Current vs Temperature
GUID-0D432C31-B541-4311-A2AF-73A5D666E38C-low.gifFigure 6-11 Output Resistance vs. Temperature
GUID-107B703F-74EB-4D6A-A4A1-5342AC00C225-low.gifFigure 6-13 Propagation Delay vs. VCCI
GUID-06E215B2-8158-469E-B7AF-BF1B829565AF-low.gifFigure 6-15 Propagation Delay Matching (tDM) vs. VDD
GUID-DA83523C-A178-46DC-9C75-C50C0E1C5545-low.gifFigure 6-17 VDD UVLO Hysteresis vs. Temperature
GUID-5EEC6B3A-7BCC-4D87-B2BD-B71EB938BEC3-low.gifFigure 6-19 PWM/DIS Hysteresis vs. Temperature
GUID-88A87A1A-CC15-4AE6-99B5-164F6EECF52F-low.gifFigure 6-21 PWM/DIS High Threshold
GUID-8F93F44E-F172-499E-9BB6-DDEDBE5C9C24-low.gifFigure 6-23 Dead Time Matching vs. Temperature

7 Parameter Measurement Information

 
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